Diffusion Of Boron Or Silicon Patents (Class 148/DIG34)
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Patent number: 5925574Abstract: A method of producing a bipolar transistor composed of collector, base and emitter regions disposed sequentially on a semiconductor substrate. According to the method, a semiconductor layer is deposited on the collector region, the semiconductor layer is cleaned to expose an active surface, an impurity source gas is applied to the exposed active surface while heating the substrate to form an impurity adsorption layer, the impurity is diffused into the semiconductor layer to form the base region, another semiconductor layer is deposited on the base region, this semiconductor layer is cleaned to expose an active surface, another impurity source gas is applied to the exposed active surface while heating the substrate to form another impurity adsorption layer, and impurity is diffused into the semiconductor layer to from the impurity adsorption layer to form the emitter region.Type: GrantFiled: April 10, 1992Date of Patent: July 20, 1999Assignee: Seiko Instruments Inc.Inventors: Kenji Aoki, Tadao Akamine, Yoshikazu Kojima
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Patent number: 5674777Abstract: The present invention is related to a method for fabricating a silicon electronic device having a boron diffusion source layer, includes steps of: a) providing a silicon substrate; b) depositing a silicon layer on said silicon substrate; and c) growing a silicon-boron binary compound layer on said silicon layer as said boron diffusion source. When the Si-B layer is formed by a UHV/CVD process according to the present invention, the boron concentration in the Si-B binary compound layer will be extraordinary high (up to 1.times.10.sup.21 to 5.times.10.sup.22 atoms/cm.sup.3).Type: GrantFiled: December 14, 1995Date of Patent: October 7, 1997Assignee: National Science CouncilInventors: Tung-Po Chen, Tan-Fu Lei, Chun-Yen Chang
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Patent number: 5612245Abstract: An improved method of manufacturing a semiconductor device, especially suitable for a p-channel MOS transistor is disclosed. The method includes the steps of forming a gate oxide film over the surface of a semiconductor substrate in a region where a p-channel MOS transistor is to be formed, forming a polysilicon film over the gate oxide film, in order to construct a gate electrode, forming a film of an amorphous material over the polysilicon film and implanting ions of a p-type impurity, especially elemental boron atoms, into the polysilicon film, through the film of amorphous material.Type: GrantFiled: May 3, 1995Date of Patent: March 18, 1997Assignee: Kabushiki Kaisha ToshibaInventor: Yasuyuki Saito
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Patent number: 5401674Abstract: A method is provided for reducing growth of silicide and the temperatures necessary to produce silicide. Germanium is implanted at a concentration peak density depth below the midline and above the lower surface of a metal layer receiving the implant. Subsequent anneal causes germanide to occupy an area above growing silicide such that consumption of silicon atoms is reduced, and that silicide is formed to a controlled thickness.Type: GrantFiled: June 10, 1994Date of Patent: March 28, 1995Assignee: Advanced Micro DevicesInventors: Mohammed Anjum, Ibrahim Burki, Craig W. Christian
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Patent number: 5366922Abstract: The method of producing a CMOS transistor device. A pair of device regions are formed in separated relation from each other by a field oxide film on a pair of corresponding well regions formed in a semiconductor substrate. A gate insulating film and a gate electrode is sequentially formed on each of the device regions. The gate insulating film is removed through a mask of the patterned gate electrode to expose a silicon active surface at least in one of the device regions. A diborane gas containing P type impurity of boron is applied to the silicon active surface to form thereon a boron absorption film. N type impurity of arsenic is doped into the other device region by ion implantation to form N type of source and drain regions while masking the one device region. The boron is diffused from the adsorption film into the one device region to form P type of source and drain regions by annealing of the substrate.Type: GrantFiled: November 22, 1993Date of Patent: November 22, 1994Assignee: Seiko Instruments Inc.Inventors: Kenji Aoki, Naoto Saito
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Patent number: 5350709Abstract: A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semiconductor, the sample is subjected to at least one heat treatment to cause silicon in the SiOx film to diffuse into the Group III-V compound semiconductor, thereby forming a doped layer. Using this doped layer forming method, field-effect transistors, diodes, resistive layers, two-dimensional electron gas or one-dimensional quantum wires, zero-dimensional quantum boxes, electron wave interference devices, etc. are fabricated.Type: GrantFiled: June 10, 1993Date of Patent: September 27, 1994Assignee: Sanyo Electric Co., Ltd.Inventors: Yasoo Harada, Shigeharu Matsushita, Satoshi Terada, Emi Fujii, Takashi Kurose, Takayoshi Higashino, Takashi Yamada, Akihito Nagamatsu, Daijirou Inoue, Kouji Matsumura
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Patent number: 5278096Abstract: A method of forming p.sup.+ transistor gates is disclosed. A polysilicon layer is covered with an amorphous silicide layer which prevents penetration of p-type dopants through the gate oxide. The silicide may be covered by a dielectric which is formed at a temperature low enough to prevent crystallization of the silicide, a p-type dopant species is directed at the silicide layer. Subsequently an anneal is performed at a temperature high enough to cause a substantial amount of the p-type dopant to move to the polysilicon layer.Type: GrantFiled: December 23, 1991Date of Patent: January 11, 1994Assignee: AT&T Bell LaboratoriesInventors: Kuo-Hua Lee, Chen-Hua D. Yu
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Patent number: 5273934Abstract: A doped region (14) is produced in a substrate (11) of silicon by diffusion of dopant from a doped glass layer (13) that is arranged on an intermediate layer (12) situated on the substrate (11) . The dopant concentration in the doped region (14) is thereby limited by the intermediate layer (12). The doped glass layer (13) is particularly produced by chemical vapor deposition of (B(OSi(CH.sub.3).sub.3).sub.3).Type: GrantFiled: May 11, 1992Date of Patent: December 28, 1993Assignee: Siemens AktiengesellschaftInventors: Karl Ehinger, Michael Bianco, Helmut Klose
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Patent number: 5242741Abstract: In the boronizing of a ferrous sintered material, the porosity of the surface to be boronized is reduced, while the interior of the ferrous sintered material is kept essentiall as sintered. The boron phase is selectively on the surface having a low porosity, resistance are attained.Type: GrantFiled: October 21, 1992Date of Patent: September 7, 1993Assignee: Taiho Kogyo Co., Ltd.Inventors: Eiji Sugiyama, Motoshi Hayashi
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Patent number: 5208185Abstract: In a boron diffusion process, a multiplicity of semiconductor wafers and pyrolytic boron nitride dopant disks are placed in a diffusion tube kept in an inert atmosphere at a high temperature, and boron diffusion is performed with hydrogen injection, the initial concentration of hydrogen in the diffusion tube being a very low range of 0.05% by volume at maximum. The result is that it is possible to improve dispersion of sheet resistivity (.rho.s) of the silicon wafer surface remarkably and to suppress occurrence of lattice defects.Type: GrantFiled: March 17, 1992Date of Patent: May 4, 1993Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Yoshiyuki Mori, Yukiharu Kitazawa, Masahide Kojima, Tomoyuki Sakai, Eiichi Nishijo, Nobuhiro Tsuda, Tadayuki Ebe
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Patent number: 5192409Abstract: A material for high-vacuum vessels characterized by depositing a mixture film of stainless steel and boron nitride on the surface of a metal or an alloy through the sputtering process, and heating and precipitating hexagonal boron nitride onto the surface thereof.Type: GrantFiled: April 3, 1992Date of Patent: March 9, 1993Assignee: National Research Institute For MetalsInventors: Masahiro Tosa, Kazuhiro Yoshihara
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Patent number: 5183777Abstract: A method of forming a shallow junction comprises the step of: forming a film including a hydrogen compound with one element selected from the group of boron, phosphorus arsenic to a thickness of several atom layers to 1000 .ANG. on a silicon substrate and annealing the film, whereby an impurity region having a depth of 1000 .ANG. or less and an impurity concentration of 10.sup.18 to 10.sup.21 cm.sup.-3 is formed in the surface layer of the silicon layer.Type: GrantFiled: September 13, 1991Date of Patent: February 2, 1993Assignee: Fujitsu LimitedInventors: Masahiko Doki, Michiko Takei
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Patent number: 5141895Abstract: A semiconductor device is formed by a process in which a diffusant penetration layer and a diffusant source layer containing a boron dopant are formed overlaying the surface of a semiconductor substrate. The diffusant source layer is annealed to cause the boron dopant to controllably diffuse through the diffusant penetration layer to the semiconductor substrate to form a doped region at the surface. The diffusant source layer and the diffusant penetration layer are removed and a gate insulator is formed on the substrate surface overlaying the doped region. An N doped gate electrode is then formed overlaying the gate insulator.Type: GrantFiled: January 11, 1991Date of Patent: August 25, 1992Assignee: Motorola, Inc.Inventors: James R. Pfiester, Howard C. Kirsch
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Patent number: 5086016Abstract: A contact is provided in a self-aligned manner to a doped region a semiconductor substrate by first forming a layer of a transition metal-boride compound over a selected region on the substrate. A layer of a transition metal-nitride compound is formed over the layer of transition metal-boride compound, and the structure is heated to drive dopant from the layer of transition metal-boride compound into the substrate. The transition metal-boride/transition metal nitride layers are patterned to leave a contact to the doped region.Type: GrantFiled: October 31, 1990Date of Patent: February 4, 1992Assignee: International Business Machines CorporationInventors: Stephen B. Brodsky, Rajiv V. Joshi, John S. Lechaton, James G. Ryan, Dominic J. Schepis
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Patent number: 5047366Abstract: A method of diffusing Si into compound semiconductor from a Si film provided on a surface region of the compound semiconductor, wherein the diffusion is conducted with providing a diffusion stopper layer at a position of predetermined depth from the surface of the compound semiconductor, which stopper layer has a lower diffusion speed than that of the compound semiconductor.A compound semiconductor device includes a compound semiconductor substrate, a diffusion stopper layer provided on the semiconductor substrate, a compound semiconductor layer provided on the diffusion stopper layer, a Si film provided on the semiconductor layer, and Si diffusion regions into which Si is diffused from the Si film so as to reach the interface between the diffusion stopper layer and the semiconductor substrate.Type: GrantFiled: October 28, 1988Date of Patent: September 10, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takashi Murakami
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Patent number: 4916090Abstract: A method for manufacturing a amorphous silicon thin film transistor comprises exposing an morphous silicon layer situated between a source electrode and a drain electrode to a gas phase atmosphere having a gas containing an impurity forming an acceptor, then activating said impurity with an electric field or light energy and doping the activated impurity into said amorphous silicon layer. The gas may be a hydrogen compound and it may include an oxidizing gas.Type: GrantFiled: March 13, 1989Date of Patent: April 10, 1990Assignees: Nippon Precision Circuits Ltd., Seikosha Co., Ltd.Inventors: Noboru Motai, Yoshihisa Ogiwara, Yasunari Kanda
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Patent number: 4824798Abstract: A thin film bilayer composite source comprises a deposited impurity source layer, e.g. Si or Sb, heavily doped with a diffusion enabling agent, e.g. As, and capped with a passivating layer, e.g. Si.sub.3 N.sub.4, SiO.sub.2, AlN or SiO.sub.x N.sub.y. In a preferred embodiment, a thin film bilayer composite source comprises a Si layer on the surface of said structure vapor deposited at a temperature in excess of 500.degree. C. in the presence of a source of As to hevily dope the layer in the range of 5%-20% atomic weight and a thin cap layer of Si.sub.3 N.sub.4 deposited on the Si layer at a temperature in excess of 500.degree. C. having a thickness only sufficient to prevent the outdiffusion of Ga and As, which thickness may be about 400 .ANG.-700 .ANG.. An important aspect of the employment of this bilayer composite source as a diffusion source for III-V structures is that the composite source is initially deposited at high temperatures, above 500.degree.0 C., i.e.Type: GrantFiled: November 5, 1987Date of Patent: April 25, 1989Assignee: Xerox CorporationInventors: Robert D. Burnham, Robert L. Thornton
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Patent number: 4640004Abstract: A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.Type: GrantFiled: April 13, 1984Date of Patent: February 3, 1987Assignee: Fairchild Camera & Instrument Corp.Inventors: Michael E. Thomas, Madhukar B. Vora, Ashok K. Kapoor