Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

Abstract: The temperature of the front heater is set to a higher value than the set temperature of the center heater and the temperature of the rear heater is set to a lower value than the set temperature of the center heater to thereby provide such a temperature gradient that the temperature of a center heater region gradually rises from the rear side toward the front side and the impurity diffusion is accelerated under the temperature gradient, whereby it is possible to compensate for the decrease in the quantity of the diffused impurity caused by the lowering of the impurity concentration of the impurity gas gradually from the rear side toward the front side, so that the impurity is uniformly diffused into the wafers located in the core pipe.

Abstract: An LPCVD deposition process for depositing doped thin films on a substrate is provided. The process may be performed in a LPCVD reaction chamber at elevated temperatures and reduced pressures. The process is especially suited to the deposition and doping of chemically incompatible deposition species and dopants such as polysilicon and arsenic. A deposition gas (e.g. silane) and a dopant gas (e.g. arsine) are thermally decomposed in the reaction chamber. During the deposition process the gas flows are pulsed relative to one another in some manner. This pulsed gas flows form a multi-layer stack which includes alternating deposition layers and doping layers. The dopants in the doping layer are then diffused during a subsequent annealing step (or during subsequent processing) into the deposition layers to form a uniformly doped thin film.

Abstract: A wafer boat on which semiconductor wafers are placed is inserted into a process tube, and a process gas is supplied into the process tube to perform heat treating. In this case, prior to the heat treating, the process tube is evacuated to have a pressure lower than a pressure in the heat treating while a temperature in the process tube is kept to be higher than a temperature in the heat treating. After the heat treating is performed, the process tube is purged with an N.sub.2 gas.

Abstract: A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode of the field effect transistor and a collector electrode of the bipolar transistor are formed from a common electrode layer of a high impurity concentration, and in which the collector region of the bipolar transistor comprises a region of a high impurity concentration having a conductivity type the same as that of the collector region of the bipolar transistor.

Abstract: Gold is diffused into a silicon substrate by first depositing an ultrathin layer of gold on one of the main faces of the substrate and then by heating the substrate to a temperature range of about 300.degree.-850.degree. C., instead of to about 1000.degree. according to the prior art. Then, following the removal of the remaining gold layer from over the substrate, the latter is reheated to a higher temperature ranging from about 700.degree. C. to about 1000.degree. C. for activating the diffused gold. The gold diffusion at the reduced temperature serves to decrease the surface irregularities of the substrate as a result of gold-silicon alloy zones created at the interface between gold layer and silicon substrate during the thermal diffusion process.

Abstract: The invention relates to a method of manufacturing a Bi-CMOS semiconductor IC device in which the bipolar transistor structure contained therein has a flat PN plane junction between its base and emitter regions, said device having improved breakdown voltage characteristics.The improved method involves preparing a silicon substrate having a P-type base region formed in an N-type collector region, forming a thick silicon oxide layer over the suface of a bipolar transistor region on said substrate, selectively removing the silicon oxide layer to form a first window exposing a part of the collector region and a second window exposing a part of the base region, diffusing phosporus atoms into the base region and collector region through said first and second windows to form an emitter region in the base region and a collector contact in the collector region, subjecting the structure thus-obtained to an oxidation process in a wet oxygen atmosphere at a temperature of 940.degree. C..+-. 20.degree. C.

Abstract: The present invention relates to a semiconductor device and a method of producing the same. According to this method, a lower diffusion layer of a double isolation diffusion area is attached to a surface of a substrate, an epitaxial layer being formed on the lower diffusion layer, the lower diffusion layer being largely outdiffused upwardly in the epitaxial layer and simultaneously an element diffusion area being deeply diffused from a surface of the epitaxial layer, and then an upper diffusion layer of the double isolation diffusion area being shallowly diffused from the surface of the epitaxial layer. Thus, the lateral expansion of the upper diffusion layer of the double isolation diffusion area can be suppressed and the integrated extent can be improved.

Abstract: A method for fabricating isolated regions for a dielectric isolated complementary integrated circuit which avoids the difficulty of mask alignment and patterning on a deeply etched uneven surface of the substrate by aligning the patterns before etching and thereby forming p-type and n-type islands at the same time. A poly-silicon layer is grown on the surface of the substrate covering the islands and the substrate is removed from its back surface, leaving the islands embedded in the poly-silicon layer which becomes a new substrate.