Electric Field Patents (Class 148/DIG45)
  • Patent number: 5714396
    Abstract: A semiconductor structure having an edge termination feature wherein a first doped region and a second doped region are selectively formed in a semiconductor layer. The second doped region is coupled with the first doped region and has an impurity concentration less than that of the first doped region. An insulating layer is disposed over the semiconductor layer and over at least a portion of the second doped region. A conductive layer, having a coil-shaped configuration, is disposed over the insulating layer and is coupled to the semiconductor layer.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: February 3, 1998
    Assignee: Motorola, Inc.
    Inventors: Stephen Robb, Paul Groenig
  • Patent number: 5462886
    Abstract: A method of manufacturing a semiconductor element such as a thin film transistor or a photo diode, in which a voltage is applied to an organic insulating layer in the direction vertical to a substrate during a coating process of polyimide constituting the interlayer insulating layer formed over a semiconductor layer, a prebaking process for initial hardening which immediately follows the coating process, and a postbaking process after the pattern formation of the interlayer insulating layer.
    Type: Grant
    Filed: November 26, 1993
    Date of Patent: October 31, 1995
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Yoshihiko Sakai, Takayuki Yamada
  • Patent number: 5231049
    Abstract: A novel display screen structure and method of manufacturing such screens for use, for example, in large screen television displays. The process of the present invention is one which can be accomplished with no new materials, no critical geometric requirements such as critical separations and alignments and only low voltage drivers. The combination of these features results in a technology which can be easily scaled to large sizes to provide relatively low-cost large screens for televisions. An important step in a first embodiment of the present invention is the alignment of a large plurality of columnar-shaped light emitting diode slivers in an uncured optical epoxy by applying an electric field through a mixture of such slivers and epoxy and then curing the epoxy to effectively fix the light emitting diode slivers in that aligned configuration. In a second embodiment, the LED slivers are mixed with molten glass which is formed into elongated glass fibers.
    Type: Grant
    Filed: January 31, 1992
    Date of Patent: July 27, 1993
    Assignee: California Institute of Technology
    Inventors: Charles F. Neugebauer, Amnon Yariv
  • Patent number: 5116782
    Abstract: A method and apparatus for processing a fine pattern of a sample of one of an electronic device, molecular device and bioelement device, wherein a needle having a sharpened tip is disposed in opposed relation to the sample with a gap therebetween. A voltage is applied between the needle and the sample so as to enable a tunnel current and/or a field emission current to flow therebetween and the fine pattern is provided to correct the fine pattern by effecting at least one of removal, repositioning, annealing and film formation of at least one of individual atoms and individual molecules.
    Type: Grant
    Filed: December 22, 1989
    Date of Patent: May 26, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Yamaguchi, Keiya Saito, Tateoki Miyauchi
  • Patent number: 5079187
    Abstract: A method for processing semiconductor material for annealing or circuitizing purposes, includes establishing a high intensity light which is controlled at a high repetition rate, and exposing it toward the surface of the semiconductor material to process it in an improved manner. The high speed light is directed transversely to the surface of the material to be processed, only to a shallow depth.
    Type: Grant
    Filed: May 4, 1989
    Date of Patent: January 7, 1992
    Assignee: The Regents of the University of California
    Inventors: John F. Asmus, Ralph H. Lovberg
  • Patent number: 4966858
    Abstract: A method of fabricating a lateral semiconductor structure includes providing a semiconductor substrate and forming wells therein. Following formation of a dielectric layer on the substrate, field region openings are formed through which field regions are implanted into the substrate. The self-aligned formation of field oxidation regions to the field region openings then occurs and is followed by the formation of field plates on the field oxidation regions. A first active device region is then formed in said substrate, the formation of which is self-aligned to the field plates. This is followed by the formation of a second active device region in the first active device region which is also self-aligned to the field plates. The resulting structure allows for high speed devices that maintain consistently high current gain without sacrificing Early or breakdown voltages.
    Type: Grant
    Filed: November 2, 1989
    Date of Patent: October 30, 1990
    Assignee: Motorola, Inc.
    Inventors: Michael P. Masquelier, David N. Okada
  • Patent number: 4957772
    Abstract: An improved method for forming a functional deposited film by introducing a raw material gas into a substantially enclosed reaction chamber containing a substrate onto which the functional deposited film is to be deposited and coupling microwave energy from a source of microwave energy thereinto to thereby form a glow discharge plasma causing decomposition of the raw material gas whereby forming the functional deposited film on the substrate, the improvement comprising supplying microwave of a power equivalent to 1.1 times or more over that of microwave with which the deposition rate for the decomposed products from the raw material gas being deposited onto the substrate to be saturated to the raw material gas in the reaction chamber and regulating the inner pressure of the reaction chamber to a vacuum of 10 m Torr or less.
    Type: Grant
    Filed: December 21, 1988
    Date of Patent: September 18, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keishi Saitoh, Junichiro Hashizume, Shigehira Iida, Tetsuya Takei, Takayoshi Arai
  • Patent number: 4950624
    Abstract: An improved CVD apparatus for depositing a uniform film is shown. The apparatus comprises a reaction chamber, a substrate holder and a plurality of light source for photo CVD or a pair of electrode for plasma CVD. The substrate holder is a cylindrical cart which is encircled by the light sources, and which is rotated around its axis by a driving device. With this configuration, the substrates mounted on the cart and the surroundings can be energized by light or plasma evenly throughout the surfaces to be coated.
    Type: Grant
    Filed: May 16, 1988
    Date of Patent: August 21, 1990
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Inuzima, Shigenori Hayashi, Toru Takayama, Seiichi Odaka, Naoki Hirose
  • Patent number: 4914052
    Abstract: A process for the formation of a functional deposited film containing atoms belonging to the group III and V of the peridoical table as the main constituent atoms by introducing, into a film forming space for forming a deposited film on a substrate disposed therein, a group III compound (1) and a group IV compound (2) as the film-forming raw material and, if required, a compound (3) containing an element capable of controlling valence electrons for the deposited film as the constituent element each in a gaseous state, or in a state where at least one of such compounds is previously activated in an activation space disposed separately from the film forming space, while forming hydrogen atoms in excited state which cause chemical reaction with at least one of the compounds (1), (2) and (3) in the gaseous state or in the activated state in an activation space different from the film forming space and introducing them into the film-forming space, thereby forming the functional deposited film on the substrate, whe
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: April 3, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masahiro Kanai
  • Patent number: 4910163
    Abstract: Silicon epitaxial layers are grown on oriented silicon substrates using an open-tube Si-I.sub.2 chemical vapor deposition (CVD) reactor in the temperature range of 650.degree.-740.degree. C. Hydrogen and inert gases such as helium and argon are used as carrier gases, and the iodine/carrier gas mixture contacts the silicon source to produce silicon iodide which disproportionates to deposit pure silicon epitaxial layers on the substrate.
    Type: Grant
    Filed: June 9, 1988
    Date of Patent: March 20, 1990
    Assignee: University of Connecticut
    Inventor: Faquir C. Jain
  • Patent number: 4908329
    Abstract: A process for the formation of a functional deposited film containing atoms belonging to the group II and VI of the periodical table as the main constituent atoms by introducing, into a film forming space for forming a deposited film on a substrate disposed therein, a group II compound (1) and a group VI compound (2) as the film-forming raw material and, if required, a compound (3) containing an element capable of controlling valence electrons for the deposited film as the constituent element each in a gaseous state, or in a state where at least one of such compounds is previously activated in an activation space disposed separately from the film forming space, while forming hydrogen atoms in an excited state which cause chemical reaction with at least one of the compounds (1), (2) and (3) in the gaseous state or in the activated state in an activation space different from the film forming space and introducing them into the film-forming space, thereby forming the functional deposited film on the substrate, w
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: March 13, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Kanai, Tsutomu Murakami, Takayoshi Arai, Soichiro Kawakami
  • Patent number: 4900694
    Abstract: A process for the preparation of a multi-layers stacked junction typed thin film transister of which electric amplification factor (.beta.) at the time of the base electrode or the emitter electrode being grounded is about 10 and which has an excellent amplifying operation.
    Type: Grant
    Filed: March 21, 1988
    Date of Patent: February 13, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventor: Katsumi Nakagawa
  • Patent number: 4891330
    Abstract: A method of fabricating doped microcrystalline semiconductor alloy material which includes a band gap widening element through a glow discharge deposition process by subjecting a precursor mixture which includes a diluent gas to an a.c. glow discharge in the absence of a magnetic field of sufficient strength to induce electron cyclotron resonance.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: January 2, 1990
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Subhendu Guha, Stanford R. Ovshinsky
  • Patent number: 4889605
    Abstract: A plasma pinch system includes a fluid-jet pinch device for establishing a plasma source composed of a tenuous vapor preconditioning cloud surrounding a central narrow flowing fine stream of fluid under pressure. A discharge device is connected electrically to the fluid-jet pinch device for supplying an electrical flow through a portion of the fluid stream for establishing an incoherent light emitting plasma therealong. A method of using the plamsa pinch system for manufacturing semiconductors, includes exposing a semiconductor wafer to the incoherent light emitted by the plasma for either annealing or etching purposes.
    Type: Grant
    Filed: December 7, 1987
    Date of Patent: December 26, 1989
    Assignee: The Regents of the University of California
    Inventors: John F. Asmus, Ralph H. Lovberg
  • Patent number: 4870030
    Abstract: A remote plasma enhanced CVD apparatus and method for growing semiconductor layers on a substrate, wherein an intermediate feed gas, which does not itself contain constituent elements to be deposited, is first activated in an activation region to produce plural reactive species of the feed gas. These reactive species are then spatially filtered to remove selected of the reactive species, leaving only other, typically metastable, species which are then mixed with a carrier gas including constituent elements to be deposited on the substrate. During this mixing, the selected spatially filtered reactive species of the feed gas chemically interacts, i.e., partially dissociates and activates, in the gas phase, the carrier gas, with the process variables being selected so that there is no back-diffusion of gases or reactive species into the feed gas activation region. The dissociated and activated carrier gas along with the surviving reactive species of the feed gas then flows to the substrate.
    Type: Grant
    Filed: September 24, 1987
    Date of Patent: September 26, 1989
    Assignee: Research Triangle Institute, Inc.
    Inventors: Robert J. Markunas, Robert Hendry, Ronald A. Rudder
  • Patent number: 4800174
    Abstract: A method of producing an amorphous silicon semiconductor device makes use of a capacitance-coupled high-frequency glow-discharge semiconductor production apparatus which is equipped with a plurality of glow-discharge chambers each having a high-frequency electrode and a substrate holder opposing each other and means for supplying material gases to the glow-discharge chambers. A reaction of a material gas is effected in a first glow-discharge chamber, so as to form a semiconductor layer having a first conductivity type on a substrate introduced into the first glow-discharge chamber, and, after moving the substrate into a second glow-discharge chamber, a reaction of a material gas different from the material gas used in the first glow-discharge chamber is effected, thereby forming a semiconductor layer having a second conductivity type on the semiconductor layer of the first conductivity type.
    Type: Grant
    Filed: May 18, 1987
    Date of Patent: January 24, 1989
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Ishihara, Masatoshi Kitagawa, Takashi Hirao
  • Patent number: 4774196
    Abstract: A method of fusing two or more semiconductor wafers involves growing a silicon dioxide planar layer on each of two polished silicon wafer substrates, implanting positive ions in the silicon dioxide layers on one wafer and negative ions in the silicon dioxide layer on the other wafer. The source of positive ions is preferably cesium and the source of negative ions is preferably boron. The implanted grown oxide layers are brought into abutment so electrostatic attraction forces of the oppositely charged ions keep the wafers together while they are exposed to a relatively high temperature in an oxygen ambient to fuse the abutting surfaces together.
    Type: Grant
    Filed: August 25, 1987
    Date of Patent: September 27, 1988
    Assignee: Siliconix incorporated
    Inventor: Richard A. Blanchard
  • Patent number: 4671845
    Abstract: The present invention relates to the production of a stable insulator of a germanium and a device produced thereby. A germanium substrate is provided with a layer of silicon nitride deposited on one of the outer surfaces. Ionized nitrogen is implanted by an ion beam into the silicon nitride layer. An electric field is applied across the substrate and layer. In one embodiment the substrate and layer are annealed while maintaining the electric field, the electric field is removed, and a second annealing step grows the germanium nitride insulator layer subcutaneously. In another embodiment the subcutaneous germanium nitride insulator layer is grown during a single annealing step by continued application of the electric field to the substrate and the layer.
    Type: Grant
    Filed: March 22, 1985
    Date of Patent: June 9, 1987
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Max N. Yoder
  • Patent number: 4641420
    Abstract: Contacting an underlying region (e.g., doped silicon) through an access hole in an overlying dielectric layer (e.g., p-glass) formerly required flowing the dielectric to smooth the edges of the hole, so that aluminum would deposit smoothly into the hole. The present technique smoothes the side of the hole by forming a smoothing region on the sidewall. Improved aluminum coverage results, as well as allowing a smaller contact head, if desired. Improved contact resistance can be optionally provided by depositing a more conductive layer on the underlying layer prior to forming the sidewall.
    Type: Grant
    Filed: August 30, 1984
    Date of Patent: February 10, 1987
    Assignee: AT&T Bell Laboratories
    Inventor: Kuo-Hua Lee