Abstract: A process for manufacturing integrated circuits includes the following steps. First, an oxide layer is formed on at least one surface of two respective semiconductor material wafers. Next, a single semiconductor material wafer is obtained with a first layer and a second layer of semiconductor material and a buried oxide layer interposed therebetween starting from said two semiconductor material wafers by direct bonding of the oxide layers previously grown. The single wafer is submitted to a controlled reduction of the thickness of the first layer of semiconductor material and the top surface of the first layer of semiconductor material is lapped. Dopant impurities are selectively introduced into selected regions of the first layer of semiconductor material to form the desired integrated components.

Abstract: A semiconductor device with a high-density wiring structure, and a producing method for such device are provided. The semiconductor device has a substrate such as silicon, an insulation layer laminated on the substrate and having a groove or a hole, and a wiring of a conductive material formed in the groove or hole in the insulation layer. The wiring is formed by depositing a conductive material such as aluminum or an aluminum alloy in the groove or hole of the insulation layer by a CVD method utilizing alkylaluminum hydride gas and hydrogen. The groove or hole can be formed by an ordinary patterning method combined with etching.

Abstract: The present invention concerns a method for making an identification mark on a silicon surface. In a preferred embodiment, the identification mark formed on the silicon surface does not substantially score the silicon. A silicon or silicon dioxide surface coated with an insulating layer is marked by laser scribing, leaving an exposed area on the silicon or the silicon dioxide. The exposed area on the silicon wafer is preferably not marked by the laser scribing. The exposed silicon surface is then oxidized by dry or wet oxidizing. The silicon oxide can be subsequently removed to leave an etched mark. The method reduces or eliminates the formation of stresses and silicon slag at the etched mark that can cause defects and reduce yield.

Abstract: A method for separating a joined substrate type wafer, which wafer is composed of a pair of semiconductor substrates joined through an insulation film, utilizes dielectrics through simple processing steps. Trenches for separating a semiconductor substrate with dielectrics are dug from the surface of the substrate and a dielectrics film is deposited on the surface of the substrate including the trenches. Then poly-crystalline silicon is grown by CVD to a thickness of about 0.5 .mu.m, which is deep enough to fill the trenches. The process time for growing poly-crystalline silicon is shortened, and the processing step for removing the poly-crystalline silicon deposited on the unwanted areas is eliminated by growing the poly-crystalline silicon in the trenches but not on the crystalline surface of semiconductor regions based on the growth rate dependence of the poly-crystalline silicon on the crystallinity of the surface on which the poly-crystalline silicon is grown.

Abstract: A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface.

Abstract: Method for detaching chips in the silicon layer of a SOI substrate, wherein trenches are etched between the chips down to the insulating layer of the SOI substrate. Spacers for the passivation of SiO.sub.2 layers of the chips are produced. Finally, the chips are detached by etching the insulating layer off.

Abstract: A thin film forming method which comprises the steps of supporting a substrate to be treated, having a trench or an unevenness thereon, in a reaction vessel; introducing a reactive gas into the reaction vessel; activating the reactive gas to form a deposit species, the deposit species characterized by a phase diagram including a liquid phase region defined by a melting curve and an evaporation curve that intersect at a triple point; and forming a thin film containing at least a part of the deposit species on the substrate while retaining a pressure of the deposit species in the reaction vessel higher than the triple point of the phase diagram of the deposit species, and retaining a temperature of the substrate within the liquid phase region of the phase diagram of the deposit species.

Abstract: A semiconductor device including a layer formed without being affected by a stepped ground pattern and a method of fabricating the semiconductor device are disclosed. Cap portions (30) (insulating layers) formed over trenches (13) and covering doped polysilicon (5) have an inclined surface (26) which satisfies Y/X <5 where X is the length of the inclined surface (26) in a direction of the surface of a body (50) and Y is the height of the inclined surface (26) from the surface of the body (50). Formation of the insulating layers having the smooth inclined surface satisfying Y/X<5 permits a first main electrode to be formed nondefectively without being affected by the ground pattern including the insulating layers.

Abstract: A semiconductor device comprises a semiconductor substrate having a major surface, a trench device isolation region having a trench selectively formed to define at least one island region in the major surface of the semiconductor substrate and a filler insulatively formed within the trench, an elongated gate electrode insulatively formed over a central portion of the island region so that each of its both ends which are opposed to each other in the direction of its length overlaps the trench device isolation region, and source and drain regions formed within the island region on the both sides of the gate electrode. The surface of the trench device isolation region is formed lower than the major surface of the semiconductor substrate.

Abstract: A method for separating a joined substrate type wafer, which wafer is composed of a pair of semiconductor substrates joined through an insulation film, utilizes dielectrics through simple processing steps. Trenches for separating a semiconductor substrate with dielectrics are dug from the surface of the substrate and a dielectrics film is deposited on the surface of the substrate including the trenches. Then poly-crystalline silicon under layer is grown by CVD method to a thickness of about 0.5 .mu.m. Thereafter, a poly-crystalline silicon filler layer, which is deep enough to fill the trenches, is grown over the underlying poly-crystalline silicon under layer, followed by selectively removing the two poly-crystalline silicon layers from the surface of the substrate excluding the regions inside the trenches. An alternative embodiment contemplates depositing a second dielectrics film interposed between the poly-crystalline silicon under layer and the poly-crystalline silicon filler layer.

Abstract: There are disclosed a semiconductor device and a method for fabrication thereof. The semiconductor device comprises an insulating film for well isolation which electrically insulates N-well from P-well, the drain electrode of PMOS and the drain electrode of NMOS being adjacent to the trench for well isolation, and a conductive wire filling one contact hole which interconnects the drain electrodes of N-well with those of P-well. The semiconductor device is very reduced in size, and thus, high integration thereof can be achieved.

Abstract: An integrated circuit based on submicron technology is disclosed herein along with the way in which it is formed. The integrated circuit is comprised of an arrangement of different substances which are combined to form its body structure and which define within the body structure an array of electronic components including a diamond thin film coated trench arrangement. In one embodiment disclosed herein, the array of electronic component includes two such components which are in close proximity to and must be electrically isolated from one another and the diamond thin film coated trench arrangement serves to electrically isolate these two components from each other. In a second embodiment, the diamond thin film coated trench is specifically designed to serve as a capacitor forming part of, for example, a DRAM, a mixed signal circuit or a neuro-fuzzy circuit.

Abstract: A non-volatile memory cell and array of such cells is provided. The memory cell includes a single transistor floating gate cell fabricated on a sidewall of a silicon pillar etched into a silicon substrate. The memory cells are arranged in an array of rows extending in a bit line direction and columns extending in a word line direction. A substantially smaller cell and array size is realized by limiting the dimension of the pillar and the bit line in the word line direction to be the minimum line width as limited by the lithography.

Abstract: A method of fabricating a semiconductor device incorporates the steps of forming in succession a gate insulting film, a polycrystalline silicon film and a first insulating film on a semiconductor substrate surface, and etching a portion of the first insulating film, the polycrystalline silicon film and the gate insulating film to expose the semiconductor substrate. The exposed semiconductor substrate is etched to form a trench. The trench is then buried by depositing a second insulating film and thereafter a third insulating film. The second and third insulating films are then etched with the third insulating film being etched at a higher rate than the second insulating film. The polycrystalline silicon film is used as a stopper to leave behind the second and third insulating films in the trench. A fourth insulating film is deposited, and then etched again using the polycrystalline silicon film as a stopper. The side walls of the trench are thus coated with the fourth insulating film.

Abstract: The RC time constant of a semiconductor device is reduced by decreasing the capacitance C. The decrease in capacitance is achieved by replacing the interlayer silicon dioxide (dielectric constant of 4.0) with air (dielectric constant of 1.0). Alternatively, the air space can also be filled with another low dielectric constant material, such as an organic material having a dielectric constant in the range of about 2.2 to 3.4. In either case, the final effective dielectric constant of the device is lowered. As a result of lowering the effective dielectric constant, a smaller RC time constant is achieved, which results in higher device speed.

Abstract: The deposition of oxide over a semiconductor substrate to fill trenches provides for simpler isolation processing for semiconductor circuit fabrication. Both shallow and deep trenches are etched in a semiconductor substrate for the formation of both device isolation structures and well isolation structures. Oxide is then deposited using chemical vapor deposition over the substrate, filling both the shallow and deep trenches. The resulting oxide layer over the substrate is then planarized, thus forming shallow and deep trench isolation structures in the substrate.

Abstract: A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

Abstract: An isolation region structure of a semiconductor device and a method for fabricating the same using both a buried oxide isolation technique and a local oxidation of silicon technique, thereby capable of having an advantage of high integrity. In the isolation region structure, narrow trenches are filled only with a polysilicon film whereas wide trenches are filled with a field oxide film and a polysilicon film so as to isolate adjacent active regions from each other.

Abstract: Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.

Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.

Abstract: An object of the invention is to prevent the occurrence of breaking or short-circuiting of a wiring caused by a difference in level in an isolation trench area formed in an SOI substrate. An oxide film is formed for a pad on the main surface of an SOI layer formed on an insulating substrate, a silicon nitride film are formed and an SiO.sub.2 film in order, then an isolation trench reaching to the insulating substrate is by means of an R.I.E process using the SiO.sub.2 film as a mask. Thereafter an insulating film is formed on an inside wall of the isolation trench by means of thermal oxidation, the isolation trench is filled with polysilicon, the polysilicon is etched back while controlling the etching so that the top of the polysilicon in the isolation trench remains higher than the top of the silicon nitride film, an extra part of the polysilicon deposited on the surface of the substrate, is removed and then the SiO.sub.

Abstract: A method of making a gettering structure for dielectrically isolated wafer structures, such as bonded wafers. A getterer layer is deposited over the wafer having semiconductor regions isolated from each other by trenches. The polysilicon is etched back leaving the polysilicon on the sides of the regions. The polysilicon may be doped. The polysilicon is oxidized and a second layer of polysilicon may be deposited to fill voids in the trenches.

Abstract: The present invention provides a novel method of forming an isolation region comprising a trench isolation region and a selective oxidation film region involved in a semiconductor integrated circuit device. A silicon oxide film is deposited on a surface of a trench groove formed within a semiconductor bulk, followed by a deposition of a polycrystalline silicon material. The silicon oxide film within the trench groove is subjected to etching up to a predetermined depth so as to form a hollow portion. A polycrystalline silicon film is deposited within the hollow portion and on both surfaces of the polycrystalline silicon material and the semiconductor bulk. The polycrystalline silicon film within the hollow portion, the polycrystalline silicon material and the semiconductor bulk in the vicinity of the trench groove is subjected to selective oxidation so as to form a selective oxidation film region.

Abstract: A process useful for isolating active areas of semiconductor devices in which an isolation trench is created in a substrate, the isolation trench being lined with an oxidation barrier and filled with a thick film. An oxidation step is performed in which the thick film is oxidized. The oxidation is self-limiting as the oxidation barrier prevents the substrate surrounding the trench from being oxidized.

Abstract: An integrated circuit fabrication process for creating field oxide regions in a substrate is disclosed. In the process, masking layers of oxide, nitride and deposited silicon dioxide are formed on the substrate. A pattern that defines the field oxide regions in the substrate is introduced into the substrate through these masking layers. The field oxide region is bordered by steep sidewalls in a portion of the substrate and the masking layers overlying the substrate. A thin layer of oxide is grown on the exposed portion of the substrate, and a conformal second layer of nitride followed by a conformal layer of a polycrystalline material are formed over the substrate/mask structure. The polycrystalline layer is selectively removed, so that the only portion of the polycrystalline material that remains on the structure is the portion covering the sidewalls.

Abstract: An isolation structure is disclosed which isolates an active region (24) from other proximate active regions. The isolation structure utilizes the combination of a LOCOS structure (26) comprising bird's beak structure (26a) and (26b). A trench (34) is formed through the LOCOS structure (26). A channel stop implant region (40) is formed along the sidewalls of the trench (34). A trench plug (46) is used to fill the trench. The isolation structure thereby uses the isolation capabilities of trench isolation structures, but prevents the leakage currents common along trench sidewalls by isolating the trench sidewalls from the active region using the LOCOS structures.

Abstract: A method of making a fully self-aligned, planar, two phase charge coupled device comprises the steps of first forming upon a semiconductive substrate a uniform first insulative dielectric layer; then depositing and patterning in the form of a trench extending to the first insulative layer a second insulative layer; then implanting ions of a second conductivity type into the substrate, then patterning closely spaced strips of a first conductive layer on the first and second insulative layer, then further implanting ions of a second conductivity type in the regions between said first conductive strips, then depositing uniformly a second conductive layer electrically isolated from the first conductive strips, then entirely removing by uniform planarization those portions of the second conductive layer disposed over regions of the first conductive strips or over regions of the second insulative layer so as to form closely spaced, coplanar, alternating first and second electrically isolated conductive strips, then

Abstract: A thin film forming method which comprises the steps of supporting a substrate to be treated, having a trench or an unevenness thereon, in a reaction vessel; introducing a reactive gas into the reaction vessel; activating the reactive gas to form a deposit species, the deposit species characterized by a phase diagram including a liquid phase region defined by a melting curve and an evaporation curve that intersect at a triple point; and forming a thin film containing at least a part of the deposit species on the substrate while retaining a pressure in the reaction vessel higher than the triple point of the phase diagram of the deposit species, and retaining a temperature of the substrate within the liquid phase region of the phase diagram of the deposit species.

Abstract: A method for the fabrication of a trench isolation region (44) includes the deposition of first, second, and third oxidizable layers (28, 34, 42). The first oxidizable layer (28) is deposited to overlie the surface of a trench (12) formed in a semiconductor substrate (10). The first oxidizable layer (28) also fills a recess (26) formed in a masking layer (14), and resides adjacent to the upper surface of the trench (12). After oxidizing the first oxidizable layer (28), a second oxidizable layer (34) is deposited to fill the trench (12). A third oxidizable layer (42) is deposited to overlie the second oxidizable layer (34) and fills a remaining portion of the recess (26). An oxidation process is performed to oxidize oxidizable layer (42) and a portion of second oxidizable layer (34) to form a trench isolation region (44). In an alternative embodiment of the invention, a shallow isolation region (46) is formed in proximity to the trench isolation region ( 44).

Abstract: A method of forming shallow trench isolation with a nitride liner layer for devices in integrated circuits solves a problem of recessing the nitride liner that led to unacceptable voids in the trench filler material by using a liner thickness of less than 5 nm. A densification step of a pyrogenic oxide anneal at 800.degree. C. not only drives out impurities and achieves the same density as a conventional argon anneal at 1000.degree. C., but also drastically reduces the thermal load.

Abstract: Trenches having different profiles are formed in a material, such as a semiconductor substrate, by forming a resist pattern having windows with at least two different widths. An etchant, such as Fluorine, is implanted into portions of the semiconductor using an ion implantation technique. A tilt angle and an azimuth angle of the ion beam are chosen such that the Fluorine ions cannot pass through narrower resist windows but can pass through wider resist windows to impinge on the underlying semiconductor substrate. The semiconductor substrate is then subjected to an anisotropic etching process. Accordingly, the substrate regions exposed between the narrow-width resist windows are etched to produce trenches having highly vertical profiles. The substrate regions exposed by the wide-width resist windows, including the regions having implanted etchant ions, are preferentially etched to produce trenches having tapered profiles.

Abstract: A channel stop is self-aligned with a trench sidewall of a trench-isolated semiconductor architecture, so that there is no alignment tolerance between the stop and the trench wall. An initial masking layer, through which the trench pattern is to be formed in a semiconductor island layer, is used as a doping mask for introducing a channel stop dopant into a surface portion of the semiconductor layer where the trench is to be formed. The lateral diffusion of the dopant beneath the oxide and adjacent to the trench aperture defines the eventual size of the channel stop. The semiconductor layer is then anisotropically etched to form a trench to a prescribed depth, usually intersecting the underlying semiconductor substrate. Because the etch goes through only a portion of the channel stop diffusion, leaving that portion which has laterally diffused beneath-the oxide mask, the channel stop is self-aligned with the sidewall of the trench.

Abstract: A method for forming a semiconductor on insulator device is provided that begins with an outer semiconductor layer (16). Trenches (12) of a predetermined depth are formed in outer semiconductor layer (16). An insulator layer (20) is formed outwardly from outer semiconductor layer (16). A mesa (18a) having a predetermined thickness is formed by removing portions of outer semiconductor layer (16) to expose a working surface such that mesa (18a) has a thickness substantially equal to the predetermined depth of the trenches (12) after the working surface is exposed.

Abstract: A method for fabricating a trench buried-bit line mask ROM includes the steps: firstly, longitudinally coating a plurality of spaced photo-resist strips on a silicon well surface thus dividing the silicon well surface into a plurality longitudinally spaced strip regions; secondly, etching into each of the silicon strip regions a predetermined depth and forming a longitudinal trench therein; thirdly, depositing a strip of N+ ions along each of the longitudinal trenches such that each strip of N+ ions constitutes a bit line of the ROM; fourthly, removing the photoresist strips from the silicon well surface and leaving a silicon ridge between each two trenches such that an inverse U-shaped channel is defined substantially along periphery of each silicon ridge; fifthly, applying a layer of oxide material to cover the trenches and the silicon ridges; and, sixthly, laterally depositing a plurality of spaced semiconductor strips on the oxide layer such that each of the lateral semiconductor strips constitutes a word

Abstract: A method for manufacturing a semiconductor device in which an opening is formed in an insulation film laid on a semiconductor substrate, and in which an annular trench that is narrower than a minimum width obtained by lithography is formed in the semiconductor substrate along the opening in a self-aligned manner. The method includes the steps of: forming a first insulation film on a main surface of a semiconductor substrate; forming an opening in the first insulation film; forming an annular film along the inner sidewall of the opening; forming a second insulation film on the surface of the semiconductor substrate surrounded by the annular film; removing the annular film to cause the semiconductor substrate to be annularly exposed; forming an annular trench by etching the exposed area of the semiconductor substrate; and forming a film layer containing at least a third insulation film over the entire main surface of the semiconductor substrate including the inside of the annular trench.

Abstract: An insulating layer wherein contact holes to regions to be contacted are opened is applied surface-wide onto a substrate. For producing an interconnect mask, a photoresist layer is applied, exposed and developed such that the surface of the regions to be contacted remains covered with photoresist in exposed regions, whereas the surface of the insulating layer is uncovered in the exposed regions. Using the interconnect mask as etching mask, trenches are etched into the insulating layer. Contacts and interconnects of a metallization level are finished by filling the contact holes and the trenches with metal.

Abstract: A trench mask is formed of two dissimilar layers of material deposited over a substrate. The lower of the two layers is an insulating layer such as silicon dioxide or silicon nitride, or combinations of both, and the upper of the two layers is doped or undoped polysilicon. Together, the two layers are patterned in a first etch step to form a trench mask for subsequent etching of trenches in the substrate. The upper layer is deposited to a thickness "t" related to the desired depth "d" of the trenches to be etched. In a second etch step, the trenches are formed in the substrate. In the case of substantially uniform etching of the polysilicon and the substrate, the thickness of the polysilicon is substantially equal to the desired trench depth. In the case of unequal etching of the polysilicon and the substrate, the thickness of the polysilicon is based on the etch rate disparity.

Abstract: A method for forming contact of a semiconductor device which prevents residues of a conductive material due to high steps on an insulating layer between metal lines, and minimizes contact area, includes the steps of forming an impurity diffusion region on a predetermined portion of an isolation region on a substrate, forming a first insulating layer on the surface of the substrate, forming a first conductive pattern and a second insulating pattern on the upper portion of the first insulating layer, forming a barrier pattern on the upper portion of the second insulating pattern, forming a third insulating layer on the upper portion of the barrier pattern and the first insulating layer, and etching the third insulating layer to expose the upper portion of the barrier pattern, forming a photoresist pattern for contact mask on the surfaces of the barrier pattern and third insulating layer, etching the third insulating layer and first insulating layer exposed by the photoresist pattern to form a contact hole havin

Abstract: A process for producing a semiconductor device of the type having a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate; a first element formed in a region of the semiconductor layer and having a perimeter including a bottom; a second element formed in another region of the semiconductor layer; an insulating layer surrounding the perimeter of the first element, for electrically insulating and separating the first element from the second element and the semiconductor substrate; an electrical shield layer disposed between the insulating layer and the first element, surrounding the perimeter of the first element, and adapted to a reference electric potential applied thereto, for shielding the first element from an electrical fluctuation of the semiconductor substrate caused by the second element; and an electrode for applying the reference electric potential to the electrical shield layer.

Abstract: There are disclosed methods for the formation of field oxide film in a semiconductor device. By the methods, a field oxide film which plays a role of insulation for the separation of device, is formed in a trench formed in a semiconductor substrate. In the methods, an oxide-nitride film is utilized as an oxidation protective film which prevents a pad oxide film and the side well of the trench from being oxidized. As a result, the bird's beak is reduced, which allows to secure the active region more large. In addition, the methods make the field oxide film smooth. Furthermore, increasing the threshold voltage of a field, the field oxide film is superior in punchthrough characteristics. Accordingly, the methods can be applied to fabricate highly integrated semiconductor devices.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of: sequentially forming a silicon oxide film, a silicon nitride film, a polysilicon film; and a protective film on a silicon substrate, etching and removing the protective film from a shallow groove formation region to expose a surface of the polysilicon film; etching and removing the protective film, the polysilicon film, the silicon nitride film, and the silicon oxide film from a deep groove formation region to expose asurface of the silicon substrate; etching the silicon substrate and the polysilicon film, both of which are exposed, using the protective film as a mask to form agroove having a predetermined depth in the deep groove formation region; etching and removing at least the silicon oxide film left in the shallow groove formation region to expose a surface of the silicon substrate; and simultaneously etching the silicon substrate in the deep and shallow groove formation regions using the protective film as a mask

Abstract: Integrated circuits are fabricated on a bonded wafer which has a buried silicide layer.

Abstract: A method of fabricating a stress-free isolation layer for semiconductor integrated circuit that solves the problems of crystalline defects and the degraded characteristics of devices due to the presence of structural stresses. Partial trench etching is employed to form at least one narrow trenches, followed by anneal-treating to release stress and eliminate crystalline defects therein. Isolating material is then filled into the narrow trenches to form a complete stress-free isolation layer.

Abstract: The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide (44) is chemically vapor deposited over the trench isolation region (44) and the adjacent active region (23). A transistor gate electrode (46) is subsequently formed over the thin layer of silicon dioxide (44). The thin layer of silicon dioxide (44) increases the thickness of the gate dielectric that lies between the transistor gate electrode (46) and the trench corner, and therefore the breakdown voltage of the gate dielectric at the trench corner is increased.

Abstract: A thin film forming method comprises the steps of supporting a semiconductor substrate having a trench or an unevenness thereon in a reaction vessel; introducing a reactive gas into the vessel; activating the reactive gas to form a deposit species, the deposit species characterized by a phase diagram including a liquid phase region defined by a melting curve and an evaporation curve that intersect at a triple point; and forming a thin film containing at least part of the deposit species on the substrate while retaining a pressure in the vessel higher than the triple point of the phase diagram of the deposit species, and retaining a temperature of the substrate within the liquid phase region of the phase diagram of the deposit species.

Abstract: A novel device isolation scheme for separating active regions on a semiconductor substrate by combining field oxide formation with trench isolation is disclosed. According to this scheme, shallow and deep trenches are etched into the semiconductor substrate. A layer of nitride is deposited over the entire substrate followed by a layer of poly-silicon. Oxide spacers on the poly-silicon and a photoresist mask is aligned within the oxide spacers, thereby permitting the selective etching of the poly-silicon layer. The poly-silicon layer overlying the active regions of the semiconductor substrate are etched away. Then an oxidation step is performed such that the poly-silicon layer filling the shallow trenches is oxidized while the poly-silicon filling the deep trenches remains unoxidized. The alignment of the photoresist becomes highly non-critical because of the use of the oxide spacers and fully walled junctions are provided.

Abstract: A new method of local oxidation by means of forming a plurality of silicon trenches is described. Portions of the insulating layer over the surface of a silicon substrate not covered by a mask pattern are etched through exposing the portion of the silicon substrate that will form the device isolation region. A first trench is etched into the exposed portion of the substrate. A layer of silicon nitride is deposited over the insulating layer and within the trench. A layer of an aluminum-silicon alloy is deposited overlying the silicon nitride layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the silicon nitride layer. The nodules are oxidized to form silicon dioxide nodules. Using the silicon dioxide nodules as a mask, the silicon nitride layer is etched through to the insulating layer where it exists and to the silicon substrate surface where it is exposed and a set of narrow trenches is etched into the exposed portions of the substrate.

Abstract: A semiconductor device includes a semiconductor substrate, first and second semiconductor layers of opposite conductivity types successively disposed on the semiconductor substrate, and a via hole structure including a hole penetrating through the first and second semiconductor layers and into the substrate, the via holes being defined by a side wall of the first and second layers and of the substrate, an electrically conducting material disposed on the side wall contacting the first and second semiconductor layers, and an electrically isolating region disposed in the first and second layers at the side wall and contacting the electrically conducting material. The electrically isolating region is formed with an ion flux applied either before or after etching of the via hole.

Abstract: A method is provided for forming a fully planarized trench isolated region in a semiconductor substrate for an integrated circuit, for example, a trench isolated field oxide region, or a trench isolated semiconductor region in which thin film semiconductor devices are formed. Planarization is accomplished by a chemical mechanical polishing process in which coplanar layers of a chemical mechanical polish resistant material are provided in a centre region of wide trenches as well as on the semiconductor substrate surface adjacent the trenches. The chemical mechanical polish resistant layer in the centre region of a wide trench forms an etch stop to prevent dishing of layers filling the trench during overall wafer planarization by chemical mechanical polishing. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuit structures.

Abstract: A method of manufacturing semiconductor devices by forming a U-shaped insulated gate on a substrate, etching the substrate to expose a sidewall of the U-shaped insulated gate, covering the exposed part with a masking material, forming the sidewall of the masking material only adjoining to the exposed U-shaped insulated gate, etching the substrate vertically to form a groove, forming a semiconductor region on the groove and burying a metal into the groove.