Abstract: Pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (e.g., less than 100 nm) depth provides a solution to fabrication problems including (1) high thermal conduction in crystalline silicon and (2) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology.

Abstract: Provided is a process for producing a semiconductor silicon wafer by which an intrinsic gettering effect can be improved and at the same time the top side can be made free from faults. A silicon ingot is produced and sliced to obtain silicon wafers. Then, a polycrystal silicon depositing film is formed on one side of a silicon wafer, which is subjected to a heat treatment in an inert gas, a reducing gas or a mixture thereof to discharge oxygen from the vicinity of the other side. Alternatively, after discharging oxygen from the silicon wafer by a heat treatment, a polycrystal silicon depositing film may be formed on one side of the silicon wafer.

Abstract: The present invention is related to a method for fabricating a silicon electronic device having a boron diffusion source layer, includes steps of: a) providing a silicon substrate; b) depositing a silicon layer on said silicon substrate; and c) growing a silicon-boron binary compound layer on said silicon layer as said boron diffusion source. When the Si-B layer is formed by a UHV/CVD process according to the present invention, the boron concentration in the Si-B binary compound layer will be extraordinary high (up to 1.times.10.sup.21 to 5.times.10.sup.22 atoms/cm.sup.3).

Abstract: A method for forming impurity junction regions of a semiconductor device wherein impurity junction regions with a small depth are formed by selectively forming defecting regions and amorphous regions in a semiconductor substrate by an implantation of impurity ions with a large molecular weight, thereby achieving an improvement in the characteristics of the semiconductor device.

Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.

Abstract: An improved semiconductor processing is disclosed. In the manufacturing process, a semiconductor layer is formed and then undergoes photo annealing. A neutralizer is then introduced to the photoannealed semiconductor. The semiconductor thus formed demonstrates the SEL effect instead of the Staebler-Wronski effect.

Abstract: A method of gettering unintentional mobile impurities starts with production of an damaged portion on the reverse side of a silicon wafer, and the silicon wafer is placed in a high temperature vacuum ambience so that the unintentional mobile impurities are firstly trapped by the damaged portion and, then, evacuated to the high temperature vacuum ambience.

Abstract: A method of gettering heavy metal impurities from p-type silicon substrates comprises the prior step of forming an intrinsic gettering layer covered with a surface denuded zone in the silicon substrate by subjecting the substrate to heat treatments which form the intrinsic gettering layer having a large density of crystal microdefects compared to the density of crystal microdefects in the denuded zone; then the step of performing most of the required wafer processes other than the step of forming a metal layer; and subsequently the gettering step of heating the silicon substrate to a predetermined temperature and simultaneously irradiating the substrate with light rays, the predetermined temperature being selected to be within the temperature range 150.degree. C. to 220.degree. C., preferably around 200.degree. C.

Abstract: Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n.sup.- active channel region formed on a GaAs substrate, a Schottky gate overlying the n.sup.- region and highly doped and deep n.sup.+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels.In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length.In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n.sup.- semiconductor layer is formed in the device active region.

Abstract: A method of passivating the surface of an indium gallium arsenide substrate by cleaning the indium gallium arsenide substrate in an etching solution and depositing a sodium hydroxide film on the substrate. The step of depositing the sodium hydroxide film is preferably performed by spin-on of a sodium hydroxide solution, followed by drying or annealing. The resulting passivated surface exhibits superior surface recombination velocity characteristics compared to prior art passivation techniques, thereby making possible superior solid state device operating characteristics.

Abstract: Hillock formation as a result of heating uncapped polycrystalline silicon layers can be avoided by first implanting the uncapped poly layers with silicon, oxygen, or nitrogen prior to heating. Equivalent mono-atomic oxygen or nitrogen doses in the range of about 10.sup.15 to about 5.times.10.sup.16 ions/cm.sup.2 at energies in the range 10-50 keV are useful with good results being obtained with equivalent oxygen doses of 2.times.10.sup.15 ions/cm.sup.2 at 30 keV. When polysilicon layers with this oxygen implant are heated to about 1150 degrees C., a temperature which would ordinarily produce pronounced hillock formation in un-capped, un-treated poly layers, it is found that hillock formation is suppressed. The implanted oxygen concentrations are far below what is required to produce a separate oxide layer or phase. Some effect on poly layer sheet resistance is observed for implanted oxygen but the implanted layers have sheet resistances within a factor of two of those without the oxygen implants.

Abstract: A method of manufacturing a semiconductor device has the steps of forming an insulating film on a semiconductor substrate, forming a polycrystalline silicon layer on the insulating film, converting either all of the polycrystalline silicon layer or a portion of predetermined thickness of the polycrystalline silicon layer into an amorphous silicon layer, patterning the polycrystalline silicon layer, either all of which or a portion of predetermined thickness of which has been converted into an amorphous silicon layer, and ion-implanting an impurity in the semiconductor substrate using the patterned layer as a mask.

Abstract: A method of forming a thin semiconductor film has the steps of: forming a thin semiconductor film on a predetermined substrate; implanting predetermined ions in the thin semiconductor film to convert the thin semiconductor film to a thin amorphous semiconductor film; decreasing a thickness of the thin amorphous semiconductor film to a predetermined thickness; and annealing the thin amorphous semiconductor film to cause solid-phase growth. According to this method, a large thin polycrystalline semiconductor film with a crystal grain size larger than the conventional crystal grain size and a good crystal grain orientation can be uniformly formed at a low temperature. It is, therefore, possible to use such a thin semiconductor film to fabricate a thin film semiconductor device with excellent electrical characteristics.

Abstract: The present invention provides a method of protecting semiconductor integrated circuit from mobile ion contamination. In one embodiment a gettering agent is implanted into a dielectric layer. In an alternative embodiment a gettering agent is implanted into a photoresist layer which is ashed in an oxygen based plasma, leaving the gettering agent on the surface underlying the photoresist.

Abstract: A method for producing hyperabrupt P.+-. or N.+-. regions in a near-surface layer of a substantially defect free crystal, using solid phase epitaxy and transient annealing. The process for producing a hyperabrupt retrograde distribution of the dopant species begins with amorphizing the near-surface layer of a base crystal, and then implanting a steep retrograde distribution of the desired species into the amorphized layer, so that the retrograde distribution lies entirely within the amorphized layer, thereby avoiding channelling effects during implantation. The substantially defect-free structure of the base crystal is restored by annealing the implanted base crystal at a temperature sufficiently high to induce solid phase epitaxial regrowth on the underlying nonamorphized crystal, but at a temperature sufficiently low to avoid significant diffusion of the implanted species.

Abstract: The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhibits their ability to inject carriers into the substrate and well.

Abstract: For achieving dense packing of MOS transistors at the top surface of a silicon semiconductor body, second level metallization including arsenic doped polysilicon contacts are used in conjunction with a phosphorus gettering step at a time when the top surface is sealed against the introduction of phosphorus by an undoped sacrificial glass layer, i.e., which is essentially free of phosphorus. The second level metallization is thereafter completed by coating the polysilicon with a high conductivity metal, such as aluminum. During the gettering, the polysilicon contacts are insulated from the first level metallization by a planarized glass layer doped with phosphorus to a concentration below the saturation level of phosphorus in the glass.

Abstract: A silicon on sapphire (SOS) semiconductor structure may be processed to improve the electrical characteristics of a silicon film on a sapphire substrate by silicon-regrowth (SRG) techniques using oxidation to remove silicon from the outward surface of the silicon film. An epitaxial film on a sapphire substrate is implanted with silicon to amorphize the silicon film except for a thin seed layer on the outward surface of the silicon film. The silicon is recrystallized inwards using the seed layer as a seed for crystallization. The silicon film is oxidized to produce an oxide layer on the outward surface of the silicon film, the SOS structure may be heated to densify the oxide layer, and the oxide layer is etched away. This produces a silicon film with a reduced p-type electrical activity and improved crystalline quality surface so that the channel mobility is improved for semiconductor devices fabricated in the silicon film.

Abstract: The invention relates to a process for gettering semiconductor devices. A getter layer of amorphous or microcrystalline silicon is applied to the device. The so coated device is thermally treated and the getter layer is removed.

Abstract: There is disclosed a process and the resulting semiconductor wafer wherein the backside of the wafer has applied thereto a layer of polysilicon. Portions of this layer are exposed to an energy beam to recrystallize them into single crystal silicon fused to and extending from the underlying wafer. The recrystallized portions contact adjacent portions of the polysilicon layer, thereby providing a path for impurities migrating from the wafer to the polysilicon.