Abstract: A process for producing a metal oxide semiconductor (MOS) transistor is provided. At least two trenches are formed at a surface of a first substrate. Oxide is deposited onto the at least two trenches. The at least two trenches each have a surface spaced apart from the surface of the first substrate. A second substrate is placed onto the surface of the first substrate. A layer is delaminated from the first substrate. The layer includes the at least two oxide-filled trenches and a portion of the first substrate. The layer is then bonded to a second substrate. First and second active regions are then formed, in the portion of the first substrate, overlaying the surfaces of the at least two trenches.

Abstract: An SOI integrated circuit contains Al implanted below the channel areas of NFETs and has a positive substrate bias, the magnitude of the substrate bias and the implant dose being set such that the bias suppresses backside leakage in the PFETs and the implant dose suppresses leakage in the NFEts in spite of the bias.

Abstract: An SOI-type thin film transistor having a transparent insulating substrate a first gate electrode, a first gate insulating film, a semiconductor layer, a second gate electrode and a second gate insulating film which are respectively formed on the transparent insulating substrate, wherein the width of the first gate electrode and that of the second gate electrode are different from each other and as well as the thickness of the first gate insulating film and that of the second gate insulating film are different from each other.

Abstract: A method for fabricating low leakage current bipolar junction transistors of silicon-on-sapphire for efficient use in operational amplifiers utilizes all implant technology, improved silicon conditioning processing, and low temperature annealing.

Abstract: A process for making a silicon-on-insulator MOS transistor is disclosed which includes forming an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to sidewall oxide filaments on the source side of the gate electrode. The lightly-doped drain extension of the source region remains disposed between the contact region and the body node at the surface, but the contact region extends below the depth of the lightly-doped drain region to make contact to the body node. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor.

Abstract: The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.

Abstract: A method of fabricating CMOS circuit devices on an insulator substrate is disclosed in which a solid phase epitaxy process is applied to islands for the individual devices in the same step as the channel dopant implants. An ion species, preferably silicon for a silicon island, is implanted into each island at an energy and dosage sufficient to amorphize a buried layer of the island in the vicinity of an underlying insulated substrate; silicon-on-sapphire (SOS) is preferably employed. The buried layers are then recrystallized, using the unamorphized portions of the semiconductor islands as crystallization seeds. Islands of generally uniform, high quality semiconductor material are thus obtained which utilize dopant implants more efficiently, and avoid prior parasitic transistors and leakage currents.

Abstract: Method is provided for manufacturing large crystalline and monocrystalline semiconductor-on-insulator devices.

Abstract: In one embodiment of a vertical bipolar transistor constructed in accordance with the teachings of this invention, oxygen is implanted into the vertical bipolar transistor to provide a silicon dioxide layer between the base and collector of the vertical bipolar transistor. This silicon dioxide layer reduces the actual interface area of the base to collector junction, thereby decreasing the capacitance of the base-collector junction. In addition, the dielectric constant of the silicon dioxide layer is such that the capacitance across the silicon dioxide layer, and thus between the base and collector, is minimal relative to the base to collector capacitance provided by the base to collector junction itself. In an alternative embodiment, nitrogen is implanted to form silicon nitride regions rather than silicon dioxide regions.

Abstract: The invention relates to a method for the manufacture of field effect transistors of the coplanar and self-aligned type, obtained in thin film form on an insulating substrate.As a result of electrode self-alignment and ion implantation, the method makes it possible to use only three masking levels.The invention is applicable to the field of large surface microelectronics and particularly to the control and addressing of a flat liquid crystal screen or an image sensor.

Abstract: MOS transistors in which the source and drain contact are isolated from the common substrate are formed by using the gate conductor to mask a high dose high energy implant which creates a thin dielectric region within the body of the common substrate beneath the source and drain regions, but not beneath the channel region. For single crystal silicon substrates, oxygen and nitrogen are the preferred ions for use in forming the buried dielectric region. The conductive gate must be sufficiently thick so as to preclude the implanted oxygen or nitrogen ions from reaching the underlying gate dielectric or the portion of and channel region of the device will be substantially free the substrate beneath the gate. This ensures that the gate and channel region of the device will be substantially free of the implant damage which otherwise occurs during formation of the buried dielectric regions. Dielectric isolation walls are conveniently provided laterally exterior to the source-drain regions.

Abstract: A process is disclosed for preparing selectively doped and recrystallized silicon-on-insulator semiconductor wafers, and wafers prepared thereby, wherein successive amorphizing and annealing sequences are utilized to optimize the defect structure and doping of multiple regions or islands of the silicon on an insulator substrate. Prior to fabrication of the active devices, the various silicon islands are given customized ion implantation treatments to amorphize a silicon near-interface layer under differing sets of implantation conditions. The entire wafer is then annealed to achieve downward epitaxial recrystallization of the amorphized near-interface layers in all of the amorphized islands, growing on the near-surface crystalline layer of the silicon remote from the interface. The near-surface layers of the islands are then amorphized and annealed to achieve upward epitaxial recrystallization of the layers on the underlying silicon layer.

Abstract: A method of simultaneously manufacturing semiconductor regions having different doping concentrations, for example, for obtaining semiconductor resistors having differences values. Due to difference in the rate of oxidation, oxide edges of different widths can be formed by oxidation of n-type silicon regions thus obtained. According to the invention, ion implantation or deposition takes place through doping windows for each of which the ratio between the window surface area and the surface area to be doped is different. Subsequently, homogeneous doping concentrations are obtained by diffusion.

Abstract: Disclosed is a nonvolatile memory device which utilizes a laser beam recrystallized silicon layer having source-channel-drain regions. Underlying the recrystallized layer and separated therefrom by a memory dielectric is a gate in alignment with the source and drain. The gate is formed directly on a substrate of an insulative material (e.g. non-silicon material).The process of forming the above device comprises forming a conductive polysilicon gate on a substrate followed by a memory nitride layer deposition thereon. A thick oxide layer is formed over the nitride followed by removal of the thick oxide corresponding to a central portion of the gate thereby exposing the nitride therebeneath. The exposed nitride surface is thermally converted into a thin, stoichiometric memory SiO.sub.2. A doped polysilicon layer is then formed on the structure and thereafter converted to recrystallized silicon by subjecting it to laser radiation.

Abstract: A silicon on sapphire (SOS) semiconductor structure may be processed to improve the electrical characteristics of a silicon film on a sapphire substrate by silicon-regrowth (SRG) techniques using oxidation to remove silicon from the outward surface of the silicon film. An epitaxial film on a sapphire substrate is implanted with silicon to amorphize the silicon film except for a thin seed layer on the outward surface of the silicon film. The silicon is recrystallized inwards using the seed layer as a seed for crystallization. The silicon film is oxidized to produce an oxide layer on the outward surface of the silicon film, the SOS structure may be heated to densify the oxide layer, and the oxide layer is etched away. This produces a silicon film with a reduced p-type electrical activity and improved crystalline quality surface so that the channel mobility is improved for semiconductor devices fabricated in the silicon film.

Abstract: The invention provides a process comprising a step for depositing at least one intrinsic or doped monocrystalline silicon layer on a substrate, also monocrystalline, followed by a step for forming a thin silica layer at the level of the original substrate-silicon interface. The silica layer is obtained by oxidation through the substrate, followed by a heat treatment step during which the monocrystalline silicon is oxidized by the implanted oxygen ions. The first approach may take place according to two variants: thermal or plasma oxidation of the silicon-substrate interface. Oxidation takes place during the return to ambient temperature of the stack of layers after the deposit has been made.

Abstract: A process for the interdisposition of a semiconductor compound by high dose oxygen ion implantation after a high quality single crystal semiconductor film has been formed on an insulator substrate. Specifically, in one embodiment, after the formation of a single crystal silicon semiconductor film on an insulator substrate of either sapphire or spinel, oxygen ion implantation is formed to create a silicon dioxide layer at the interface between the silicon semiconductor film and the insulator substrate in order to reduce the interface states and form a diffusion barrier between the semiconductor material and the electrical insulator substrate.