Abstract: A method and apparatus for characterizing and controlling the heat treatment of a metal alloy employing non-contact sensors selectively positioned to minimize the effects of background temperature contributions. The sensors monitor the temperature of the part being treated at a location that is remote from the surface that is being irradiated directly. In preferred embodiments, the surface where the temperature measurements are taken are located within a black body source. The collected temperature information is used to control the heat treatment of the metal alloy.

Abstract: Disclosed is a method of manufacturing a semiconductor device wherein a corpuscular beam is radiated to a semiconductor substrate to create crystal defects therein. The semiconductor substrate is subjected to a heat treatment, e.g. for 1 second to 60 minutes, wherein rapid heating-up, e.g. raising temperature to 550.degree. to 850.degree. C. within 10 minutes, is done in a process prior to that of carrying out of the radiation with a corpuscular beam. By doing so, there is provided a semiconductor device which is free from degradation in electrical characteristics such as current amplification factor and has an increased switching speed, even where crystal defects are created through the radiation of corpuscular beam such as an electron beam to shorten the carrier lifetime. Thus, the inventive semiconductor device is satisfied by both requirements of switching speed and electrical characteristic.

Abstract: This is a system and method of forming an electrical contact to the optical coating of an infrared detector. The method may comprise: forming thermal isolation trenches 22 in a substrate 20; depositing a trench filler 24 in the thermal isolation trenches 22; depositing a common electrode layer 31 over the thermal isolation trenches 22; depositing an optical coating 26 above the common electrode layer 31; mechanically thinning the substrate to expose the trench filler 24; etching to remove the trench filler 24 in the bias contact area; depositing a contact metal 34 on the backside of the substrate 20, wherein the contact metal 34 connects to the common electrode layer 31 at bias contact areas 34 around a periphery of the thermal isolation trenches; and etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20. Bias contact vias 23 may be formed in the bias contact areas and then filled with bias contact metal 49.

Abstract: A substantial portion of the material at the pn junction (27) of the photodiode (37, 41) having an implanted region extending to a surface thereof is selectively removed (39), leaving a very small junction region (35, 43) with the remainder of the p-type (23) and n-type (25) material of each photodiode being spaced apart or electrically isolated at what was originally the junction. In the ion implanted n-type on p-type approach, the majority of the signal is created in the implanted n-type region while the majority of the noise is generated in the p-type region. By selectively removing p-type material, n-type material or both from the pn junction of the diode or otherwise electrically isolating most of the p-type and n-type regions from each other at the pn junction and thereby minimizing the pn junction area, noise is greatly reduced without affecting the signal response of the photodiode.

Abstract: A process for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface of the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Abstract: Photodetectors that produce detectivities close to the theoretical maximum detectivity include an electrically insulating substrate carrying a body of semiconductor material that includes a region of first conductivity type and a region of second conductivity type where the region of first conductivity type overlies and covers the junction with the region of second conductivity type and where the junction between the first and second regions separates minority carriers in the region of second conductivity type from majority carriers in the region of first conductivity type. These photodetectors produce high detectivities where radiation incident on the detectors has wavelengths in the range of about 1 to about 25 microns or more, particularly under low background conditions.

Abstract: Methods are disclosed for making semiconductor windows which are transparent to light in the infrared range which have good electrical conductivity and are formed of a substrate material (11) having a semiconductor coating (14) having a dopant included therein. The coating is diffused, grown or deposited on one surface of the substrate and is controlled to obtain both low electrical resistivity and high infrared transmissivity. The coating can be formed of the same material as the substrate or can be a different material. Windows having particular thermal properties are formed utilizing zinc selenide and zinc sulfide as the substrate.

Abstract: The efficiency of a metal silicide infrared detector (10) in greatly enhanced by depositing on the substrate (14) a stack (30) of alternating metal silicide (12,24) and silicon layers (22). The metal silicide layers (12,24) are connected to each other and to a contact pad (20) in the substrate (14) by a metal silicide deposit (32) on one side of the stack (30) and the silicon layers (22) are connected to each other and to the substrate (14) by a silicon deposit (34) on another side of the stack (30). The stacking of layers is made possible by depositing the silicon layers (22) at a rate of 1 .ANG./sec or less in a vacuum of 10.sup.-9 torr or better at a temperature of about 250.degree. C.

Abstract: A method of forming an integrated circuit for the detection of infrared radiation comprising a semi-isolating substrate provided with a buried PIN photodiode, with a junction field effect transistor J-FET, whose gate is connected to the PIN photodiode, and with a resistor R connected to the transistor, this method including the growth of a first structure of epitaxial layers of semiconductor materials, in which the J-FET transistor is formed, the growth of a second structure of epitaxial layers of semiconductor materials, in which the PIN diode is formed, and the step of etching a pit, in which the second structure of layers is formed, characterized in that the step of etching the pit is effected after the growth of the first structure of epitaxial layers and is carried out through this structure down to the substrate, in that the growth of the second structure of epitaxial layers is localized in such a manner that this second structure is limited to the pit and in that its upper surface is copolanar with tha

Abstract: An apparatus and method for fabricating a backside contacted mosaic detector array which provides close detector packing in one or more directions by eliminating over the edge contacts typically used. The method uses indium or other coldweldable metal, both as a means for fastening the array from the backside to its circuit board and as a means for providing electrical contact with each detector.

Abstract: A method for growing a Group II-VI epitaxial layer on a substrate, said epitaxial layer having an electron mobility greater than 1.5.times.10.sup.5 cm.sup.2 /V-sec at 77.degree. K. and a carrier concentration less than 4.times.10.sup.15 (cm.sup.-3) is described. The method includes the steps of directing a plurality of vapor flows towards the substrate including a Group II metalorganic vapor having a mole fraction in the range of 3.0.times.10.sup.-4 to 4.5.times.10.sup.-4, a Group VI metalorganic vapor having a mole fraction in the range of 2.9.times.10.sup.-3 to 3.5.times.10.sup.-3 and a Group II elemental metal vapor having a mole fraction in the range of 2.6.times.10.sup.-2 to 3.2.times.10.sup.-2. The source of Group II metal is heated to at least 240.degree. C. while radiant energy is directed toward the reactor vessel to warm the zone of the reactor vessel between the Group II metal source and the substrate to at least 240.degree. C.