Abstract: A low dielectric constant insulation layer for an integrated circuit structure material, and a method of making same. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The porous insulation layer is formed by depositing a composite layer comprising an insulation material or a material which can be converted to an insulation material, by a converting process and a material which can be converted to a gas upon subjection to the converting process. Release of the gas leaves behind a porous matrix of the insulation material which has a lower dielectric constant than the composite layer.

Abstract: Defects in a thin dielectric layer of a semiconductor device are plugged by a discontinuous layer to maintain integrity of the dielectric without degrading the reliability of the device. In one form of the invention, a semiconductor device (10) includes an oxide layer (14) formed on a substrate material (12). Growth of a nitride layer (18), using CVD techniques, is initiated in any defects (16) in the oxide layer, but growth is terminated prior to entering a continuous growth stage. By plugging the defects with nitride without forming a continuous nitride layer, defect density in thin oxides is reduced without experiencing disadvantages associated with thick oxide-nitride stacks. The invention is also applicable to plugging defects in dielectric layers other than oxide. Furthermore, growth of a discontinuous layer may be achieved with a material other than a nitride using CVD techniques.

Abstract: A passivation layer of dielectric material disposed on the top surface of the semiconductor device prevents the metallized patterns on the semiconductor substrate from being exposed to chemical attack. This layer also provides for improved metal electro-migration resistance through the well-known mechanism of grain boundary pinning. The semiconductor device substrate includes a dielectric layer which is disposed along the surface over the electrode metallization. The semiconductor substrate includes metallized regions on top of the dielectric layer which is disposed over the substrate surface and the electrodes thereon. These metallized regions form capacitors to the semiconductor electrodes and capacitively couple electrical input and output signals to the electrodes from external electronic apparatus.

Abstract: Control of the Fermi level pinning problem and the production of flat band surface performance in compound semiconductors is achieved by providing a cationic oxide free of anionic species on the surface of the semiconductor for flat band performance and with a localized inclusion of some anionic species for barrier performance so that oxide and metal work function responsiveness is available in structure and performance in MOSFET, MESFET and different work function metal FET structures. A cationic gallium oxide is produced on GaAs by oxide growth during illumination and while being rinsed with oxygenated water. The oxidation is used to produce both anionic and cationic species while the rinsing process selectively removes all the anionic species.

Abstract: A semiconductor laser includes a semiconductor substrate on which a longitudinal groove is provided in the resonator direction, a first semiconductor layer disposed on a region of the semiconductor substrate where the groove is not provided and forming a rectifying junction therewith, a first cladding layer provided on the semiconductor substrate in the groove, an active layer provided on the first cladding layer in the groove, and a second cladding layer provided directly on the active layer and opposite the first semiconductor layer with an interposed insulating layer, such as a gap void of solid material or a gap and current blocking material having only negligible parasitic capacitance.

Abstract: A method for forming a multilayer integrated circuit is described wherein the resultant top surface thereof is substantially planar. The method involves first forming a layer of connecting metallization on integrated circuit components formed in a conventional manner. Then a first layer of dielectric is formed on the metallization layer. Next a second dielectric layer is formed on the first dielectric layer. Via areas are then formed by etching the first and second dielectric layers in order to expose selected areas of the first metallization layer, and filled with metal to form vias. A layer of photoresist is deposited on all surfaces. Lastly, the surface is etched using an etchant that etches dielectric, metal and photoresist at substantially the same rate such that said vias are exposed and a planar top surface produced.

Abstract: Certain semiconductor device structures are described in which single crystal layers of cubic Group II fluorides cover at least part of the surface of III-V semiconductor compound. The fluoride crystal has a cubic structure and may be lattice matched or lattice mismatched to the compound semiconductor substrate depending on fluoride composition. These fluoride single crystal layers are put down by a moleuclar beam epitaxy procedure using certain critical substrate temperature ranges and a particular cleaning procedure.

Abstract: Certain semiconductor device structures are described in which single crystal layers of cubic Group II fluorides cover at least part of the surface of III-V semiconductor compound. The Fluoride crystal has a cubic structure and may be lattice matched or lattice mismatched to the compound semiconductor substrate depending on fluoride composition. These fluoride single crystal layers are put down by a molecular beam epitaxy procedure using certain critical substrate temperature ranges and a particular cleaning procedure.

Abstract: The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.

Abstract: A process for forming a thin sealing layer of silicon nitride directly upon a silicon substrate to minimize bird's beak encroachment. The process employs in situ fabrication whereby the native oxide is removed from the silicon substrate by etching the hydrogen or hydrogen chloride and followed in direct succession, and in the absence of exposure to an oxidizing environment, with the deposition of a silicon nitride layer by LPCVD. Bird's beak encroachment is incrementally reduced by the absence of the native oxide layer as a path for oxygen species movement during the field oxide growth.

Abstract: A method for forming a silicon dioxide layer on a silicon island on an insulating substrate includes the steps of initially providing an insulating substrate having a major surface on which a silicon island is disposed. The surface of the silicon island is then thermally oxidized and a silicon layer is deposited on the oxidized island and the portion of the substrate surface adjacent to the island. This entire silicon layer is then oxidized and a conductive polycrystalline silicon electrode is deposited thereon.

Abstract: A method of manufacturing a semiconductor device comprises a step of preparing a semiconductor substrate (12) having a surface layer of silicon, a step of forming a conductive thin film (14) of a silicide composed of a metal having a high melting point and silicon on the semiconductor substrate (12), a step of forming an oxidation-resistant mask (18) on a first portion (14a) of the conductive thin film (14) and a step of converting a second, exposed, portion (19) of the conductive thin film (14) into an insulating film (19a) of a composite oxide composed of silicon oxide and an oxide of the subject metal by oxidizing the exposed portion (19) while maintaining the first portion (14a) of the conductive thin film (14) covered by the mask (18).

Abstract: Passivation of predominantly crystalline semiconductor devices (12) is provided for by a surface coating (21) of sputtered hydrogenated amorphous semiconductor material. Passivation of a radiation detector germanium diode, for example, is realized by sputtering a coating (21) of amorphous germanium onto the etched and quenched diode surface (11) in a low pressure atmosphere of hydrogen and argon. Unlike prior germanium diode semiconductor devices (12), which must be maintained in vacuum at cryogenic temperatures to avoid deterioration, a diode processed in the described manner may be stored in air at room temperature or otherwise exposed to a variety of environmental conditions. The coating (21) compensates for pre-existing undesirable surface states as well as protecting the semiconductor device (12) against future impregnation with impurities.

Abstract: A silicon nitride film containing from 20 to 70% oxygen, for use as a surface passivation film, has enhanced ultraviolet ray transmissivity while exhibiting the desirable moisture proofness quality of a silicon nitride film.

Abstract: In a 1.2 micron CMOS process, the gate oxide is formed by growing a 1000 Angstrom thickness of sacrificial oxide, immediately performing an oxide strip and then effecting a thin gate oxidation. The gate oxidation step is characterized by a temperature ramp from 700 to 950 degrees Centigrade in a flow of 9 liters per minute nitrogen and 0.36 liters per minute oxygen. At the 950 degrees Centigrade point, the nitrogen flow ceases and the oxygen flow increases to 9 liters per minute. The temperature is then downwardly ramped to 900 degrees Centigrade.

Abstract: A process for producing a semiconductor device by which the minority carrier lifetime can be selectively changed in a semiconductor device. A radiation beam is irradiated onto the surface of a semiconductor substrate to shorten the minority carrier lifetime. Then ions are selectively implanted into a region in which the minority carrier lifetime is to be recovered. Finally, the resultant structure is annealed.