Abstract: A semiconductor device includes a rectangular semiconductor chip having a main surface, a stripe-form semiconductor element forming portion formed in parallel to one of sides of the semiconductor chip to cross the main surface, a first groove portion formed along one of sides of the semiconductor element forming portion in a longitudinal direction, a second groove portion formed along the other side of the semiconductor element forming portion in the longitudinal direction, the second groove portion including a hollow space which is enlarged in substantially a central portion, a surface electrode formed on at least part of an upper portion of the semiconductor element forming portion, an external lead connecting terminal electrode formed in the hollow space, a wiring formed on part of a bottom surface and a side surface, which is adjacent to stripe-form portion, of the second groove portion, for electrically connecting the surface electrode with the terminal electrode, a first dummy electrode formed at least

Abstract: A method for electrically isolating an integrated circuit element in an acoustic charge transport device comprises the steps of providing a semi-insulating substrate; providing an epitaxial layer with a thickness and carrier concentration appropriate for an ACT device; providing a circuit element semiconductor layer in the epitaxial layer for construction of an integrated circuit element, the layer having a thickness substantially less than the thickness of the epitaxial layer and having a carrier concentration substantially greater than the ACT epitaxial layer; laterally isolating the semiconductor layer from other regions of the ACT epitaxial layer; and bombarding the semiconductor layer with protons at a dose sufficient to provide significant vertical electrical isolation from underlying regions of the epitaxial layer semi-insulating with minimal detrimental effect on the electrical characteristics of the semiconductor layer.

Abstract: A method for ion-implanting a dopant species in semiconductors includes the steps of implanting a dopant species in a semiconductor material at a predetermined rate, the predetermined rate being based on a rate corresponding to a maximum in a characteristic graph of percent activation as a function of dopant species implantation rate; and annealing the dopant implanted semiconductor.

Abstract: A wide band-gap semiconductor, such as a II-VI semiconductor having low bipolar resistivity and a method for producing such a semiconductor. To form this semiconductor, atomic hydrogen is used to neutralize compensating contaminants. Alternatively, the semiconductor dopant and hydrogen are introduced into the undoped semiconductor together, and later, the hydrogen is removed leaving an acceptably compensation free wide band-gap semiconductor.

Abstract: A method for increasing the corrosion resistance of honeycomb core panel construction by using an ion implantation process. In one aspect of the invention, molybdenum ions are implanted to a predetermined depth into the front and back surfaces of a honeycomb-shaped core. The ions interact with the metal in the core wall to form an aluminum-molybdenum alloy which is impervious to corrosion. In another aspect of the invention, both front and back surfaces of the honeycomb-shaped core are bombarded with ions so that the ions are implanted throughout the entire core wall. The method may also be extended to include implanting ions into the outer skin layers to achieve enhanced corrosion resistance.

Abstract: According to the present invention, an ingot of the compound semiconductor single crystal grown by the LEC method or the HB method, or a block/blocks or wafers cut from the ingot is subjected to a high temperature annealing at any temperature in the range not less than 1100.degree. C. and not more than the melting point, and then the ingot is cooled at the cooling rate of 15.degree..about.30.degree. C./min. This method ensures that the egg-shape etch pit density revealed in the single crystal by AB etchant is 5.times.10.sup.4 cm.sup.-2 or less, preferably 5.times.10.sup.3 cm.sup.-2 or less. As a result, the device employing the single crystal as its substrate can be possessed of homogeneous property.

Abstract: A semiconductor optical device having a quantum well structure which can easily integrate plural optical devices of band gaps which are different from each other, and yet can achieve a high coupling coefficient by means of disordering the quantum well structure to form a waveguide region except for the portion which is used as an active region. Non-absorbing edges can be formed on the semiconductor laser on the optically integrated circuits by disordering the facets of the quantum well structure with ion implantation and thermal processing.

Abstract: Interstitial incorporation of Group III or Group V dopants, such as As, Sb, Ga, Al or B, in a III-V semiconductor, such as GaAs or Al.sub.x Ga.sub.1-x As, in the absence of any substitutional doping via a Group IV or Group VI dopant, will substantially eliminate, if not completely suppress, the formation of deep donor levels or DX centers in the III-V semiconductor.

Abstract: A plasma containing both beryllium ions and beryllium fluoride ions is achieved. Beryllium crystals are used as a cathode in an ionization chamber containing boron trifluoride gas. The boron trifluoride gas and the beryllium are ionized to produce both beryllium fluoride ions (BeF.sup.+) and beryllium ions (Be.sup.+). Beryllium fluoride ions are emitted to impact a semiconductor target and where they divide thereby implanting beryllium and fluorine.

Abstract: Disclosed is a semiconductor device including a heterojunction bipolar transistor in which the front surface of a base layer and the surface of an emitter-base junction are covered with a high-resistivity layer of compound semiconductor containing at least one constituent element common to an emitter layer and the base layer.

Abstract: An optical semiconductor device manufacturing method is disclosed which involves an ion implantation step of implanting ions into a compound semiconductor wafer through an ion implantation mask and an annealing step of activating atoms in the compound semiconductor wafer through an annealing mask film. The ion implantation step and the annealing step are performed in succession after laminating mono- or multi-layered compound semiconductor layers as the ion implantation mask and the annealing mask film on the compound semiconductor wafer.

Abstract: An ion beam (113) focused into a diameter of at most 0.1 .mu.m bombards substantially perpendicularly to the superlattice layers of a one-dimensional superlattice structure and is scanned rectilinearly in a direction of the superlattice layers so as to form at least two parallel grooves (108, 109, 110, 111) or at least two parallel impurity-implanted parts (2109) as potential barrier layers, whereby a device of two-dimensional superlattice structure can be manufactured. At least two parallel grooves (114, 115, 116, 117) or impurity-implanted parts are further formed orthogonally to the potential barrier layers of the two-dimensional superlattice structure, whereby a device of three-dimensional superlattice structure can be manufactured. In addition, deposition parts (2403, 2404, 2405) may well be provided by further depositing an insulator into the grooves (108, 109, 110, 111, 114, 115, 116, 117) which are formed by the scanning of the ion beam.

Abstract: A method of manufacturing a semiconductor device includes forming a base region and a collector region on an Si substrate, forming, on the base region, an emitter region of a semiconductor material having an energy gap larger than that of Si, forming an Si film on the emitter region, ion-implanting an element into a surface portion of the emitter region or at the interface of the emitter region and the Si film and a periphery portion of the interface, and simultaneously forming electrodes on the base and collector regions and on the Si film. A heterojunction bipolar transistor manufactured by the above method is also disclosed.

Abstract: A high speed GaAs FET is provided by forming a sandwiched GaAs channel between AlGaAs layers and employing an Si implant to provide channel doping for the GaAs channel. The poor activation efficiency of Si in AlGaAs relative to its activation efficiency in GaAs provides a channel having a higher active dopant concentration than exists in the adjacent sandwiching layers. This tends to enhance conductivity in the channel relative to the sandwiching layers.

Abstract: A method of making semiconductor laser arrays having an impurity disordered pattern of waveguides at least some of which are directly joined at branching junctions. The region near the branching junctions provides a phase boundary condition in which lightwaves propagating in adjacent waveguides are in phase. Using one impurity dose and one disordering depth in a first portion of the pattern and another in a second portion of the pattern provides a combination of strong and weak waveguiding with strong waveguides that eliminate evanescent coupling from occurring at least in the branching junction regions, and with weak guides near one or both end facets permitting evanescent coupling. The evanescent coupling between adjacent weak waveguides preserves the in phase relationship that was established in the Y-junction regions, resulting in a diffraction limited single lobe far field output.

Abstract: An improved system and method for annealing indium antimonide ion implanted junctions employing an open-tube benign annealing environment. A furnace having a hollow chamber therein is maintained continuously at a predetermined annealing temperature and wafers of indium antimonide to be annealed are inserted into the chamber through a resealable airlock at one end of the chamber. A source of molten indium saturated with antimony is provided within the chamber to maintain desired partial pressures of indium and antimony within the chamber. Hydrogen gas is continuously flushed through the chamber to purge contaminants and maintain the chamber at a desired slight overpressure over atmospheric. At the conclusion of annealing, the indium antimonide wafer is removed from the chamber into the airlock which is flushed with hydrogen gas. The wafer is allowed to cool to room temperature and removed from the airlock for subsequent processing steps.

Abstract: When high-vacuum methods are used in the manufacture of miniaturized devices such as, e.g., semiconductor integrated-circuit devices, device layers on a substrate are preferably patterned without breaking of the vacuum. Preferred patterning involves deposition of a semiconductor mask layer, generation of the pattern in the mask layer by ion deflected-beam writing, and transfer of the pattern by dry etching. When the mask layer is an epitaxial layer, further epitaxial layer deposition after patterning may proceed without removal of remaining mask layer material.

Abstract: An optical time delay unit for use in an optical phased array beam-steering system includes a switchable polarization rotator in conjunction with Brewster plates and mirrors to form electrically-selectable optical paths of different lengths. The switchable polarization rotator is aligned with the optical beam and is responsive to a control signal for varying the polarization of light passing therethrough. The Brewster plates receive the light passing through the first polarization rotator and are transmissive to a first polarization and reflective of a second. The transmissive and reflective paths are of different lengths, and are recombined at a second Brewster plate. The original polarization may be restored by a second polarization rotator. A plurality of time delay units may be cascaded to permit selection from among many paths of various lengths. In a preferred embodiment, the polarization rotators include liquid crystal cells having nematic phase molecules.

Abstract: A method of annealing a wafer in a rapid thermal annealer is disclosed. The walls of the chamber are heated more rapidly than is the wafer. In a preferred embodiment, the interior of the graphite walls of the annealer is lined with a molybdenum sheet which is open toward the lamps that heat the chamber. Thus, the walls heat very rapidly to a temperature greater than the condensation point of arsenic, preventing arsenic condensation on the walls. Effective annealing can be achieved at wall temperatures in the range of 500.degree. to 600.degree. C. Prior to the heat ramp up, an arsenic atmosphere, preferably trimethylarsenic (TMAs) at an appropriate overpressure is introduced. This overpressure is maintained both during the heating and cooling cycle. By the use of this method, the exposure time for annealing can be reduced from prior times of as much as 20 minutes to as little as 10 seconds.

Abstract: Synthetic layered structures, which may be semiconductor structures, are modified, both laterally and vertically, to provide novel electronic, optoelectronic, and optical properties. This is accomplished by selective intermixing of such layered structures through selective irradiation with laser beam or electron beam energy sources to effect interaction between neighboring regions, to a degree dependent on the energy density, while avoiding physical damage to the layered structures.

Abstract: A method for reducing the defect and dislocation density in III-V material layers deposited on dissimilar substrates is disclosed. The method involves ion implantation of dopant materials to create amorphous regions within the layers followed by an annealing step during which the amorphous regions are recrystallized to form substantially monocrystalline regions. The wafers produced by the process are particularly well suited for optoelectronic devices.

Abstract: A method of rapid thermal annealing a wafer of an ion implanted III-V compound semiconductor material by heating the wafer in close proximity to a III-V compound semiconductor wafer coated with a layer of tin or indium. A localized overpressure of the Group V element is produced by the combination of the III and V elements with the tin or indium tending to reduce surface decomposition of the implanted wafer.

Abstract: An aluminum liftoff masking process is effected on a prepared gallium arsenide wafer having a base thereon. Successive layers of silicon dioxide and aluminum are deposited on the wafer. The aluminum and silicon dioxide layers are successively etched, including undercutting of the aluminum layer. Base majority carriers are implanted through the windows to the base and refractory metal ohmic contacts are built up in the windows. After forming the base contacts, the base contact areas may be passivated. The aluminum layer and any overlaying layers thereon are removed by etching off the aluminum.

Abstract: A heterojunction transistor doped to form a specially-shaped emitter-base conduction band step or spike is disclosed. The potential barrier is then utilized to accelerate electrons across the base region at the maximum velocity obtainable without scattering electrons to the upper valleys. In this manner the electrons may be transported across the base region virtually without collisions and at a velocity approximately 10 times that of normal electron diffusion across the base region, thus increasing the frequence response of the transistor.

Abstract: A method of passivating a gallium arsenide surface includes the steps of implanting a subsurface layer of nitrogen ions and annealing and reactive the nitrogen to form a layer consisting primarily of gallium nitride.

Abstract: A method of adjusting the threshold voltages of field effect transistors fabricated on a III-V compound semi-insulating wafer includes the steps of measuring the threshold voltages of the transistor, directing an ion beam at the wafer to selectively damage the channels of the transistors, thereby shifting the threshold voltages to an interim value, and annealing the wafer at a temperature and for a time sufficient to stabilize the threshold voltages at a predetermined optimum value determined by the intensity and duration of the ion beam implantation. The III-V compound semi-insulating wafer may be GaAs. The ion beam may be supplied as protons accelerated to approximately 320 KeV with a concentration of between approximately 10.sup.11 and 10.sup.13 protons/cm.sup.-2. The wafer may be annealed at a temperature from approximately 100.degree. C. to approximately 300.degree. C. (for approximately one half hour at 300.degree. C.

Abstract: This invention is concerned with an improved Schottky-barrier gate field effect transistor, which comprises a semi-insulating semiconductor substrate, an active layer formed on the surface of the semiconductor substrate and a source electrode, Schottky-barrier gate electrode and drain electrode formed on the active layer, in which the active layer has a first part having such a thickness as to give a predetermined pinch-off voltage and being formed near the gate electrode and a second part having a substantially similar carrier concentration to that of the first part and a larger thickness than the first part and being formed between the Schottky-barrier gate electrode and source electrode, and the upper surfaces of the first part and second part of the active layer are in a same plane.

Abstract: A method of manufacturing a heterojunction bipolar transistor comprising the steps of forming a first semiconductor layer of a first conductivity type as a collector on a semiconductor substrate, forming a second semiconductor layer of a second conductivity type as a base on the first semiconductor layer, forming a third semiconductor layer of the first conductivity type as an emitter on the second semiconductor layer, the third and second semiconductor layers constituting a heterojunction, selectively forming a first mask on the third semiconductor layer, ion-implanting ions of an impurity of the second conductivity type into the resultant structure using a first mask, thereby forming an external base region of the second conductivity type extending to the second semiconductor layer, forming a second mask on a side wall of the first mask, and ion-implanting a predetermined material into the resultant structure using the first and second masks, thereby forming a high-resistance layer for isolating the externa

Abstract: Ultra low-power GaAs complementary junction field effect transistors are implemented in the design of complementary integrated circuits using a planar technology in conjunction with multiple and selective ion implantation. Both junction FETs, namely the p and n channel devices, are enhancement mode devices and biased in the forward direction thus leading to the advantageous DCFL (directly coupled field effect transistor logic) with one power supply, low power dissipation and high packing densities, all prerequisites for VLSI (very large scale integration).

Abstract: A method of capless annealing for an ion implanted substrate of a group III-V compound semiconductor, wherein said ion implanted substrate is placed in an inert ambient with a temperature ranging between 500 to 1000 degrees centigrade and a pressure ranging from 30 to 90 atmospheres, thereby increasing the deep energy level EL 2 concentration in the surface portion of a semiconductor substrate. The resistivity of the compound semiconductor substrate is increased in accordance with the deep energy level EL 2 concentration. This method is conducive to maintenance of the isolation between adjacent semiconductor elements fabricated on the group III-V compound semiconductor substrate.

Abstract: Bipolar transistors and other electronic structures are fabricated on a gallium arsenide (GaAs) substrate to form an integrated circuit device. This process is made possible by development of an ion implant technique which uses an acceptor material to create a P type region, boron or protons to create insulating regions, and silicon or selenium to create an N type region. The process avoids the difficult problems encountered in diffusion methods, and, due to the precise control available with the ion implant method, makes possible the fabrication of IC quality transistors consistently over a substrate. This same control enables the fabrication of integrated circuits with improved device packing density and reduced parasitic parameters.

Abstract: A method of converting selected areas of a semiconductor structure into a disordered alloy comprising a well feature epitaxially deposited on a semiconductor support, the well feature comprising at least one first well layer of narrow bandgap material deposited adjacent to at least a second layer of wider bandgap material or interposed between second and third layers of wider bandgap material. The disordered alloy exhibits higher bandgap and lower refractive index properties than the first layer.

Abstract: High transconductance is obtained in GaAs FET's by forming a channel layer having a carrier concentration monotonously decreasing from the interface of the channel layer and a control gate toward the interface of the channel layer and the substrate it is formed in. This is established by ion implantation of the channel layer through an insulating layer, preferably an AlN layer, on a GaAs substrate. An AlN layer is preferable since it has no adverse effects on the GaAs substrate during ion implantation and the following heat treatment, allowing higher uniformity of the threshold voltages of the FET's.

Abstract: A Schottky diode and method of making same in which a n+ doped layer, an n oped layer and an undoped layer of a semi-insulating material selected from the group consisting of gallium arsenide, aluminum gallium arsenide and indium phosphide is grown consecutively on a semi-insulating substrate made of the same material. A mesa with acute angled sides is etched on the undoped layer to such a depth that the n doped layer is exposed. A Schottky and ohmic contact are then deposited on opposite sides of the mesa. The exposed n layer is then bombarded with protons at normal incidence.

Abstract: A method is disclosed for converting a multilayer semiconductor structure, that includes active semiconductor regions interposed between semiconductor barrier layers, into a disordered alloy by introduction of a specified disordering element into the multilayer structure. Devices made using the method are also disclosed.

Abstract: When the collector, base and emitter layers of a heterojunction bipolar transistor or a tunneling hot electron transistor are vertically stacked, the thickness of the base layer is preferably small so as to increase the current gain or switching speed. A thin base layer, however, has a disadvantage in that a space of the base layer between the actual base region and the base electrode makes the base resistance too large, decreasing current gain or switching speed, or is fully depleted due to interface states, making the transistor inoperable. This disadvantage is eliminated by forming a base contact region by doping in a region in alignment with the edge of an electrode so as to remove said space, that is, the base contact region is in contact with the actual base region.

Abstract: A method of manufacturing GaAs semiconductor devices includes the steps of emplacing doping impurities by ion implantation on at least one surface of a GaAs substrate, and a step of annealing to remove damage resulting from the implantation of the impurities in the GaAs material. Prior to the annealing, a silicon capping layer is deposited on the surface by either sputtering, evaporation, or vapor deposition to a thickness of 100-10,000 angstroms. Subsequent to the annealing, the silicon capping layer is removed by etching. The silicon cap prevents out-diffusion of arsenic from the GaAs, and has a coefficient of thermal expansion which is sufficiently close to that of the GaAs to inhibit the formation of cracks in the capping layer.

Abstract: A heterojunction bipolar transistor having an n- type epitaxial indium phosphide collector layer grown on a semi-insulating indium phosphide substrate with an n+ buried layer, a p- type indium phosphide base and an epitaxial, n- type boron phosphide wide gap emitter. The p- type base region is formed by ion implantation of magnesium ions into the collector layer. The transistor is applicable to millimeter wave applications due to the high electron mobility in the indium phosphide base. The wide gaps of both the boron phosphide (2.2 eV) and indium phosphide (1.34 eV) permit operation up to 350.degree. C. The transistor is easily processed using metal organic-chemical vapor deposition (MO-CVD) and standard microelectronic techniques.

Abstract: A process is described for fabricating semiconductor devices in which atomic hydrogen is used to neutralize shallow donors in III-V semiconductor compounds so as to make certain areas exhibit high resistance. Also described is reverse neutralization in which heat is used to convert neutralized regions to regions with n-type conductivity.

Abstract: A method of preparing an active surface layer on a semi-insulating GaAs substrate comprising the steps of ion implanting a surface layer with silicon to form an n-type active layer and ion implanting a buried diffusion layer beneath the active layer with boron to prevent defects in the substrate from influencing the active region. The method is particularly useful for GaAs MESFETs.

Abstract: The property of materials in the GaAs/AlGaAs system, whereby at certain doses proton bombarded n-type material becomes highly resistive but p-type material remains highly conductive, is utilized to fabrication of integrated circuits which include buried semiconductor interconnections or bus bars between devices.

Abstract: The property of materials in the InP system, whereby helium ion or deuteron bombarded p-type material becomes highly resistive but n-type material remains relatively conductive, is utilized to fabricate integrated circuits which include buried semiconductor interconnections or bus bars between devices.

Abstract: The quality of a compound semiconductor crystal such as gallium arsenide used for an integrated circuit is upgraded by a method comprising optionally forming a protective film on the obverse surface and reverse surface of a substrate consisting of a compound semiconductor crystal, subjecting the substrate to a heat treatment in an inert atmosphere at a temperature of at least the same as the activating temperature after the ion implantation into the substrate and then optionally revmoving the protective film.

Abstract: A gallium arsenide transistor is provided having a self-aligned base enhancement to emitter region and a method of applying metal to the emitter region. A series of steps provide an NPN structure overlying a substrate and includes an N region of aluminum gallium arsenide overlying a P base region for increasing the efficiency of the base-emitter junction by eliminating the need for a very heavily doped emitter at the surface of the chip. Two masking layers, one overlying the other, are deposited over the N emitter region and are patterned by known photoresist methods. The P base region is enhanced by implanting beryllium ions therein and partially into the N collector region. This ion implantation is blocked by the masking layers, creating a base enhancement region aligned with the emitter region. An etching process then undercuts the lower masking layer before the upper masking layer is removed. A photoresist is deposited on the surface and the lower masking layer is removed.

Abstract: Ions are selectively implanted into layers of a semiconductor substrate of, for example, semi-insulating gallium arsenide via a photoresist implantation mask and a metallic layer of, for example, titanium, disposed between the substrate surface and the photoresist mask. After implantation the mask and metallic layer are removed and the substrate heat treated for annealing purposes. The metallic layer acts as a buffer layer and prevents possible contamination of the substrate surface, by photoresist residues, at the annealing stage. Such contamination adversely affects the electrical properties of the substrate surface, particularly gallium arsenide substrates.

Abstract: Ion implanted gallium arsenide substrates are annealed by providing an arsenic-containing gaseous ambient on all sides of the substrate, and heating the gallium arsenide substrate with broad area incoherent light.

Abstract: A method of producing patternable resistive regions in III-V compound semiconductor devices and a resulting device structure having improved current characteristics. III-V semiconductor substrates are irradiated with inert ions to produce a resistive region therein. At least one epitaxial layer is grown over the substrate while maintaining the resistive characteristics within the substrate. A second resistive region is then formed in at least the top epitaxial layer. This second resistive region is aligned with the first one in order to minimize current spread through the device.

Abstract: A method of improving field-effect transistors, and the product thereof, wherein the resistivity of the upper layer of the source-gate channel region of a GaAs field-effect transistor (FET) may be selectively raised is disclosed. Impurity ions are implanted in the source-gate channel region followed by a much shallower implantation of boron in the same region. The boron ion concentration should exceed the N+ impurity ion concentration by a factor of 2 or more.