Laser Beam Treatment In General Patents (Class 148/DIG93)
  • Patent number: 4816422
    Abstract: A method for fabricating a composite semiconductor from a plurality of substantially identical individual semiconductor devices formed on a common semiconductor wafer includes testing the devices on the wafer to generate a positional mapping of acceptable and non-acceptable devices, dividing the wafer into a plurality of areas of arbitrary size, connecting corresponding contact pads on only the acceptable devices within a given area to each other via common conductive paths which are supported on a dielectric film covering the pads, the film having appropriately located holes filled with conductive material to electrically couple the common conductive paths and the underlying contact pads of only the acceptable devices. The devices within a given area are intercoupled in a manner to form an operational array; single or multiple arrays may be coupled together to form a composite package having common external contacts and heat sink supports.
    Type: Grant
    Filed: December 29, 1986
    Date of Patent: March 28, 1989
    Assignee: General Electric Company
    Inventors: Alexander J. Yerman, Constantine A. Neugebauer
  • Patent number: 4814289
    Abstract: Thin-film capacitors are produced with laser chemical vapor deposition technology on a substrate, which is preferably the substrate of an integrated circuit, by forming alternating layers of electrodes and dielectric.
    Type: Grant
    Filed: December 21, 1987
    Date of Patent: March 21, 1989
    Inventor: Dieter Baeuerle
  • Patent number: 4800173
    Abstract: Process for producing a valence electron controlled functional crystalline film by introducing (i) a film forming gaseous raw material, (ii) a halogen series gaseous oxidizing agent to oxidize the raw material (i), and (iii) a gaseous raw material to impart a valence electron controlling agent separtely into a reaction region of a film deposition space and chemically reacting them to generate plural kinds of precursors containing excited precursors and to let at least one kind of said precursors to act as a film forming supplier whereby said crystalline film is formed on a selected substrate being kept at a predetermined temperature in the film deposition space.
    Type: Grant
    Filed: February 18, 1987
    Date of Patent: January 24, 1989
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Kanai, Junichi Hanna, Isamu Shimizu
  • Patent number: 4800179
    Abstract: A method for fabricating a semiconductor device comprises forming a contact hole in an insulating film formed on a first wiring composed of an Al film, covering the insulating film with an Al film for a second wiring, applying laser beam pulses to the Al film for a second wiring from above, and patterning the Al film to form a second wiring.
    Type: Grant
    Filed: June 12, 1987
    Date of Patent: January 24, 1989
    Assignee: Fujitsu Limited
    Inventor: Ryoichi Mukai
  • Patent number: 4764485
    Abstract: A method for producing a hole in a polymer film includes the steps of depositing a conductive layer onto the polymer film and irradiating a spot on the layer with a burst of focused laser energy at a level sufficient to form an opening in the film and, subsequently, plasma etching the film so as to form a hole of desired depth in the polymer film underlying the opening in the conductive layer. This method is particularly applicable to the formation of multichip intergrated circuit packages in which a plurality of chips formed in a semiconductor wafer are coated with a polymer film covering the chips and the substrates. The holes are provided for the purpose of interconnecting selected chip contact pads via a deposited conductive layer which overlies the film and fills the holes.
    Type: Grant
    Filed: January 5, 1987
    Date of Patent: August 16, 1988
    Assignee: General Electric Company
    Inventors: James A. Loughran, James G. McMullen, Alexander J. Yerman
  • Patent number: 4764476
    Abstract: A method of making a photoelectric conversion device with a substrate having an insulating surface, and a plurality n of non-single crystal semiconductor photoelectric conversion elements U.sub.1 to U.sub.n sequentially formed side by side on the substrate and connected in series one after another, which eliminates leakage between electrodes and attains a high photoelectric conversion efficiency. The active portion of each element U.sub.1 to U.sub.n is selectively annealed by light irradiation to increase its crystallinity, hence conductivity. The intercell coupling portion has a high resistance to current leakage.
    Type: Grant
    Filed: May 19, 1987
    Date of Patent: August 16, 1988
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 4758533
    Abstract: Nonrefractory micrometer-thick deposited metal or metallization, for example, aluminum and aluminum alloy films, on integrated circuits are planarized by momentarily melting them with optical pulses from a laser, such as a xenon chloride excimer laser. The substrate, as well as any intervening dielectric and conducive layers, are preheated to preferably one-half the melting temperature of the metal to be planarized, thereby enhancing reflow of the metal upon melting. This improves planarization and reduces stress in the resolidified metal. Laser planarization offers an attractive technique for fabricating multilayer interconnect structures, particularly where a number of ground or power planes are included. Excellent step coverage and via filling is achieved without damaging lower layers of interconnect.
    Type: Grant
    Filed: September 22, 1987
    Date of Patent: July 19, 1988
    Assignee: XMR Inc.
    Inventors: Thomas J. Magee, John F. Osborne, Peter Gildea, Charles H. Leung
  • Patent number: 4755475
    Abstract: A method of manufacturing a photovoltaic device, in which a plurality of photoelectric conversion elements comprising a first electrode layer, a semiconductive layer and a second electrode layer are laminatedly arranged on an insulative surface of a substrate and said photoelectric conversion elements are electrically connected in series with each other, comprising a step of dividedly arranging the first electrode layer on the surface of the substrate, a step of coating the semiconductive layer on the surface of the substrate including the upper surface of the divided first electrode layer, a step of coating the second electrode layer on the semiconductive layer, and a step of dividing the semiconductive layer and/or the second electrode layer in order to define each element by irradiating energy-beams on the semiconductive layer and/or the second electrode layer.
    Type: Grant
    Filed: February 17, 1987
    Date of Patent: July 5, 1988
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Seiichi Kiyama, Yasuaki Yamamoto, Hideki Imai, Yutaka Hirono
  • Patent number: 4751193
    Abstract: Method is provided for manufacturing large crystalline and monocrystalline semiconductor-on-insulator devices.
    Type: Grant
    Filed: October 9, 1986
    Date of Patent: June 14, 1988
    Assignee: Q-Dot, Inc.
    Inventor: James J. Myrick
  • Patent number: 4743567
    Abstract: A structure comprising thin defect-free monocrystalline layer of a silicon of an insulating layer is produced from a structure comprising a thin recrystallizable layer of silicon on an insulating layer by use of a low softening point insulating layer, scanning the structure relative to a zone heater the beams of which are focused on the recrystallizable silicon layer so as to form a melt zone having a convex solid-liquid interface in the silicon layer while forming a liquid area under the melt zone in the insulating layer.
    Type: Grant
    Filed: August 11, 1987
    Date of Patent: May 10, 1988
    Assignee: North American Philips Corp.
    Inventors: Ranjana Pandya, Andre M. Martinez
  • Patent number: 4729962
    Abstract: The process of the invention includes applying precursors 6 with N- and P-type dopants therein to a silicon web 2, with the web 2 then being baked in an oven 10 to drive off excessive solvents, and the web 2 is then heated using a pulsed high intensity light in a mechanism 12 at 1100.degree.-1150.degree. C. for about 10 seconds to simultaneously form semiconductor junctions in both faces of the web.
    Type: Grant
    Filed: March 24, 1986
    Date of Patent: March 8, 1988
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventor: Robert B. Campbell
  • Patent number: 4714684
    Abstract: In a method of manufacturing a semiconductor device of a three-dimensional structure having a semiconductor substrate and another single crystal semiconductor layer formed thereon, the another single crystal semiconductor layer is prepared by melting a vapor-deposited amorphous or polycrystalline semiconductor layer by the energy of laser beams then solidifying and converting the layer into single crystals. For initiating the melting at selected regions of the layer, the layer is formed at the surface thereof with a silicon nitride film of a uniform thickness and a silicon nitride film with a thickness at the region corresponding to the selected region different from that of the remaining region. The region thicker or thinner than other region reflects the laser energy at different reflectivity thereby to provide a desired temperature distribution.
    Type: Grant
    Filed: March 26, 1986
    Date of Patent: December 22, 1987
    Assignee: Agency of Industrial Science and Technology
    Inventors: Kazuyuki Sugahara, Tadashi Nishimura, Shigeru Kusunoki, Yasuo Inoue
  • Patent number: 4692190
    Abstract: Semiconductor body is prepared and a film is formed on the semiconductor body, followed by forming an interconnection layer of aluminum alloy on the insulating film. A silicon oxide film is formed on the interconnection layer, followed by removing that portion of the silicon oxide film which is situated on a predetermined trimming area of the interconnection layer. A silicon nitride film is formed on the whole surface of the resultant structure. An energy beam is directed onto the predetermined trimming area of the interconnection layer, causing the interconnection layer to be locally heated to 400.degree. to 600.degree. C. whereby atoms in the interconnection layer migrate to permit the interconnection layer to be trimmed.
    Type: Grant
    Filed: December 24, 1985
    Date of Patent: September 8, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeru Komatsu
  • Patent number: 4691434
    Abstract: In the manufacture of semi-custom integrated circuits silicon wafers with P and N or N and P structures are used, and interconnections to establish a specific application must be created. Unlike currently known technologies, electrically conductive film with standardized openings made according to a pre-arranged raster must be deposited on the silicon wafer. Subsequently the conductive film, will be removed from between the openings directly or indirectly by means of electromagnetic radiation in order to produce the required circuit configuration. A laser beam is particularly appropriate for this since it can be positioned and controlled, and can be used directly for the exposure of a photosensitive film. The creation of insular conductive film is then achieved through a photo- etch technique. By use of this process, an expensive customer specific photo mask can be avoided.
    Type: Grant
    Filed: February 4, 1983
    Date of Patent: September 8, 1987
    Assignee: Lasarray Holding AG
    Inventors: Richard Percival, Ernst Uhlmann
  • Patent number: 4685976
    Abstract: A semiconductor processing technique is disclosed for forming a multi-layered semiconductor structure in a single chamber and with the same equipment, without removing the semiconductor wafer substrate or otherwise transferring it to another chamber. A gaseous mixture of different gases is provided in a chamber. Excimer pulsed ultraviolet laser radiation is introduced into the chamber at a first discrete wavelength to photolytically react with a first of the gases at a discrete excitation energy photochemically breaking bonds of the first gas to epitaxially deposit a first layer on the substrate, followed by radiation at a second discrete wavelength to photolytically react with a second gas to deposit a second layer on the first layer, and so on. The different gases may be introduced into the chamber collectively, or serially between radiations. Scavenging between layers is provided by photolytic removal of surface containments and the products of reaction.
    Type: Grant
    Filed: May 22, 1985
    Date of Patent: August 11, 1987
    Assignee: Eaton Corporation
    Inventors: Steven R. Schachameyer, James A. Benjamin, John B. Pardee, Lyle O. Hoppie
  • Patent number: 4681640
    Abstract: Germanium and doped-germanium polycrystalline films are formed using photolytic CO.sub.2 laser-induced chemical vapor deposition method. Germanium being transparent to IR light makes the production of high purity polycrystalline germanium and doped-germanium films from starting compounds of germane, ethylgermane diethylgermane, and triethylgermane ideally adapted to the laser induced infrared radiation provided by the tunable, continuous-wave CO.sub.2 laser which delivers infrared laser radiation in the range of 10.4 or 9.4 micrometers. Triethylgermane produces germanium in a quantity usable as a dopant. Scanning electron microscopy is used for analysis of the films. The products identified on irradiation of germane are germanium and hydrogen. Conversion rates on the order of 86% are readily obtained. On irradiation of diethylgermane and ethylgermane, ethylene, germane, germanium and hydrogen are produced.
    Type: Grant
    Filed: August 6, 1986
    Date of Patent: July 21, 1987
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Ann E. Stanley
  • Patent number: 4674176
    Abstract: In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.
    Type: Grant
    Filed: June 24, 1985
    Date of Patent: June 23, 1987
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventor: David B. Tuckerman
  • Patent number: 4670063
    Abstract: A semiconductor processing technique is disclosed for periodically selectively effecting lattice ordering and dopant distribution during a semiconductor layer formation process. Excimer pulsed ultraviolet laser radiation is provided at different energy fluxes to provide an electrically active layer as formed, without post-annealing, and curing lattice damage otherwise due to certain processing methods such as ion implantation. In a photolytic deposition technique, excimer laser radiation is periodically increased to transiently provide a pyrolytic thermal reaction in the layer as thus far deposited to provide a plurality of short intermittent periodic annealing steps to ensure crystallization as the layer continues to be deposited at lower radiation energy fluxes. Single crystalline material may be formed without post-annealing by periodically irradiating incremental thicknesses of the layer as formed.
    Type: Grant
    Filed: April 10, 1985
    Date of Patent: June 2, 1987
    Assignee: Eaton Corporation
    Inventors: Steven R. Schachameyer, James A. Benjamin, John B. Pardee, Lyle O. Hoppie
  • Patent number: 4668304
    Abstract: A dopant gettering semiconductor processing technique is disclosed for selectively activating an otherwise benign reactant to remove dopant from a semiconductor wafer substrate. Excimer pulsed ultraviolet laser radiation is provided at a discrete designated pulsed wavelength corresponding to a discrete designated gettering excitation energy of the otherwise benign reactant photochemically breaking bonds of the reactant such that the reactant is photolytically activated to remove dopant from the substrate, without thermally driven pyrolytic reaction. The bonds of a reactant gas are photochemically broken to produce gettering agents reacting with the substrate to remove dopant by forming a gaseous compound liberated from the substrate and benign to and unactivated by the discrete designated wavelength of the excimer pulsed ultraviolet laser radiation.
    Type: Grant
    Filed: April 10, 1985
    Date of Patent: May 26, 1987
    Assignee: Eaton Corporation
    Inventors: Steven R. Schachameyer, James A. Benjamin, John B. Pardee, Lyle O. Hoppie, Herman P. Schutten
  • Patent number: 4663826
    Abstract: A method for generating an area of increased conductivity on the surface of a body of dielectric material, such as for the purpose of attaching electrodes or other electrical interconnections to the area includes the steps of enclosing the surface within a reducing atmosphere and irradiating the portion of the surface corresponding to the desired conductive area with laser radiation for a selected period of time. The atmosphere may be a hydrogen atmosphere at a pressure in the range of 0-1000 HPa. Additionally, the surface may be preheated prior to irradiation.
    Type: Grant
    Filed: September 23, 1985
    Date of Patent: May 12, 1987
    Inventor: Dieter Baeuerle
  • Patent number: 4662949
    Abstract: In an apparatus for forming a single crystal semiconductor layer from a non-single-crystalline semiconductor material by scanning a region of the material with an electron beam, a first pair of deflection electrodes and a second pair of deflection electrodes, both pairs being provided in the path of the electron beam. A deflection signal generated by modifying the amplitude of a high-frequency fundamental wave signal with a modulation wave signal having a frequency lower than that of the high-frequency fundamental wave signal is supplied to the deflection electrodes of the first pair. The electrodes rapidly deflect the electron beam in a first direction, while changing the range of deflecting the beam, thereby forming a locus of the beam spot on the sample. Simultaneously, the deflection electrodes of the second pair deflect the beam in a second direction, thereby annealing a region of the material, to form a single crystal semiconductor layer.
    Type: Grant
    Filed: August 5, 1985
    Date of Patent: May 5, 1987
    Assignee: Director-General of Agency of Industrial Science and Technology
    Inventors: Tomoyasu Inoue, Hiroyuki Tango, Kyoichi Suguro, Iwao Higashinakagawa, Toshihiko Hamasaki
  • Patent number: 4655850
    Abstract: A new method of manufacturing semiconductor devices, in which monocrystalline thin film is formed by melting and recrystallizing either amorphous or polycrystalline thin film via annealing by radiation of energy beams, wherein the manufacturing method comprises the formation of a belt-shaped high melting point metal film having a width narrower than the diameter of the radiated energy beams on either an amorphous or polycrystalline thin film and beam scanning in parallel with the belt, by means of radiating energy beams, onto the belt-shaped high melting point metal film, so as to generate a nucleus in a limited area beneath the belt-shaped thin film at the moment the film-covered amorphous or polycrystalline area dissolves recrystallizes so that the said recrystallized area eventually grows into a monocrystalline configuration.
    Type: Grant
    Filed: July 1, 1985
    Date of Patent: April 7, 1987
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seizo Kakimoto, Jun Kudo, Masayoshi Koba
  • Patent number: 4655849
    Abstract: A semiconductor processing technique is disclosed for reasonantly reacting with a semiconductor wafer substrate and cleaving surface atomic bonds to create dangling bonds. The substrate is irradiated with excimer pulsed ultraviolet laser radiation at a discrete designed wavelength to resonantly photolytically cleave surface bonds and create the dangling bonds. This enhances further processing operations such as single crystalline silicon deposition and enhanced bonding and growth thereof.
    Type: Grant
    Filed: May 22, 1985
    Date of Patent: April 7, 1987
    Assignee: Eaton Corporation
    Inventors: Steven R. Schachameyer, James A. Benjamin, John B. Pardee, Lyle O. Hoppie
  • Patent number: 4649624
    Abstract: This invention relates to a process of manufacturing an integrated structure in which optical signals can be processed in an electrooptic material such as lithium tantalate and electrical signals can be processed in a semiconductor material such as silicon. Microelectronic semiconductors are fabricated in the semiconductor material and electrooptic devices are fabricated in the electrooptic material. Devices made by the process of the present invention are also disclosed.
    Type: Grant
    Filed: October 3, 1983
    Date of Patent: March 17, 1987
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Ronald E. Reedy
  • Patent number: 4623403
    Abstract: A target for a laser beam consists of a plurality of closely spaced lines that causes the generation of an readily-identifiable read-out so that the laser beam can be indexed when performing laser scribing for redundant memory devices or the like.
    Type: Grant
    Filed: June 15, 1984
    Date of Patent: November 18, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Kendall S. Wills, Paul A. Rodriguez
  • Patent number: 4602420
    Abstract: A method of manufacturing a semiconductor device including the steps of forming a passivation film, which has an opening exposing that region of the interlayer insulation film formed on the fuse element, which corresponds to the region to be melted of fuse element, melting the region of the fuse element to be melted by radiating a laser beam on the exposed region of the interlayer insulation film through the opening, and the step of forming a protective resin layer on the whole main surface of the resultant structure after melting is completed.
    Type: Grant
    Filed: December 13, 1984
    Date of Patent: July 29, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shozo Saito
  • Patent number: 4561906
    Abstract: An integrated circuit is fabricated with some redundant capacity by forming potential electrically conducting links which can subsequently be made electrically when extra circuit capacity is required. Field oxide is grown on a silicon substrate and then a layer of polysilicon deposited over the oxide. At the redundancy sites where electrical connections may subsequently be made, an anti-reflective silicon nitride coating is deposited and photodefined. The areas of this coating are used as masks in order to diffuse dopant into the polysilicon at parts of the polysilicon laterally adjacent the redundancy sites. When later it is necessary to bring spare capacity into the circuit the complete circuit is scanned with a continuous wave laser. The laser melts the polysilicon under the nitride mask permitting the dopant to diffuse from the adjacent parts of the polysilicon and so form a conducting link.
    Type: Grant
    Filed: October 24, 1983
    Date of Patent: December 31, 1985
    Assignee: Northern Telecom Limited
    Inventors: Iain D. Calder, Hussein M. Naguib
  • Patent number: 4545823
    Abstract: Regular arrays of grain boundary free silicon islands have been produced in a silicon on insulator (SOI) structure by using a pattern antirelfective coating in combination with a laser scanning technique. The antireflective coating pattern is made up of a series of parallel stripes terminating in seeding windows. A laser beam is scanned perpendicular to the stripes and over at least two stripes simultaneously, with the long axis of the beam parallel to the scan direction. Grain boundaries are confined to the region under the antireflective stripes.
    Type: Grant
    Filed: November 14, 1983
    Date of Patent: October 8, 1985
    Assignee: Hewlett-Packard Company
    Inventor: Clifford I. Drowley
  • Patent number: 4536231
    Abstract: A method for forming a polysilicon thin film semiconductor device precursor, and the precursor, are disclosed, wherein the deposited thin film layer is scanned with a continuous wave laser in a first direction, and scanned a second time in a direction different from that of the first direction. The cross-scanning reduces the anisotropy of the thin film produced by the first scanning and apparently induces larger grain size in the recrystallized polysilicon.
    Type: Grant
    Filed: May 22, 1984
    Date of Patent: August 20, 1985
    Assignee: Harris Corporation
    Inventor: Alan J. Kasten