With Mechanical Mask Or Shield Or Shutter For Shielding Workpiece Patents (Class 156/345.19)
  • Patent number: 6746503
    Abstract: A system for separating particles entrained in a fluid includes a base with a first channel and a second channel. A precision gap connects the first channel and the second channel. The precision gap is of a size that allows small particles to pass from the first channel into the second channel and prevents large particles from the first channel into the second channel. A cover is positioned over the base unit, the first channel, the precision gap, and the second channel. An port directs the fluid containing the entrained particles into the first channel. An output port directs the large particles out of the first channel. A port connected to the second channel directs the small particles out of the second channel.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: June 8, 2004
    Assignee: The Regents of the University of California
    Inventors: William J. Benett, Robin Miles, Leslie M. Jones, II, Cheryl Stockton
  • Publication number: 20040099375
    Abstract: An embodiment of the invention is an edge-contact ring 15 used to support a wafer 3 on a pedestal plate 16.
    Type: Application
    Filed: November 21, 2002
    Publication date: May 27, 2004
    Inventors: Yanghua He, Chad J. Kaneshige, Michael S. Wang
  • Patent number: 6733616
    Abstract: A surface isolation device for isolating a predetermined area of a second surface of a wafer from an etching solution while the etching solution etches a first surface of the wafer to form a plurality of manifolds in the wafer. The surface isolation device has a base for positioning the wafer, a fixture for fixing the wafer on the base, and an isolation ring positioned on the base for isolating the predetermined area from the etching solution. When the fixture fixes the wafer on the base, the wafer sticks to the isolation ring, forming a seal that isolates the predetermined area from the etching solution.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: May 11, 2004
    Assignee: BenQ Corporation
    Inventors: Hung-Sheng Hu, Tsung-Ping Hsu, Wei-Lin Chen, Chung-Cheng Chou, In-Yao Lee
  • Patent number: 6682629
    Abstract: The present invention is a processing unit for processing a substrate in a casing, having: a transfer port provided in the casing through which the substrate passes when the substrate is carried into the casing by a carrier for carrying the substrate; and an inflow restricting device for controlling an atmosphere outside the casing to restrict the atmosphere from flowing into the casing through the transfer port. According to the present invention, it is possible to control the atmosphere outside the casing to restrict the atmosphere from flowing into the casing, which restricts the temperature of the substrate in the processing unit from partially varying and the temperature distribution from becoming ununiform within a plane of the substrate.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: January 27, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Hiroyuki Kudo, Takahiro Okubo, Minoru Kubota
  • Patent number: 6649077
    Abstract: A method and an apparatus for removing coating layers from the top of alignment marks on a wafer situated in a spin processor are described. The method may be carried out by first providing a spin process equipped with a rotatable wafer pedestal, then providing a wafer that has at least one alignment mark covered by a coating layer, mounting an edge ring on an outer periphery of the wafer pedestal, the edge ring has at least one tab section extending outwardly from an inner periphery of the edge ring, then positioning the wafer faced down and supported by an inert gas flow on the edge ring such that a narrow gap is formed between the tab section on the edge ring and the alignment marks and dispensing an etchant onto a backside of the wafer while rotating.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: November 18, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd
    Inventors: Pang-Yen Tsai, Tien-Chen Hu, Sen-Shan Yang, Wei-Cheng Ku
  • Patent number: 6589385
    Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: July 8, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Akiyuki Minami, Satoshi Machida
  • Patent number: 6579408
    Abstract: An apparatus and a method for mounting a wafer and etching a wafer backside in an etchant solution are provided. The apparatus is constructed by a first circular disc that has a first sidewall integrally formed, a gas inlet in the first circular disc or the first sidewall, a second circular disc that has a second sidewall integrally formed for positioning inside the first circular disc and forming a first cavity therein between, a third circular disc that has a third sidewall integrally formed for positioning inside the second circular disc and forming a second cavity therein between, a gas outlet in the second circular disc for withdrawing air from the second cavity, and sealing means positioned on top of the sidewalls for providing a substantially sealed second cavity when a wafer is positioned on top of the sidewalls.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: June 17, 2003
    Assignee: Industrial Technology Research Institute
    Inventors: Hui Chi Su, Song Tsang Chiang
  • Publication number: 20030073309
    Abstract: The present invention generally provides an improved apparatus and method for removing an edge bead from a substrate. The apparatus includes a processing chamber having an edge bead removal fluid distribution system positioned therein and a substrate support member positioned in the processing chamber proximate the fluid distribution system. The substrate support member generally includes an upper substrate support surface having a plurality of fluid dispensing apertures formed therein, at least three capillary ring support posts radially positioned about a perimeter of the upper substrate support surface, and a annular capillary ring having a planar upper surface rigidly mounted to the capillary ring support posts.
    Type: Application
    Filed: October 16, 2001
    Publication date: April 17, 2003
    Applicant: Applied Materials, Inc.
    Inventor: Ramin Emami
  • Publication number: 20030070755
    Abstract: The present invention provides an apparatus for removing an edge bead from a substrate. The apparatus includes a substrate support member, a plurality of mounting posts positioned along a perimeter of the substrate support member, and a rigid annular capillary ring mounted to the plurality of mounting posts. The rigid annular capillary ring includes a substantially planar upper capillary surface and is configured to maintain the substantially planar capillary surface when attached to the mounting posts.
    Type: Application
    Filed: October 16, 2001
    Publication date: April 17, 2003
    Applicant: Applied Materials, Inc.
    Inventor: Ramin Emami
  • Publication number: 20020174951
    Abstract: A surface isolation device for isolating a predetermined area of a second surface of a wafer from an etching solution while the etching solution etches a first surface of the wafer to form a plurality of manifolds in the wafer. The surface isolation device has a base for positioning the wafer, a fixture for fixing the wafer on the base, and an isolation ring positioned on the base for isolating the predetermined area from the etching solution. When the fixture fixes the wafer on the base, the wafer sticks to the isolation ring, forming a seal that isolates the predetermined area from the etching solution.
    Type: Application
    Filed: May 21, 2002
    Publication date: November 28, 2002
    Inventors: Hung-Sheng Hu, Tsung-Ping Hsu, Wei-Lin Chen, Chung-Cheng Chou, In-Yao Lee
  • Patent number: 6485655
    Abstract: An internal coating on an internal passage wall exposed at a passage opening through an article external surface is protected from removal during repair of the article, including removal of at least a portion of an external coating, by a masking assembly disposed about the passage opening. The masking assembly comprises a masking member and a substantially flexible seal, substantially inert to a coating removal medium for the external coating. The masking member is shaped for disposition about the passage opening across a gap between the external surface and the masking member. The substantially flexible seal is disposed across the gap substantially to seal the gap.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: November 26, 2002
    Assignee: General Electric Company
    Inventors: Nripendra Nath Das, Stephen Joseph Ferrigno, Jim Dean Reeves, Michael Glenn Gordon
  • Publication number: 20020153097
    Abstract: A system for optionally depositing or etching a layer of a wafer includes mask plate opposed to the wafer with the mask plate having a plurality of openings that transport a solution to the wafer. An electrode assembly has a first electrode member and a second electrode member having channels that operatively interface a peripheral and center part of the wafer. The channels transport the solution to the mask.
    Type: Application
    Filed: April 23, 2001
    Publication date: October 24, 2002
    Applicant: NuTool, Inc.
    Inventors: Bulent M. Basol, Cyprian Uzoh, Halit N. Yakupoglu, Homayoun Talieh
  • Publication number: 20020032940
    Abstract: In a method for polishing leads of a semiconductor package, a plurality of semiconductor packages is arranged in a certain manner. Then, the leads are automatically polished. The semiconductor packages may be masked to expose at least a part of the leads to be polished.
    Type: Application
    Filed: November 28, 2001
    Publication date: March 21, 2002
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Takeyuki Sato