Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract: A multilayer electronic component includes a body including first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction and including a dielectric layer and internal electrodes alternately disposed with the dielectric layer interposed therebetween in the first direction, and external electrodes disposed on the third and fourth surfaces, wherein the external electrodes include an electrode layer disposed on the body and a conductive resin layer disposed on the electrode layer, and the conductive resin layer includes a conductive metal, an epoxy resin, and an acrylic resin.

Abstract: The present disclosure provides a resin composition for a metal substrate, and a resin varnish and a metal base copper-clad laminate comprising the same. The resin composition comprises 5-40% of a main resin and 60-95% of a thermally conductive filler when the total weight of the resin composition is calculated as 100%, wherein the main resin comprises 60-90% of a flexible epoxy resin having a structure as shown in Formula I and 10-40% of a phenoxy resin when the total weight of the main resin is calculated as 100%. The resin composition provided by the present disclosure has a low modulus, can alleviate the stress generated by thermal shocks and can withstand more than 1000 thermal cycles.

Abstract: A process for conformally coating passive surface mount components soldered to a printed circuit substrate of a lidless flip-chip ball grid array package includes affixing a stiffener ring to the substrate before forming a conformal coating on the passive surface mount components. The stiffener ring is affixed to the substrate so that the plurality of passive surface mount components and the integrated circuit die are contained within an opening formed by the stiffener ring. After affixing the stiffener ring to the substrate, the conformal coating is formed on the passive surface mount components. The conformal coating extends over each of the passive surface mount components, around a periphery of each of the passive surface mount components, and under each of the passive surface mount components. A product made according to the process is also disclosed.

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate having at least two different dielectric layers with different dielectric materials and methods for fabricating the same. One example embedded trace substrate generally includes a first metal layer; a first dielectric layer disposed below the first metal layer and comprising a first dielectric material; a second dielectric layer disposed below the first dielectric layer and comprising a second dielectric material, wherein the second dielectric material of the second dielectric layer is stiffer than the first dielectric material of the first dielectric layer; and a second metal layer disposed below the second dielectric layer.

Abstract: Hermeticity of an annular sealing bonding material to seal a vibrating part is improved. In the crystal resonator 10, a resonator-plate-side first bonding pattern 251 annularly formed on a crystal resonator plate 2 is bonded to a sealing-member-side first bonding pattern 321 annularly formed on a first sealing member 3, and a resonator-plate-side second bonding pattern 252 annularly formed on the crystal resonator plate 2 is bonded to a sealing-member-side second bonding pattern 421 annularly formed on a second sealing member 4. Thus, annular bonding materials 11a and 11b, which hermetically seal a vibrating part 22 causing piezoelectric resonance, are formed. Inner peripheral edge parts 111a and 111b and outer peripheral edge parts 112a and 112b of the bonding materials 11a and 11b are formed denser than intermediate parts 113a and 113b between the inner and outer peripheral edge parts 111a and 112a, and between the inner and outer peripheral edge parts 111b and 112b.

Abstract: A method of manufacturing a ceramic electronic component such that Voids of the ceramic element and voids at the interfaces between the ceramic element and the external electrodes are filled with a resin composition by applying, to the ceramic electronic component, a resin-containing solution that has the function of etching the surface of the ceramic element to ionize constituent elements of the ceramic element. The resin composition includes a resin, and cationic elements among the constituent elements of the ceramic elements, which are ionized and deposited from the ceramic element.

Abstract: A conductive resin layer includes a first region positioned on the end surface, a second region positioned on the side surface, and a third region positioned on a ridge portion between the end surface and the side surface. In a case where a maximum thickness of the first region is T1 (?m) and a maximum thickness of the second region is T2 (?m), the maximum thickness T1 and the maximum thickness T2 satisfy a relation of T2/T1?0.11. In a cross-section along a thickness direction of the first region, a total area of voids in the first region is in a range of 5.0 to 36.0% of an area of the first region. In a cross-section along a thickness direction of the second region, a total area of voids in the second region is in the range of 5.0 to 36.0% of an area of the second region.

Abstract: A chip antenna includes a first substrate, a second substrate overlapping the first substrate, a first patch, provided on a first surface of the first substrate, operating as a feed patch, a second patch, provided on the second substrate, operating as a radiation patch, at least one feed via penetrating through the first substrate in a thickness direction and configured to provide a feed signal to the first patch, and a ground pad provided on the other surface of the first substrate. The first substrate comprises a ceramic sintered material. The ceramic sintered material comprises an Mg2SiO4 phase, an MgAl2O4 phase, and a CaTiO3 phase, and a content of the CaTiO3 phase in the ceramic sintered material ranges from 5.1 mol % to 15.1 mol %.

Abstract: A wiring structure is provided, including a conductive wiring and an insulating layer. The conductive wiring is disposed on a substrate and has a top side, a bottom side and two side walls opposite to each other. The insulating layer which wraps around the conductive wiring at least through the top side and two side walls, wherein there is a gap between the insulating layer and at least one of the two side walls.

Abstract: Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.

Abstract: A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.

Abstract: An electronic component includes an element body and an external electrode. The element body includes a side surface and an end surface. The external electrode includes a conductive resin layer disposed over the side surface and the end surface. The conductive resin layer includes a first region positioned on the end surface, a second region positioned on the side surface, and a third region positioned on a ridge portion between the end surface and the side surface. In a case where a maximum thickness of the first region is T1 (?m), a maximum thickness of the second region is T2 (?m), and a minimum thickness of the third region is T3 (?m), the maximum thickness T1 and the maximum thickness T2 satisfy a relation of T2/T1?0.11, and the maximum thickness T1 and the minimum thickness T3 satisfy a relation of T3/T1?0.11.

Abstract: A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

Abstract: The present disclosure relates to a display device, a liquid crystal display panel and a driving method for a liquid crystal display panel. The liquid crystal display panel includes: an array substrate including a plurality of sub-pixels having active display areas, each of the sub-pixels including a plurality of first electrodes, and a first slit being disposed between adjacent first electrodes; an opposite substrate facing the array substrate, wherein a first surface of the opposite substrate facing the array substrate includes at least a target area facing an edge area of the active display area; and a control electrode disposed in the target area and opposite to the first electrode, for generating an electric field in a target direction with the first electrode, so as to control liquid crystals between an edge area of the array substrate and the target area of the opposite substrate to be deflected.

Abstract: A multilayer ceramic electronic component includes a rectangular parallelepiped laminate body. An external electrode is provided at both end surfaces of the laminate body. The external electrode includes a base electrode layer, a conductive resin layer on the base electrode layer, and a plating layer on the conductive resin layer. The conductive resin layer includes a first layer on the base electrode layer, a second layer on the first layer, and a third layer on the second layer. With respect to porosity which is an area ratio of pores obtained from a binary image within a predetermined field of view, the first layer and the third layer have a porosity of equal to or less than about 5% and the second layer has a porosity equal to or more than about 6%. Thicknesses of the first, second, and third layers satisfy predetermined conditions.

Abstract: A vehicle such as an unmanned aerial vehicle (UAV) can include a heat-generating electronic device coupled with a heat exhaust element by a vibration isolating thermal connector. The thermal connector includes a first heat-conducting element configured to draw heat from the electronic device, a second heat-conducting element separated from the first heat-conducting element, and a flexible seal connected with the first and second heat-conducting elements and defining an enclosed cavity between the elements. The enclosed cavity contains a heat conducting liquid, and allows limited movement of the first and second heat conducting elements with respect to each other while maintaining thermal connection.

Abstract: An encapsulation for electronics is provided. The encapsulation includes a circuit card assembly (CCA) on which a component of the electronics is operably disposed, a compliant thermal buffer coating (TBC), thermoset material and high-performance thermoplastic materials. The compliant TBC is layered over the component and a first area of the CCA, which extends about a periphery of the component. The thermoset material is cast over the compliant TBC and a second area of the CCA, which extends about a periphery of the compliant TBC. The high-performance thermoplastic material is injection molded over the thermoset material and a third area of the CCA, which extends about a periphery of the thermoset material.

Abstract: A metal paste is suppled into a through hole of a ceramic substrate and heated to generate a metal porous body. A glass paste is applied on a main surface of the metal porous body while the glass paste is impregnated into open pores of the metal porous body. The glass paste is hardened by heating to form a glass layer on the main surface of the metal porous body and to make the glass paste impregnated into the open pores form glass phases. The glass layer is removed to obtain a connection substrate having a ceramic substrate and through conductors provided in through holes, respectively. The through conductor includes the metal porous body and glass phases.

Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher.

Abstract: Provided is an electronic assembly including (a) an interconnect carrier having an electrically insulating core and at least two electrically conducting layers formed at the electrically insulating core; (b) a first integrated circuit chip mounted at a first side of the interconnect carrier; (c) a second integrated circuit chip mounted at a second side of the interconnect carrier opposite to the first side; and (d) an interconnection structure electrically connecting the first integrated circuit chip with the second integrated circuit chip. The electric interconnection structure extends around the insulating core and includes at least one electric conductor path which is designed in such a manner that an impedance match between the first integrated circuit chip and the second integrated circuit chip is provided. Further, there is provided an electronic system comprising such an electronic assembly.

Abstract: Various implementations include a vehicle occupant imaging system that is disposed within a vehicle. The system includes an automotive clock spring, at least one imaging unit, and a first processing unit. The automotive clock spring includes a rotor to which a rotatable portion of the steering wheel assembly is coupled, a stator coupled to a stationary portion of the vehicle, and a set of wires extending between the rotor and stator. The imaging unit is coupled to the rotatable portion of the steering wheel assembly. The first processing unit is disposed within the rotor and is configured for electrically receiving image signals captured by the imaging unit and selecting at least a portion of the image signals for communicating to a second processing unit disposed outside of the rotor. The selected image signals are electrically communicated to the second processing unit via the set of electrical wires.

Abstract: The present invention provides a low-dielectric resin composition comprising (A) a urethane resin obtained by reacting a polycarbonate diol and an isocyanate, (B) an epoxy resin, and (C) a filler, wherein the (A) urethane resin has a carboxyl group equivalent weight of 1,100 to 5,700 g/eq; the epoxy equivalent weight of the (B) epoxy resin is 0.3 to 4.5 equivalents per 1.0 equivalent of the carboxyl group of the (A) urethane resin, the (A) urethane resin has a weight-average molecular weight of 5,000 to 80,000; the (A) urethane resin has a polycarbonate content of 35% by mass or lower; the resin composition comprises 50 parts by mass or less of the (C) filler per 100 parts by mass of the (A) urethane resin; and the resin composition comprises substantially no imido group.

Abstract: Embodiments are generally directed to indium solder metallurgy to control electro-migration. An embodiment of an electronic device includes a die; and a package substrate, wherein the die is bonded to the package substrate by an interconnection. The interconnection includes multiple interconnects, and wherein the interconnection includes a solder. The solder for the interconnection includes a combination of tin (Sn), copper (Cu), and indium (In).

Abstract: An electronic module includes a carrier element and a circuit board. The circuit board is attached in and/or to the carrier element via at least one connection site. The at least one connection site is formed by means of a hardenable medium.

Abstract: A method for applying a metal on a substrate comprises: a) applying a coating by treatment in a plasma, comprising a compound selected from alkanes up to 10 carbon atoms, and unsaturated monomers, and b1) producing polymers on the surface of the substrate, the polymers comprising carboxylic groups and adsorbed ions of a second metal, reducing the ions to the second metal, or alternatively b2) producing polymers on the surface, bringing the surface of the substrate in contact with a dispersion of colloidal metal particles of at least one second metal, and c) depositing the first metal on the second metal. Advantages include that materials sensitive to, for instance, low pH or solvents can be coated. Substrates including glass, SiO2 with very few or no abstractable hydrogen atoms as well as polymer materials containing halogen atoms can be coated with good adhesion.

Abstract: A heat dissipation substrate is disclosed including a base substrate having a first surface and a second surface, an electrically conductive path formed on the first surface, a through-hole penetrating from the first surface to the second surface, a heat dissipation member that is inserted into the through-hole and at least a part of which projects from the first surface, a thermally conductive resin constituent, covering a side surface of the heat dissipation member, that is present, without space, between an inner peripheral surface of the through-hole and an outer peripheral surface of the heat dissipation member surrounded by the inner peripheral surface, and a metal layer covering the heat dissipation member projecting from the first surface, in which an outer surface of the metal layer and an outer surface of the electrically conductive path are disposed on substantially the same plane.

Abstract: A coil electronic component includes a coil including upper and lower coils and a via electrically connecting the upper and lower coils to each other. The via is formed along at least a portion of a boundary surface of a through-hole penetrating upper and lower surfaces of a support member supporting the upper and lower coils.

Abstract: A device for mounting a semiconductor element includes a metal plate serving as a base, a roughened silver plating layer with acicular projections, formed on at least either of: (a) top faces; and (b) faces that form concavities or through holes between the top faces and bottom faces; of the metal plate, and a reinforcing plating layer covering, as an outermost plating layer, an outer surface of the acicular projections in the roughened silver plating layer. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. An outer surface of the reinforcing plating layer is shaped to have acicular projections with a surface area ratio of 1.30 or more and 6.00 or less to the corresponding smooth surface, as inheriting the shape of the acicular projections in the roughened silver plating layer.

Abstract: A flexible printed wiring board includes a flexible insulating layer, a conductor layer formed on a surface of the flexible insulating layer, and a metal body having a columnar shape and fitted in a hole penetrating through the flexible insulating layer and the conductor layer such that the metal body is formed of a welding base material and has an end portion formed to be joined to an electrode of a battery by welding. The welding base material of the metal body of the flexible printed wiring board includes the same material as the electrode of the battery.

Abstract: A wiring board includes: an insulating layer that includes a first surface over which an electronic component is mounted and a second surface opposite to the first surface; a conductive layer that is disposed on the second surface; a via that is provided inside a first through-hole that penetrates a portion between the first surface and the second surface of the insulating layer; an electrode that is disposed on the first surface and connected to the via; and a glass plate that is not contact with the conductive layer and is disposed on the first surface and includes a second through-hole through which the electrode is disposed.

Abstract: A semiconductor package manufacturing method includes preparing a flexible film including input wire patterns and output wire patterns, preparing a semiconductor chip including metal bumps, attaching the semiconductor chip to one side of the flexible film, such that the metal bumps are connected to either one or both of the input wire patterns and the output wire patterns, and attaching a first absorbing and shielding tape to another side of the flexible film, wherein the first absorbing and shielding tape includes an absorption film and a protective insulating film disposed on the absorption film.

Abstract: A wiring board includes: an insulating layer that includes a first surface over which an electronic component is mounted and a second surface opposite to the first surface; a conductive layer that is disposed on the second surface; a via that is provided inside a first through-hole that penetrates a portion between the first surface and the second surface of the insulating layer; an electrode that is disposed on the first surface and connected to the via; and a glass plate that is not contact with the conductive layer and is disposed on the first surface and includes a second through-hole through which the electrode is disposed.

Abstract: Method of manufacturing laminate body by: curing thermosetting resin composition on a support; laminating the curable resin onto a substrate; heating the laminate; forming a via hole in the cured resin layer; peeling the supporting body from the cured composite; performing a second heating of the cured composite; removing resin residue in the via hole of the cured composite; and forming a conductor layer on an inner wall surface of the via hole.

Abstract: A printed circuit board includes: a core member including a through-hole; a sub-circuit board disposed in the through-hole; a first insulating layer disposed on opposing surfaces of the core member and opposing surfaces of the sub-circuit board; and an insulating material disposed between an inner wall of the through-hole and the sub-circuit board.

Abstract: An implantable device is provided. The implantable device includes a flexible polymeric substrate that extends through an aperture in an electrically conductive material to form an anchor that partially covers the electrically conductive material. Methods for fabricating the implantable device are also provided.

Abstract: A shielding film comprises multiple layers including one or more of a structured adhesive layer, an electrically conductive layer, an electrically insulative thermally conductive layer, and an electrically conductive adhesive layer. The electrically conductive shielding layer extends laterally beyond the structured adhesive layer. The electrically insulative thermally conductive layer is disposed between the electrically conductive shielding layer and the structured adhesive layer and is coextensive with the structured adhesive layer. The electrically conductive adhesive layer is disposed between the electrically conductive shielding layer and the thermally conductive layer and is coextensive with the electrically conductive shielding layer.

Abstract: Various implementations include a vehicle occupant imaging system that is disposed within a vehicle. The system includes an automotive clock spring, at least one imaging unit, and a first processing unit. The automotive clock spring includes a rotor to which a rotatable portion of the steering wheel assembly is coupled, a stator coupled to a stationary portion of the vehicle, and a set of wires extending between the rotor and stator. The imaging unit is coupled to the rotatable portion of the steering wheel assembly. The first processing unit is disposed within the rotor and is configured for electrically receiving image signals captured by the imaging unit and selecting at least a portion of the image signals for communicating to a second processing unit disposed outside of the rotor. The selected image signals are electrically communicated to the second processing unit via the set of electrical wires.

Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.

Abstract: A multilayer printed wiring board has excellent high-frequency characteristics. The multilayer printed wiring board includes one or more conductive layers and one or more insulating layers. In the multilayer printed wiring board, the one or more conductive layers and the one or more insulating layers are alternately stacked. Each insulating layer of the one or more insulating layers includes one or more of a polyolefin resin layer, a fluororesin layer, a polyphenylene ether resin layer, a polyamideimide resin layer, and a polyimide resin layer. At least one insulating layer of the one or more insulating layers includes a polyolefin resin layer.

Abstract: A method for manufacturing a feedthrough dielectric body for an active implantable medical device includes the steps of first forming a ceramic reinforced metal composite (CRMC) paste by mixing platinum with a ceramic material to form a CRMC material, subjecting the CRMC material to a first sintering step to thereby form a sintered CRMC material, ball-milling or grinding the sintered CRMC material to form a powdered CRMC material; and then mixing the powdered CRMC material with a solvent to form the CRMC paste.

Abstract: A method for manufacturing a flexible circuit board with resistor which is buried in the board includes steps of providing a composite board, the composite board comprising a substrate, and a physical development core layer formed on the substrate. A silver halide emulsion layer is formed on the physical development core layer and the silver halide emulsion layer is exposed. A developing solution is applied to the halide emulsion layer and washed to form a silver layer on the substrate. A conductive layer is formed on the silver layer and the conductive layer is etched, forming at least one opening. Such opening exposes a portion of the silver layer which contains a buried resistor. Different processes and materials applied in the above procedure serve to increase or decrease the resistance of the resistor as desired.

Abstract: A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.

Abstract: A number of variations may include a method that may include providing a glass substrate that may include a first surface and a second surface; disposing a ceramic frit that may include at least one bus bar and at least one grid line on the first surface to form a window assembly; bathing the window assembly in a first bath solution; and drying the window assembly.

Abstract: The present invention provides a titanium copper foil having improved adhesion to solder and higher resistance to discoloration due to a high temperature and high humidity environment, an acid solution or an alkaline solution, and as well as having improved etching processability. The present invention provides a titanium copper foil comprising a base metal, the base metal having a composition containing Ti of from 1.5 to 5.0% by mass, the balance being copper and inevitable impurities, and having a thickness of from 0.018 to 0.1 mm, wherein the titanium copper foil has an Sn plated layer on a surface of the base metal, and has an adhesive strength of 0.5 N or more as measured by a solder adhesive strength test according to the definition in the specification.

Abstract: An electronic component device includes: a wiring board including an insulating layer, and a plurality of pads exposed from the insulating layer; an electronic component module including: an insulating base material; an electronic component embedded in the insulating base material; and a plurality of connection terminals each connected to a corresponding one of the pads; and a sealing resin provided between the whole of a lower surface of the electronic component module id the wiring board. A content rate of filler contained in the sealing resin is higher than that of filler contained in the insulating layer and that of filler contained in the insulating base material.

Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.

Abstract: Encapsulated conformal electronic devices, encapsulated conformal integrated circuit (IC) systems, and methods of making and using encapsulated conformal electronic devices are presented herein. A conformal IC device is disclosed which includes a flexible substrate, electronic circuitry attached to the flexible substrate, and a flexible multi-part encapsulation housing encasing therein the electronic circuitry and flexible substrate. The multi-part housing includes first and second encapsulation housing components. The first encapsulation housing component has recessed regions for seating therein the electronic circuitry, while the second encapsulation housing component has recessed regions for seating therein the flexible substrate. First encapsulation housing component optionally includes a recessed region for seating therein the flexible substrate.

Abstract: A micro-pad array to conductive wire flexible attachment assembly includes a micro-pad geometry formed on a flexible printed circuit and a method for connecting a conductive wire, thread or fiber to the micro-pad geometry.

Abstract: Systems and methods are provided to produce electromechanical interconnections within integrated circuits (ICs), printed circuit boards (PCBs) and between PCBs and other electronic components such as resistors, capacitors and integrated circuits. Elements include so-called “smart pins” or “neuro-pins” that facilitate electrical pathways in the dimension normal to the plane of a PCB. Smart pins or neuro-pins may be inserted using automated processes that do not require the high temperatures normally associated with soldering. Resultant circuits generally contain a large number of layers that are more compact and more readily constructed compared with conventional PCB-based circuitry.