Abstract: A data communication system employing predetermined equalized waveforms for transmit equalization is disclosed. Serial NRZ data is received from a network controller and utilized to select from memory its equivalent as predistorted and filtered Manchester encoded data. Predetermined waveforms in memory are representative of the analog waveform produced when predistorted digital Manchester encoded data is passed through a high order transmit filter. Data from memory drives a digital to analog converter (DAC) to reconstruct the waveforms into analog form. A line driver having an integrated single pole low pass filter impresses the equalized waveform on to the transmission line.

Abstract: A digital data transmission system includes a transmitter connected to a receiver by a twisted pair. A digital transversal filter, included in the transmitter, supplies output signals to one of four resistor banks, as determined by an automatic selection system that selects one of the resistor banks based on the measured transmission characteristics of the twisted pair. The output signals are weighted by the resistors of the selected resistor bank, summed, and used to generate the transmitted pulse. The values of the resistors of each resistor bank are chosen to shape the transmitted pulse for a respective length of transmission medium so that, after distortion by the transmission medium, the transmitted pulse more nearly corresponds to the ideal pulse shape for which the receiver is designed.

Abstract: A circuit for detecting and verifying a presence of a terminating device for a high speed data transmission line. The circuit contains a first cable detector which generates a first signal if a first cable is present. A second cable detector generates a second signal if a second cable is present. The terminating device is contained in a plurality of resistor packs, each of the which contains an extra resistor. A terminating device detector senses the extra resistor presence, thereby detecting the presence of the resistor packs. The terminating device detector generates an ALL-EQUIPPED signal and a NON-EQUIPPED signal, the ALL-EQUIPPED signal is generated when all of the plurality of resistor packs are present, the NON-EQUIPPED signal is generated when all of the plurality of resistor packs are absent. Finally, a verifier circuit receives the first signal, the second signal, the ALL-EQUIPPED signal and the NON-EQUIPPED signal.

Abstract: A post-equalizer and pre-equalizer circuit for use in communicating between nodes in a pulse amplitude modulated digital communication system is described. The post-equalizer circuit comprises a first variable zero circuit, a second variable circuit, and a gain shaper circuit wherein the gain and frequency location of the zeros in the zero circuits combined with the gain of the gain shaping circuit are simultaneously controlled by a control circuit which generates a control voltage which is a monotonically increasing function of cable loss. The control voltage generates a signal equal to the difference between the equalized signal and the original transmitted signal which is used to vary the resistance of voltage variable resistors in the form of FET's in each of the zero circuits and gain shaper circuits.

Abstract: In a digital signal transmission apparatus for transmitting a digital signal through a transmission system of the type which inherently generates nonlinear distortions, the present invention, by means of digital circuits on the transmitting side, allows approximation to a linear transmission system by adding to the signal to be transmitted, compensating distortions, which are formed according to run-lengths of the digital signal and which will cancel the distortions to be produced in the transmission system. The compensating distortion which is added advances the phase of the input digital signal transitions from one logical level to another, succeeding logical level.

Abstract: A post-equalizer and pre-equalizer circuit for use in communicating between nodes in a Pulse Amplitude Modulated (PAM) digital or analog communication system is described. The post-equalizer circuit comprises a first variable zero circuit, a second variable zero circuit, and a gain shaper circuit wherein the gain and frequency location of the zeros in the zero circuits combined with the gain of the gain shaping circuit are simultaneously controlled by a control circuit which generates a control voltage which is a monotonically increasing function of cable loss. In the case of a PAM digital communication system, the control voltage generates a signal equal to the difference between the equalized signal and the original transmitted signal which is used to vary the resistance of voltage variable resistors in the form of FET's in each of the zero circuits and gain shaper circuits.