Semiconductor Patents (Class 204/192.25)
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Patent number: 8198179Abstract: A method for producing a group III nitride semiconductor light-emitting device including: an intermediate layer formation step in which an intermediate layer containing group III nitride is formed on a substrate by sputtering, and a laminate semiconductor formation step in which an n-type semiconductor layer having a base layer, a light-emitting layer, and a p-type semiconductor layer are laminated on the intermediate layer in this order, wherein the method includes a pretreatment step in which the intermediate layer is treated using plasma between the intermediate layer formation step and the laminate semiconductor formation step, and a formation step for the base layer which is included in the laminate semiconductor formation step is a step for laminating the base layer by sputtering.Type: GrantFiled: February 7, 2008Date of Patent: June 12, 2012Assignee: Showa Denko K.K.Inventors: Yasumasa Sasaki, Hisayuki Miki
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Publication number: 20120138453Abstract: A silicon target for sputtering film formation which enables formation of a high-quality silicon-containing thin film by inhibiting dust generation during sputtering film formation is provided. An n-type silicon target material 10 and a metallic backing plate 20 are attached to each other via a bonding layer 40. A conductive layer 30 made of a material having a smaller work function than that of the silicon target material 10 is provided on a surface of the silicon target material 10 on the bonding layer 40 side. That is, the silicon target material 10 is attached to the metallic backing plate 20 via the conductive layer 30 and the bonding layer 40. In a case of single-crystal silicon, a work function of n-type silicon is generally 4.05 eV. A work function of a material of the conductive layer 30 needs to be smaller than 4.05 eV.Type: ApplicationFiled: November 22, 2011Publication date: June 7, 2012Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Hiroki YOSHIKAWA, Yokio Inazuki, Hideo Kaneko
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Publication number: 20120118726Abstract: A sputtering target including an oxide sintered body which includes In, Ga and Zn and includes a structure having a larger In content than that in surrounding structures and a structure having larger Ga and Zn contents than those in surrounding structures.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: IDEMITSU KOSAN CO., LTC.Inventors: Koki Yano, Masayuki Itose
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Publication number: 20120080090Abstract: Certain example embodiments relate to a transparent conductor film stack with cadmium stannate used as a front contact layer and/or a buffer layer in a photovoltaic device or the like. The cadmium stannate-based layers may be provided between the front glass substrate and the semiconductor absorber film in a photovoltaic device (e.g., a CdS and/or CdTe based photovoltaic device). In certain example embodiments, the buffer layer based on cadmium stannate may have a higher resistivity than the transparent conductive oxide layer based on cadmium stannate. In certain example embodiments, one or more index matching layer(s) may be provided between the glass substrate and the layer(s) comprising cadmium stannate, e.g., to help overcome the optical mismatch between the glass substrate and the CdSnOx.Type: ApplicationFiled: October 1, 2010Publication date: April 5, 2012Applicant: Guardian Industries Corp.Inventors: Scott V. Thomsen, Willem den Boer, Yiwei Lu
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Publication number: 20120060750Abstract: An oxide semiconductor film with excellent crystallinity is formed. At the time when an oxide semiconductor film is formed, as a substrate is heated to a temperature of higher than or equal to a first temperature and lower than a second temperature, a part of the substrate having a typical length of 1 nm to 1 ?m is heated to a temperature higher than or equal to the second temperature. Here, the first temperature means a temperature at which crystallization occurs with some stimulation, and the second temperature means a temperature at which crystallization occurs spontaneously without any stimulation. Further, the typical length is defined as the square root of a value obtained in such a manner that the area of the part is divided by the circular constant.Type: ApplicationFiled: August 30, 2011Publication date: March 15, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Shunpei YAMAZAKI
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Patent number: 8133364Abstract: The present application discloses a method and system of depositing a lead selenide film onto another material. The lead selenide film may used in a photoconductive application or a photovoltaic application. Furthermore, the applications may be responsive to infrared radiation at ambient temperature. In one embodiment, a method includes sputtering the lead selenide film, performing a sensitization process, and applying a passivation film. In one exemplary embodiment, a p-n junction is formed by directly adhering a lead selenide film to a silicon substrate.Type: GrantFiled: November 6, 2008Date of Patent: March 13, 2012Assignee: Advanced Integration, Inc.Inventor: George Engle
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Publication number: 20120049183Abstract: A film formation is performed using a target in which a material which is volatilized more easily than gallium when heated at 400° C. to 700° C., such as zinc, is added to gallium oxide by a sputtering method with high mass-productivity which can be applied to a large-area substrate, such as a DC sputtering method or a pulsed DC sputtering method. This film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film. Another portion of the film has a decreased concentration of the added material and a sufficiently high insulating property; therefore, it can be used for a gate insulator of a semiconductor device, or the like.Type: ApplicationFiled: August 17, 2011Publication date: March 1, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Shunpei YAMAZAKI
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Publication number: 20120048726Abstract: A sputtering cathode is generally provided. The sputtering cathode can include a semiconducting target (e.g., a cadmium sulfide target, a cadmium tin oxide target, etc.) defining a sputtering surface and a back surface opposite to the sputtering surface. A backing plate can be positioned facing the back surface of the target and non-bonded to the back surface of the target. A non-bonding attachment mechanism can removably hold the target within the sputtering cathode such that the back surface is facing the backing plate during sputtering.Type: ApplicationFiled: September 28, 2010Publication date: March 1, 2012Applicant: PRIMESTAR SOLAR, INC.Inventors: Russell Weldon Black, Robert Dwayne Gossman, Patrick Lynch O'Keefe, Scott Daniel Feldman-Peabody
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Publication number: 20120043658Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.Type: ApplicationFiled: August 20, 2010Publication date: February 23, 2012Inventors: Dale W. Collins, Joe Lindgren
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Publication number: 20120024366Abstract: A thin film solar cell structure and the fabricating method thereof are disclosed. A passivation layer is embedded into the thin film solar cell structure to be in contact with an absorbing layer. The interface trap density of the absorbing layer is reduced by the surface electric field of the passivation layer. The invention helps improve the power conversion efficiency and protect the absorbing layer.Type: ApplicationFiled: October 26, 2010Publication date: February 2, 2012Applicant: NATIONAL TAIWAN UNIVERSITYInventors: Chee Wee Liu, Wen Wei Hsu, Tzu Huan Cheng, Wei Shuo Ho
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Publication number: 20120025148Abstract: A technique capable of forming an oxide semiconductor target with a high quality in a low cost is provided. In a step of manufacturing zinc tin oxide (ZTO target) used in manufacturing an oxide semiconductor forming a channel layer of a thin-film transistor, by purposely adding the group IV element (C, Si, or Ge) or the group V element (N, P, or As) to a raw material, excessive carriers caused by the group III element (Al) mixed in the step of manufacturing the ZTO target are suppressed, and a thin-film transistor having good current (Id)-voltage (Vg) characteristics is achieved.Type: ApplicationFiled: March 16, 2011Publication date: February 2, 2012Inventors: Hiroyuki Uchiyama, Hironori Wakana
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Publication number: 20120003836Abstract: A movable ground ring of a movable substrate support assembly is described. The movable ground ring is configured to fit around and provide an RF return path to a fixed ground ring of the movable substrate support assembly in an adjustable gap capacitively-coupled plasma processing chamber wherein a semiconductor substrate supported in the substrate support assembly undergoes plasma processing.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: Lam Research CorporationInventors: Michael C. Kellogg, Alexei Marakhtanov, Rajinder Dhindsa
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Publication number: 20110306165Abstract: There is provided a method for producing an a-IGZO oxide thin film by sputtering, which can control the carrier density of the film to a given value with high reproducibility. The method is an amorphous In—Ga—Zn—O based oxide thin film production method including: providing a sintered oxide material consisting essentially of indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as constituent elements, wherein the ratio [In]/([In]+[Ga]) of the number of indium atoms to the total number of indium and gallium atoms is from 20% to 80%, the ratio [Zn]/([In]+[Ga]+[Zn]) of the number of zinc atoms to the total number of indium, gallium and zinc atoms is from 10% to 50%, and the sintered oxide material has a specific resistance of 1.0×10?1 ?cm or less; and producing a film on a substrate by direct current sputtering at a sputtering power density of 2.5 to 5.5 W/cm2 using the sintered oxide material as a sputtering target.Type: ApplicationFiled: December 24, 2008Publication date: December 15, 2011Applicant: NIPPON MINING & METALS CO., LTD.Inventors: Masakatsu Ikisawa, Masataka Yahagi
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Patent number: 8062777Abstract: This invention provides a transparent oxide semiconductor, which comprises an oxide comprising indium oxide as a main component and cerium oxide as an additive and has such properties that light-derived malfunction does not occur, there is no variation in specific resistance of a thin film caused by heating and the like, and the mobility is high, and a process for producing the same. A semiconductor thin film characterized by comprising indium oxide and cerium oxide and being crystalline and having a specific resistance of 10+1 to 10+8 ?cm is used. This semiconductor thin film has no significant change in specific resistance and has high mobility. Accordingly, an element having improved switching properties can be provided by constructing a switching element using this semiconductor thin film.Type: GrantFiled: August 7, 2006Date of Patent: November 22, 2011Assignee: Idemitsu Kosan, Co., Ltd.Inventors: Kazuyoshi Inoue, Koki Yano, Nobuo Tanaka, Tokie Tanaka, legal representative
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Publication number: 20110278510Abstract: The tin-doped indium oxide thin film in accordance with the present invention has a tin-doped indium oxide, yttrium ions and europium ions, wherein the yttrium ions are proportional to 0.1-10 mol % of the tin-doped indium oxide while the europium ions proportional to 0.05-5 mol % of the tin-doped indium oxide. The method in accordance with the present invention comprises preparing a tin-doped indium oxide; and doping yttrium ions proportional to 0.1-10 mol % of the tin-doped indium and europium ions proportional to 0.05-5 mol % of the tin-doped indium oxide in the tin-doped indium oxide using a film-manufacturing method.Type: ApplicationFiled: May 12, 2010Publication date: November 17, 2011Applicant: National Chung Chen UniversityInventors: Chu-Chi Ting, Chia-Hao Tsai, Hsiang-Chen Wang
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Publication number: 20110256673Abstract: An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaOX). The oxide target includes GaOX, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.Type: ApplicationFiled: April 13, 2011Publication date: October 20, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Junichiro Sakata, Makoto Furuno
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Patent number: 8039400Abstract: A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.Type: GrantFiled: April 6, 2009Date of Patent: October 18, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank Koschinsky, Matthias Lehr, Holger Schuehrer
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Publication number: 20110240462Abstract: An object of one embodiment of the present invention is to provide a deposition apparatus for depositing an oxide semiconductor film into which impurities are not mixed. Another object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor film into which impurities are not mixed. Impurities are removed from an environment including a deposition apparatus, whereby a gas containing impurities may be prevented from leaking from the outside of the deposition apparatus to the inside thereof. In addition, an oxide semiconductor layer containing reduced impurities which is deposited by the apparatus may be applied to the semiconductor device.Type: ApplicationFiled: March 31, 2011Publication date: October 6, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Shunpei Yamazaki
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Patent number: 8029853Abstract: The inventive fabrication process for magnetoresistive devices (CPP-GMR devices) involves the formation of a zinc oxide or ZnO layer that provides the intermediate layer of a spacer layer, comprising Zn film formation operation for forming a zinc or Zn layer and Zn film oxidization operation for oxidizing the zinc film after the Zn film formation operation. The Zn film formation operation is implemented such that after a multilayer substrate having a multilayer structure before the formation of the Zn film is cooled down to the temperature range of ?140° C. to ?60° C., the formation of the Zn film is set off, and the Zn film oxidization operation is implemented such that after the completion of the Zn film oxidization operation, oxidization treatment is set off at the substrate temperature range of ?120° C. to ?40° C. Thus, excelling in both flatness and crystallizability, the ZnO layer makes sure the device has high MR ratios, and can further have an area resistivity AR best suited for the device.Type: GrantFiled: November 20, 2008Date of Patent: October 4, 2011Assignee: TDK CorporationInventors: Hironobu Matsuzawa, Tsutomu Chou, Yoshihiro Tsuchiya, Shinji Hara
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Patent number: 8012315Abstract: A method of fabricating by co-sputtering deposition a lanthanoid aluminate film with enhanced electrical insulativity owing to suppression of deviation in composition of the film is disclosed. Firstly within a vacuum chamber, hold two separate targets, one of which is made of lanthanoid aluminate (LnAlO3) and the other of which is made of aluminum oxide (Al2O3). Then, transport and load a substrate into the vacuum chamber. Next, introduce a chosen sputtering gas into this chamber. Thereafter, perform sputtering of both the targets at a time to thereby form a lanthanoid aluminate film on the substrate surface. This film is well adaptable for use as ultra-thin high dielectric constant (high-k) gate dielectrics in highly miniaturized metal oxide semiconductor (MOS) transistors.Type: GrantFiled: December 28, 2007Date of Patent: September 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Akira Takashima
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Patent number: 8012316Abstract: A method of forming a CPP-GMR spin valve having a pinned layer with an AP2/coupling/AP1 configuration is disclosed wherein the AP2 portion is a FCC-like trilayer having a composition represented by CoZFe(100-Z)/Fe(100-X)TaX/CoZFe(100-Z) or CoZFe(100-Z)/FeYCo(100-Y)/CoZFe(100-Z) where x is 3 to 30 atomic %, y is 40 to 100 atomic %, and z is 75 to 100 atomic %. Preferably, z is 90 to provide a face centered cubic structure that minimizes electromigration. Optionally, the middle layer is comprised of an Fe rich alloy such as FeCr, FeV, FeW, FeZr, FeNb, FeHf, or FeMo. EM performance is improved significantly compared to a spin valve with a conventional AP2 Co50Fe50 or Co75Fe25 single layer. MR ratio is also increased and RA is maintained at an acceptable level. The coupling layer is preferably Ru and the AP1 layer may be comprised of a lamination of CoFe and Cu layers as in [CoFe/Cu]2/CoFe.Type: GrantFiled: August 25, 2009Date of Patent: September 6, 2011Assignee: Headway Technologies, Inc.Inventors: Kunliang Zhang, Dan Abels, Min Li, Chyu-Jiuh Torng, Chen-Jung Chien, Yu-Hsia Chen
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Publication number: 20110212268Abstract: Embodiments of the present invention relate to apparatuses and methods for fabricating electrochemical cells. One embodiment of the present invention comprises a single chamber configurable to deposit different materials on a substrate spooled between two reels. In one embodiment, the substrate is moved in the same direction around the reels, with conditions within the chamber periodically changed to result in the continuous build-up of deposited material over time. Another embodiment employs alternating a direction of movement of the substrate around the reels, with conditions in the chamber differing with each change in direction to result in the sequential build-up of deposited material over time. The chamber is equipped with different sources of energy and materials to allow the deposition of the different layers of the electrochemical cell.Type: ApplicationFiled: May 6, 2011Publication date: September 1, 2011Applicant: Sakti3, Inc.Inventors: Fabio Albano, Chia-Wei Wang, Ann Marie Sastry
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Publication number: 20110203916Abstract: A magnetron-sputtering film-forming apparatus includes: a vacuum film-forming chamber (11); electrostatic chuck units (12) for adjusting a temperature of the substrate (14); a target (15) for causing high-frequency magnetron sputtering; power supply units (17) for applying a discharge voltage between the substrate (14) and the target (15), and calculating an integral power consumption of an electricity discharged by the target (15); and control units (18) for controlling the electrostatic chuck units (12) and the power supply units (17). In the magnetron-sputtering film-forming apparatus, the temperature of the substrate to be processed (14) that is most suitable for sputtering is calculated based on the integral power consumption of the electricity discharged by the target (15) until that time, and the substrate (14) is adjusted to have a predetermined temperature to be subjected to the sputtering.Type: ApplicationFiled: May 4, 2011Publication date: August 25, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Wensheng Wang
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Publication number: 20110198213Abstract: [Object] To provide a sputtering apparatus, a thin-film forming method, and a manufacturing method for a field effect transistor, which are capable of reducing damage of a base layer. [Solving Means] The sputtering apparatus according to the present invention sputters target portions Tc1 to Tc5, which are arranged in an inside of a vacuum chamber, along the arrangement direction thereof in sequence, to thereby form a thin-film on a surface of a substrate 10. With this, rate at which sputtered particles enter the surface of the substrate in a direction oblique to the surface of the substrate is increased, and hence it is possible to achieve a reduction of the damage of the base layer.Type: ApplicationFiled: October 9, 2009Publication date: August 18, 2011Applicant: ULVAC, INC.Inventors: Takaomi Kurata, Junya Kiyota, Makoto Arai, Yasuhiko Akamatsu, Satoru Ishibashi, Kazuya Saito
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Publication number: 20110198212Abstract: A sputtering apparatus (1) includes: a chamber (10) having an inside maintained in a depressurized state to generate plasma discharge (20); a cathode (22) placed in the chamber (10) and holding a target (21); and a substrate holder (60) holding a substrate (110) so that one surface of the substrate (110) faces the surface of the target (21). The substrate (110) is arranged at an upper portion in the sputtering apparatus (1) with the surface of the substrate (110) facing downward. The target (21) is arranged at a lower portion in the sputtering apparatus (1) with the surface of the target (21) facing upward. The sputtering apparatus (1) includes a heater (65) for heating the substrate (110). The temperature of the substrate (110) is raised by absorbing electromagnetic waves radiated from the heater (65). A method of manufacturing a semiconductor light-emitting element using the sputtering apparatus is also disclosed.Type: ApplicationFiled: January 10, 2011Publication date: August 18, 2011Applicant: SHOWA DENKO K.K.Inventors: Hisayuki MIKI, Kenzo Hanawa, Yasunori Yokoyama, Yasumasa Sasaki
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Patent number: 7998319Abstract: A process is provided for the formation of miniaturized getter deposits, comprising the steps of forming a layer of a photosensitive polymeric material on a support; selectively exposing the polymeric layer in order to cause a chemical modification in a portion of the polymeric layer; removing with a first solvent only one of the previously exposed or the not previously exposed portions of the polymeric layer, thus forming cavities in the polymeric layer; forming a thin layer of a getter material by cathodic deposition at the bottom of the cavity and on the residual polymer; and removing with a second solvent the polymer portion not removed by the first solvent, leaving at least a getter material deposit on the support surface.Type: GrantFiled: April 11, 2006Date of Patent: August 16, 2011Assignee: Saes Getters S.p.A.Inventors: Sara Guadagnuolo, Marco Moraja, Andrea Conte
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Publication number: 20110180763Abstract: An oxide sintered body includes indium oxide and gallium solid-solved therein, the oxide sintered body having an atomic ratio “Ga/(Ga+In)” of 0.001 to 0.12, containing indium and gallium in an amount of 80 atom % or more based on total metal atoms, and having an In2O3 bixbyite structure.Type: ApplicationFiled: September 14, 2009Publication date: July 28, 2011Applicant: Idemitsu Kosan Co., Ltd.Inventors: Futoshi Utsuno, Kazuyoshi Inoue, Hirokazu Kawashima, Masashi Kasami, Koki Yano, Kota Terai
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Publication number: 20110180392Abstract: Disclosed is a sputtering target for an oxide semiconductor, comprising In, Ga, and Zn. Also disclosed are a process for producing the sputtering target, a thin film of an oxide semiconductor using a sputtering target, and a method for thin-film transistor formation. The sputtering target comprises an oxide sintered compact containing a compound having a homologous crystal structure represented by InGaO3(ZnO) and exhibits such an X-ray diffraction pattern that the proportion of peaks at 2?=62 to 63 degrees to the maximum peak of InGaO3(ZnO) is not more than 3%.Type: ApplicationFiled: June 26, 2009Publication date: July 28, 2011Inventors: Koki Yano, Hirokazu Kawashima
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Publication number: 20110175084Abstract: The present invention generally comprises a semiconductor film and the reactive sputtering process used to deposit the semiconductor film. The sputtering target may comprise pure zinc (i.e., 99.995 atomic percent or greater), which may be doped with aluminum (about 1 atomic percent to about 20 atomic percent) or other doping metals. The zinc target may be reactively sputtered by introducing nitrogen and oxygen to the chamber. The amount of nitrogen may be significantly greater than the amount of oxygen and argon gas. The amount of oxygen may be based upon a turning point of the film structure, the film transmittance, a DC voltage change, or the film conductivity based upon measurements obtained from deposition without the nitrogen containing gas. The reactive sputtering may occur at temperatures from about room temperature up to several hundred degrees Celsius. After deposition, the semiconductor film may be annealed to further improve the film mobility.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Applicant: APPLIED MATERIALS, INC.Inventor: Yan Ye
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Publication number: 20110171395Abstract: A sputtering target, including a sputtering layer and a support structure. The sputtering layer includes an alkali-containing transition metal. The support structure includes a second material that does not negatively impact the performance of a copper indium selenide (CIS) based semiconductor absorber layer of a solar cell. The sputtering layer directly contacts the second material.Type: ApplicationFiled: March 28, 2011Publication date: July 14, 2011Inventors: Daniel R. Juliano, Deborah Mathias, Neil M. Mackie
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Publication number: 20110139246Abstract: Methods of depositing a transparent conductive oxide layer on a substrate are generally disclosed. A shield of greater than about 75% by weight molybdenum can be attached to a first surface of a substrate such that the shield contacts at least about 75% of the first surface. The shield can then be heated via an energy source to cause thermal exchange from the shield to the substrate to heat the substrate to a sputtering temperature. A transparent conductive oxide layer can then be sputtered on a second surface of the substrate at the sputtering temperature. Methods are also generally disclosed for manufacturing a cadmium telluride based thin film photovoltaic device.Type: ApplicationFiled: December 16, 2009Publication date: June 16, 2011Applicant: PRIMESTAR SOLAR, INC.Inventor: JENNIFER A. DRAYTON
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Publication number: 20110132745Abstract: A method of fabricating a variable resistance layer of a resistance memory is disclosed. The method includes placing a substrate in a sputtering chamber that has a copper target and a silicon oxide (SiO2) target or has a complex target made from copper and silicon oxide therein. Thereafter, a co-sputtering process is performed by using the copper target and the silicon oxide target, or a sputtering process is performed by using the complex target, so that a compound film is deposited on a surface of the substrate, wherein the compound film serves as a variable resistance layer of a resistance memory, and the mole percentage of Cu/(Cu+Si) of the compound film is 1-15%.Type: ApplicationFiled: February 4, 2010Publication date: June 9, 2011Applicant: National Taiwan University of Science and TechnologyInventors: Shyan-kay Jou, Chia-Jen Li
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Publication number: 20110127157Abstract: A magnetron sputtering apparatus (100) comprising: a magnetic array arranged to create a magnetic field (103) in the vicinity of a tubular target (2) which target at least partially surrounds the magnetic array and acts as a cathode (2a); an anode (2b); the magnetic array being arranged to create an asymmetric plasma distribution with respect to the normal angle of incidence to a substrate (3); and means (1b) for enhancing the magnetic field to produce a relatively low impedance path for electrons flowing from the cathode (2a) to the anode (2b).Type: ApplicationFiled: August 14, 2008Publication date: June 2, 2011Applicant: GENCOA LTD.Inventor: Victor Bellido-Gonzalez
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Publication number: 20110127158Abstract: In a copper damascene wiring process, a tantalum-based laminated film, which is used as a barrier metal film, is continuously formed in a sputtering deposition chamber. When the continuous deposition process is discontinuously applied to a number of wafers, a tantalum film and a tantalum nitride film which are relatively thin are alternately deposited over an inner surface of a shield in a sputter deposition chamber, which results in a thickness of the deposited film being on the order of several thousand nanometers. The deposited film peels off due to internal stress therein to generate foreign material or particles. To counteract this, a tantalum film, which is much thicker than the tantalum film formed over the wafer at one time, is formed over the substantially inner wall of the chamber at predetermined intervals when repeatedly depositing the tantalum nitride film and the tantalum film in the sputtering deposition chamber.Type: ApplicationFiled: November 5, 2010Publication date: June 2, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takashi HAMAYA, Hidenori SUZUKI, Yuichi HARANO, Masahiko ITO
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Publication number: 20110108116Abstract: A p-type NiO conducting film for an organic solar cell, a preparation method thereof, and an organic solar cell using the same and having enhanced power conversion efficiency, are provided, wherein the NiO conducting film is fabricated by vacuum sputtering in which nickel or nickel oxide is used as a target material, and argon, oxygen or the mixed gas of the argon and the oxygen is supplied. The p-type NiO conducting film may be easily prepared by vacuum sputtering, and since a n-type conducting film is prepared by simply coating sol-phase precursor solution, the NiO conducting film and the organic solar cells having the NiO conducting film in the order of the NiO conducting film, a photoactive layer, and a n-type conducting film, have enhanced electric energy conversion. As a result, the provided disclosure is useful particularly when applied in organic solar cells and organic light emitting devices.Type: ApplicationFiled: October 1, 2010Publication date: May 12, 2011Applicant: KOREA INSTITUTE OF MACHINERY AND MATERIALSInventors: Jae-Wook Kang, Dong Ho Kim, Sun Young Park, Do-Geun Kim, Jong Kuk Kim
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Publication number: 20110100446Abstract: Certain example embodiments of this invention relate to a front transparent conductive electrode for solar cell devices (e.g., amorphous silicon or a-Si solar cell devices), and/or methods of making the same. Advantageously, certain example embodiments enable high haze to be realized in the top layer of the thin film stack. In certain example embodiments, an insertion layer comprising ITO or AZO is provided between a layer of AZO and a layer of ITO. The AZO may be deposited at room temperature. The insertion layer is provided with an oxygen content selected so that the insertion layer sufficient to alter the crystalline growth of the layer of AZO compared to a situation where no insertion layer is provided. In certain example embodiments, the layer of ITO may be ion-beam treated so as to roughen a surface thereof. The ion beam treating may be performed a voltage sufficient to alter the crystalline growth of the layer of AZO compared to a situation where no insertion layer is provided.Type: ApplicationFiled: November 5, 2009Publication date: May 5, 2011Applicant: Guardian Industries Corp.Inventor: Alexey Krasnov
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Publication number: 20110067997Abstract: A method for forming a high purity, copper indium gallium selenide (CIGS) bulk material is disclosed. The method includes sealing precursor materials for forming the bulk material in a reaction vessel. The precursor materials include copper, at least one chalcogen selected from selenium, sulfur, and tellurium, and at least one element from group IIIA of the periodic table, which may be selected from gallium, indium, and aluminum. The sealed reaction vessel is heated to a temperature at which the precursor materials react to form the bulk material. The bulk material is cooled in the vessel to a temperature below the solidification temperature of the bulk material and opened to release the formed bulk material. A sputtering target formed by the method can have an oxygen content of 10 ppm by weight, or less.Type: ApplicationFiled: September 17, 2010Publication date: March 24, 2011Inventors: Vinh Q. Nguyen, Jesse A. Frantz, Jasbinder S. Sanghera, Ishwar D. Aggarwal, Allan J. Bruce, Michael Cyrus, Sergey V. Frolov
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Publication number: 20110067998Abstract: An electrically conductive cadmium sulfide sputtering target, the method of making the same, and the method of manufacturing a photovoltaic cell using the same.Type: ApplicationFiled: September 20, 2009Publication date: March 24, 2011Applicant: MIASOLEInventor: Stephen Barry
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Publication number: 20110062016Abstract: There is provided a method for manufacturing an aluminum-containing nitride intermediate layer, a method for manufacturing a nitride layer, and a method for manufacturing a nitride semiconductor element by using the nitride layer, in which at least one of the following conditions (i) to (iii) is employed during stacking of the aluminum-containing nitride intermediate layer by using a DC magnetron sputtering method in which a voltage is applied by means of a DC-continuous scheme. (i) The shortest distance between a center of a surface of a target and a growth surface of a substrate is set to 100 mm or more and 250 mm or less. (ii) Nitrogen gas is used as gas supplied to a DC magnetron sputtering apparatus. (iii) The target is inclined with respect to the growth surface of the substrate.Type: ApplicationFiled: August 11, 2010Publication date: March 17, 2011Applicant: Sharp Kabushiki KaishaInventors: Masahiro ARAKI, Takaaki Utsumi, Masahiko Sakata
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Publication number: 20110061724Abstract: A photovoltaic cell module, a photovoltaic array including at least two modules, and a method of forming the module are provided. The photovoltaic cell module includes a substrate and a tie layer disposed on the substrate. The tie layer has a depth of penetration of from 1.1 to 100 mm and a tack value of less than ?0.6 g·sec. The photovoltaic cell module also includes a photovoltaic cell disposed on the tie layer. The method of forming the photovoltaic cell module includes the steps of disposing the tie layer on the substrate and disposing the photovoltaic cell on the tie layer to form the photovoltaic cell module.Type: ApplicationFiled: March 13, 2009Publication date: March 17, 2011Inventors: Kevin Houle, Malinda Howell, David Johnson, Donnie Juen, Barry Ketola, Nick Evan Shephard
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Publication number: 20110065236Abstract: A method for maintaining a smooth surface of crystallizable material is disclosed. First, a substrate is provided. A target material layer is then formed on the substrate, with the target material being a crystallizable material. A protecting layer is subsequently formed on the target material layer. Next, an annealing treatment is implemented, with the surface of the target material layer, facing the protecting layer, being maintained in its original smooth state by the pressure and/or adhesion of the protecting layer. Finally, the protecting layer is removed to leave an open and smooth surface of the processed crystallizable material.Type: ApplicationFiled: October 28, 2009Publication date: March 17, 2011Applicant: National Taiwan UniversityInventors: CHING-FUH LIN, CHA-HSIN CHAO, WEN-HAN LIN
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Publication number: 20110048928Abstract: Embodiments of the invention relate generally to semiconductor device fabrication and processes, and more particularly, to methods for implementing arrangements of magnetic field generators configured to facilitate physical vapor deposition (“PVD”) and/or for controlling impedance matching associated with a non-metal-based plasma used to modify a non-metal film, such as a chalcogenide-based film.Type: ApplicationFiled: August 31, 2009Publication date: March 3, 2011Applicant: Semicat, Inc.Inventors: Jin Hyun Kim, Michael Nam, Jae Yeol Park, Jonggu Park
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Publication number: 20110048515Abstract: A solar cell module layer stack is described. The layer stack includes a doped silicon wafer substrate, a back contact layer for the solar cell module, and a first sputtered and annealed passivation layer between the wafer substrate and the back contact layer, wherein the passivation layer is selected from the group consisting of: an aluminum containing oxide layer, an aluminum containing nitride layer, an aluminum containing oxynitride layer, and mixtures thereof.Type: ApplicationFiled: September 8, 2009Publication date: March 3, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Manfred ENGLERT, Sven SCHRAMM, Roland TRASSL
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Patent number: 7887677Abstract: A silicon object formation target substrate is arranged in a first chamber, a silicon sputter target is arranged in a second chamber communicated with the first chamber, plasma for chemical sputtering is formed from a hydrogen gas in the second chamber, chemical sputtering is effected on the silicon sputter target with the plasma thus formed, producing particles contributing to formation of silicon object, whereby a silicon object is formed, on the substrate, from the particles moved from the second chamber to the first chamber.Type: GrantFiled: September 21, 2006Date of Patent: February 15, 2011Assignee: Nissin Electric Co., Ltd.Inventors: Takashi Mikami, Atsushi Tomyo, Kenji Kato, Eiji Takahashi, Tsukasa Hayashi
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Publication number: 20110011460Abstract: In one example embodiment, a method includes sputtering one or more absorber layers over a substrate. In a particular embodiment, the substrate is pre-heated to a substrate temperature of at least approximately 300 degrees Celsius prior to the sputtering and during the sputtering of each of one or more of the absorber layers, and the sputtering of at least one of the absorber layers is performed in a sputtering atmosphere having a pressure of at least 0.5 Pascals. Additionally, in a particular embodiment, the sputtering of at least one of the absorber layers comprises sputtering from a sputter target that comprises a chalcogenide alloy that comprises copper (Cu) and one or more of sulfur (S), selenium (Se), or tellurium (Te).Type: ApplicationFiled: December 18, 2009Publication date: January 20, 2011Applicant: APPLIED QUANTUM TECHNOLOGYInventors: Mariana Rodica Munteanu, Erol Girt
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Publication number: 20110005922Abstract: A method for creating a protective layer over a surface of an object comprising aluminum and magnesium for use in a semiconductor processing system, which includes oxidizing the surface of the object using a plasma electrolytic oxidation process. The method also includes generating a halogen-comprising plasma by exciting a gas comprising a halogen. The method also includes exposing the oxidized surface to the halogen-comprising plasma or excited gas.Type: ApplicationFiled: July 8, 2009Publication date: January 13, 2011Applicant: MKS Instruments, Inc.Inventors: Chiu-Ying Tai, Xing Chen, Chaolin Hu, Andrew Cowe, Ali Shajii
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Publication number: 20110000541Abstract: Disclosed is a method for depositing a film onto a substrate, with a sputter deposition process wherein the sputter deposition process is a direct current sputter deposition wherein the film consists of at least 90 wt-% of an inorganic material having semiconductor properties whereby the film of the inorganic material M2 is directly deposited as crystalline structure, so that at least 50 wt-% of the deposited film has a crystalline structure wherein the source material (target) used for the sputter deposition consists of at least 80 wt-% of the inorganic material M2. wherein the inorganic material is selected from a group including binary, ternary, and quaternary compounds including sulphur, selenium, tellurium, indium, and/or germanium.Type: ApplicationFiled: March 2, 2009Publication date: January 6, 2011Applicant: LAM RESEARCH AGInventors: Uwe Brendel, Herbert Dittrich, Hermann-Josef Schimper, Andreas Stadler, Dan Topa, Angelika Basch
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Publication number: 20100330738Abstract: An oxide semiconductor target of a ZTO (zinc tin complex oxide) type oxide semiconductor material of an appropriate (Zn/(Zn+Sn)) composition having high mobility and threshold potential stability and with less restriction in view of the cost and the resource and with less restriction in view of the process, and an oxide semiconductor device using the same, in which a sintered Zn tin complex oxide with a (Zn/(Zn+Sn)) composition of 0.6 to 0.8 is used as a target, the resistivity of the target itself is at a high resistance of 1 ?cm or higher and, further, the total concentration of impurities is controlled to 100 ppm or less.Type: ApplicationFiled: April 9, 2010Publication date: December 30, 2010Inventors: Hiroyuki Uchiyama, Hironori Wakana, Tetsufumi Kawamura, Fumi Kurita, Hideko Fukushima
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Patent number: 7851691Abstract: High performance thin film thermoelectric couples and methods of making the same are disclosed. Such couples allow fabrication of at least microwatt to watt-level power supply devices operating at voltages greater than one volt even when activated by only small temperature differences.Type: GrantFiled: September 28, 2007Date of Patent: December 14, 2010Assignee: Battelle Memorial InstituteInventors: John G. DeSteese, Larry C. Olsen, Peter M. Martin
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Patent number: 7847187Abstract: The invention relates to a photovoltaic cell comprising a photovoltaically active semiconductor material, wherein the photovoltaically active semiconductor material is a p- or n-doped semiconductor material comprising a binary compound of the formula (I) or a ternary compound of the formula (II): ZnTe??(I) Zn1-xMnxTe??(II) where x is from 0.01 to 0.99, and a particular proportion of tellurium ions in the photovoltaically active semiconductor material has been replaced by halogen ions and nitrogen ions and the halogen ions are selected from the group consisting of fluoride, chloride and bromide and mixtures thereof.Type: GrantFiled: October 26, 2005Date of Patent: December 7, 2010Assignee: BASF AktiengesellschaftInventor: Hans-Josef Sterzel