Selected Area Patents (Class 205/221)
  • Patent number: 6312581
    Abstract: A process for fabricating a silica-based optical device on a silicon substrate is disclosed. The device has a cladding formed in a silicon substrate. The device also has an active region, and that active region is formed on the cladding. The cladding is fabricated by forming a region of porous silicon in the silicon substrate. The porous silicon is then oxidized and densified. After densification, the active region of the device is formed on the cladding.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: November 6, 2001
    Assignee: Agere Systems Optoelectronics Guardian Corp.
    Inventors: Allan James Bruce, Alexei Glebov, Joseph Shmulovich, Ya-Hong Xie
  • Patent number: 6274057
    Abstract: Metallic bumps are formed for electrical interconnection between the charge plate and the charge drive electronics. This is achieved by having improved electrical connection between an ink jet charge plate and associated charge leads is promoted. First, a mask is aligned to permit plating of an etch mask on the charge plate coupon on the side opposite the charge plate circuitry, so as to place masked regions directly across the coupon from the contact pads of the charge plate circuitry. All the copper alloy charge plate coupon is then etched away except the small portions between the termination and the etch mask. The bump thus formed is used to provide a high pressure point electrical connection to the charge plate.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: August 14, 2001
    Assignee: Scitex Digital Printing, Inc.
    Inventors: Richard W. Sexton, James E. Harrison, Jr.
  • Patent number: 6267862
    Abstract: A plating apparatus and methodology is disclosed that is particularly useful in improving the plating rate, improving the plating of via holes, improving the uniformity of the plating deposition across the surface of the wafer, and minimizing damage to the wafer. With regard to improving the plating rate and the plating of via holes, the plating apparatus and method immerses a wafer in a plating fluid bath and continuously directs plating fluid towards the surface of the wafer. Immersing the wafer in a plating fluid bath reduces the occurrence of trapped gas pockets within via holes which makes it easier to plate them. The continuous directing of plating fluid towards the surface of the wafer increases the ion concentration gradient which is, in turn, increases the plating rate.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: July 31, 2001
    Assignee: Technic Inc.
    Inventors: Robert Kaufman, Gary C. Downes
  • Patent number: 6231744
    Abstract: An array of nanowires having a relativley constant diameter and techniques and apparatus for fabrication thereof are described. In one embodiment, a technique for melting a material under vacuum and followed by pressure injection of the molten material into the pores of a porous substrate produces continuous nanowires. In another embodiment, a technique to systematically change the channel diameter and channel packing density of an anodic alumina substrate includes the steps of anodizing an aluminum substrate with an electrolyte to provide an anodic aluminum oxide film having a pore with a wall surface composition which is different than aluminum oxide and etching the pore wall surface with an acid to affect at least one of the surface properties of the pore wall and the pore wall composition.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: May 15, 2001
    Assignee: Massachusetts Institute of Technology
    Inventors: Jackie Y. Ying, Zhibo Zhang, Lei Zhang, Mildred S. Dresselhaus
  • Patent number: 6224735
    Abstract: A transparent support having formed thereon a transparent conductive film and an organic or inorganic semiconductor thin film that generates an electromotive force by irradiation of light formed on the transparent conductive film, and an aqueous electrolytic solution containing a solvent, a coloring material and a polymer electrodeposition material, whose solubility in the solvent changes depending on the change of pH are prepared; the substrate and a counter electrode connected to the substrate are arranged in such a manner that an surface of the substrate, on which the semiconductor thin film is formed, and the counter electrode are immersed in the aqueous electrolytic solution; the transparent support is selectively irradiated with light; an electrodeposition film having the coloring material and the polymer electrodeposition material is deposited on a part of the support, on which an electromotive force is generated; and the deposited electrodeposition film is brought into contact with an aqueous liquid h
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: May 1, 2001
    Assignee: Fuji Xerox Co. Ltd.
    Inventors: Eiichi Akutsu, Shigemi Ohtsu, Lyong sun Pu
  • Patent number: 6224738
    Abstract: This present invention is directed to a method of etching anodic foil for electrolytic capacitors and provides a method of electrolytically growing a porous oxide mask on a surface of a high purity etchable strip of anodic foil for forming etch tunnels at strategic locations on the foil. Unetched high purity aluminum foil is placed in a prepared electrolyte doped with chloride. By passing current through the foil, a porous oxide mask is formed on the surface of the anode foil, with an optimized pore spacing. This oxide mask is then partially removed with a stripping agent in order to expose the underlying anode foil at the bottom of the mask pores to the etch solution. The mask is not removed completely, and the anode foil is exposed only at the pore sites. The foil can then be etched using a conventional etch solution. Etch pits and tunnels form only at the pore sites.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: May 1, 2001
    Assignee: Pacesetter, Inc.
    Inventors: Katherine Crawford Sudduth, Thomas Flavian Strange
  • Patent number: 6179988
    Abstract: This invention relates to a process for making wire, comprising: (A) forming a circular disk of electrodeposited copper, (B) rotating said disk about its center axis; (C) feeding a cutting tool into the peripheral edge of said disk to cause a strip of copper to peel from said disk; and (D) slitting said strip of copper to form a plurality of strands of copper wire.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: January 30, 2001
    Assignee: ElectroCopper Products Limited
    Inventors: Peter Peckham, Craig J. Hasegawa
  • Patent number: 6136175
    Abstract: The electronic component, specifically a SAW component with conductive structures disposed on a substrate is encapsulated for protection against environmental influences. The electrically conductive structures are sealed with a gas diffusion-constricting protective layer formed with an electrochemical or ion bombardment process.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: October 24, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Alois Stelzl, Hans Kruger, Wolfgang Pahl, Jurgen Machui
  • Patent number: 6048446
    Abstract: The present invention provides several methods for engraving gravure cylinders much more rapidly and at a higher resolution while, at the same time, reducing the engraving cost. The present invention employs a resist that is deposited onto the surface of a gravure cylinder. The resist is capable of being physically and/or chemically changed in response to being exposed to a form of actinic energy, such as a laser beam. The exposed areas of resist allow a material, such as chromium, to be plated onto the surface of the gravure cylinder to form walls that define cells therebetween. In use, the cells contain ink for printing the desired patterns of text and/or images.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: April 11, 2000
    Assignee: R.R. Donnelley & Sons Company
    Inventor: A. John Michaelis
  • Patent number: 5997713
    Abstract: An element with elongated, high aspect ratio channels such as microchannel plate is fabricated by electrochemical etching of a p-type silicon element in a electrolyte to form channels extending through the element. The electrolyte may be an aqueous electrolyte. For use as a microchannel plate, the; the silicon surfaces of the channels can be converted to insulating silicon dioxide, and a dynode material with a high electron emissivity can be deposited onto the insulating surfaces of the channels. New dynode materials are also disclosed.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: December 7, 1999
    Assignee: NanoSciences Corporation
    Inventors: Charles P. Beetz, Jr., Robert W. Boerstler, John Steinbeck, David R. Winn
  • Patent number: 5997709
    Abstract: Methods of providing diffusing risers on a fresnel lens die having a plurality of optical facets, wherein adjacent optical facets are separated by a riser, the method including the steps of depositing a difflusing layer on the plurality of optical facets and the risers, and selectively removing the diffusing layer from the plurality of optical facets, wherein the diffusing layer remains substantially intact on the risers. The diffusing layer can be deposited in an electrolyte bath substantially free of grain refiners.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: December 7, 1999
    Assignee: Minnesota Mining and Manufacturing Co.
    Inventor: Harlan L. Krinke
  • Patent number: 5989631
    Abstract: The invention relates to a process for equipping a kitchenware object, for example a pan, a pot, roasters or the like, comprising metal, for example aluminum, an aluminum alloy, magnesium or a magnesium alloy, with an anti-adhesion coating in the stressed surface regions, for example, on the inside, in which onto the metal surface of the object, for example after roughening, a mechanically-resistant layer, such as a mechanically-resistant anodization layer or similar mechanically-resistant layer is provided, and subsequently the stressed surface regions are provided with the anti-adhesion layer, wherein, before providing the mechanically-resistant layer, a durable surface layer is applied onto the surface regions, not to be provided with the coating system (mechanically-resistant layer or the like with or without anti-adhesion layer), of the object.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: November 23, 1999
    Assignee: Fissler GmbH
    Inventor: Klaus Dorfschmidt
  • Patent number: 5944976
    Abstract: A process for forming adjacent moats or holes in an electrically non-insulating substrate wherein an electrically insulating masking layer is deposited on the substrate. To form two adjacent moats or holes, the masking layer has an opening whose width is chosen so that it extends over a part of the overall width of the two moats or holes to be formed, and whose shape corresponds to the shape of the moats or holes to be formed. The surface of the masked substrate is then subjected to an anodic oxidation, with the oxidation voltage chosen to be so high that two adjacent moats or holes are formed per opening in the masking layer.
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: August 31, 1999
    Assignee: Micronas Intermetall GmbH
    Inventor: Gunter Igel
  • Patent number: 5944975
    Abstract: A method of fabricating an emitter plate 12 for use in a field emission device comprising the steps of providing an insulating substrate 18 and forming a first conductive layer 13 on the insulating substrate 18. This is followed by the steps of forming an insulating layer 20 on the first conductive layer 13 and forming a second conductive layer 22 on the insulating layer 20. Then, a plurality of apertures 34 are formed through the second conductive layer 22 and through the insulating layer 20. A lift-off layer 36 is then formed on the second conductive layer 22. The lift-off layer 36 is formed by a plating process wherein the plating bath has a pH between 2.25 and 4.5, and current densities of 1 to 2O mA/cm.sup.2. The method may further comprise depositing conductive material through the plurality of apertures 34 to form a microtip 14 in each of the plurality of apertures 34. The excess deposited conductive material 14' and the lift-off layer 36 are then removed from the second conductive layer 22.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: August 31, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Arthur M. Wilson, Chi-Cheong Shen, Saroja Ramamurthi
  • Patent number: 5902475
    Abstract: Disclosed herewithin is a method of fabricating a stent which involves processing a tubular member whereby no connection points to join the edges of a flat pattern are necessary. The method includes the steps of a) removing contaminates from a tubular member, b) coating the outside surface of the tubular member with a photo-sensitive resist material, c) placing the tubular member in an apparatus designed to simultaneously rotate the tubular member while passing a specially configured photographic frame negative between a UV light source and the tubular member, thereby exposing a specified pattern of UV light to the resist coated tubular member, d) exposing the outside surface of the tubular member to a photoresist developer for a specified period of time, e) rinsing the excess developer and uncured resist from the outside surface of the tubular member, f) treating the tubular member with a electro-chemical process to remove uncovered metal.
    Type: Grant
    Filed: April 8, 1997
    Date of Patent: May 11, 1999
    Assignee: Interventional Technologies, Inc.
    Inventors: Thomas Trozera, Gary W. Gomringer
  • Patent number: 5897762
    Abstract: A method for coloring tool bits includes cutting a beam having a hexagonal cross section into a number of segments. The segments are electroplated for forming an outer layer on the segments. The segments each have one or two of the ends machined to form a tool bit end for engaging with fasteners. The segments are then dyed for allowing color material to be attached onto the tool bit end and for coloring the tool bit end. The electroplated outer layer may prevent the color material from attaching onto the outer peripheral portion of the segments.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: April 27, 1999
    Inventor: Kuo Tien Liu
  • Patent number: 5865978
    Abstract: A new field of technology, near-field photolithography, is proposed. In near-field photolithography, an opaque pattern having a nanoscale resolution is made using a modified scanning tunneling microscope to deposit the opaque material on an electrically conductive material. A transparent sheet of indium tin oxide is patterned with a plurality of opaque copper deposits having a nanoscale resolution. The patterned indium tin oxide is then used as a photolithographic mask in the optical near-field. Near-field resolution is not diffraction limited, and near-field photolithography is able to pattern objects with sub-wavelength resolution. As a result, smaller semiconductor microchips can be manufactured and a new nanotechnology, e.g., nanomachines, can be developed. The scanning tunneling microscope (STM) is used as an "electrochemical paintbrush" to transfer the copper from a massive copper supply to the STM electrode tip and then to the ITO surface without degrading the STM tip.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: February 2, 1999
    Inventor: Adam E. Cohen
  • Patent number: 5681444
    Abstract: Electrical feedthroughs in printed circuit board support substrates for use in making double sided ceramic multilayer printed circuit boards are made by insulating the feedthrough openings with a first layer of nickel oxide and one or more layers of glass, and then filling the remainder of the feedthroughs with a conductive metal via fill ink. After firing, the resultant structure provides insulated electrical feedthroughs through the support substrate.
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: October 28, 1997
    Assignee: David Sarnoff Research Center, Inc.
    Inventors: Thomas Peter Azzaro, Barry Jay Thaler, Edward James Conlon, Ananda Hosakere Kumar
  • Patent number: 5650042
    Abstract: In an SOI substrate having a base substrate, an insulating film and a semiconductor active layer, a potential difference is given between the base substrate and an etching solution or among the base substrate, the semiconductor active layer and the etching solution to form a uniform depletion layer on the active layer side from the interface between the insulating film and the active layer. The semiconductor active layer is uniformly thinned down by etching using a solution or by the combination of chemical or electro-chemical surface and etching with the resultant reaction product. In this case, the individual electrodes are provided with seal members to prevent the base substrate electrode and the active layer electrode from contacting the etching solution or the reaction solution due to the etching using the etching solution or the chemical reaction using the reaction solution.
    Type: Grant
    Filed: September 27, 1995
    Date of Patent: July 22, 1997
    Assignee: NEC Corporation
    Inventor: Atsushi Ogura
  • Patent number: 5591480
    Abstract: One method for fabricating solderable pads (406) onto a substrate (220) for direct chip attachment uses a multilayer metallization coating (500). The coating has a bottom layer (202) of indium-tin oxide, with an intermediate layer (204) of copper and a top layer (206) of indium-tin oxide. A masking layer (208) is deposited on the active display area (402) of the substrate, leaving the bonding pads uncovered. The revealed bonding pads are then plasma etched, using the polyimide as an etch resist, and the top layer of ITO is selectively removed to reveal the underlying copper layer. The exposed copper layer (204) is then plated with a solderable metal to the desired thickness to form bonding pads that may be used with direct chip attachment schemes.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: January 7, 1997
    Assignee: Motorola, Inc.
    Inventors: Douglas H. Weisman, Thomas J. Swirbel, John K. Arledge
  • Patent number: 5527426
    Abstract: An improved process is disclosed for deinking waste paper which contains laser, electrostatic, and other non-impact printing toners/inks to produce high quality (high brightness, little to no dirt content) pulp with little or no fiber loss. The process involves attachment of ink particles in the waste paper pulp to a magnetic carrier material with the help of an agglomeration agent followed by removal of the attached ink particles by magnetic separation. The magnetic treatment preferably is conducted at ambient or greater temperature, at neutral to alkaline pH, and at a low pulp consistency. Agglomeration and magnetite addition, followed by exposure of the repulped waste paper to a magnetic field provides near complete ink removal over exposure to the magnetic field without such pretreatment.
    Type: Grant
    Filed: May 5, 1994
    Date of Patent: June 18, 1996
    Assignee: Westvaco Corporation
    Inventors: Nipun Marwah, Allen A. Gold
  • Patent number: 5525205
    Abstract: A process for forming an electrical circuit component includes forming an initial metal layer on a surface of a synthetic plastics substrate, and irradiating the initial metal layer with laser light along a closed path so as to remove the initial metal layer therealong. The closed path irradiated by the laser light thereby establishes an insulating region covered by a first portion of the initial metal layer which is bounded by the closed path, and a conducting region covered by a second portion of the initial metal layer which surrounds the closed path and the insulating region established thereby. A further metal layer is then formed over the second portion of the initial metal layer of the conducting region. The first portion of the initial metal layer of the insulating region may thus be removed to thereby expose a corresponding surface portion of the synthetic plastics substrate.
    Type: Grant
    Filed: August 19, 1994
    Date of Patent: June 11, 1996
    Assignee: Polyplastics Co., Ltd.
    Inventor: Takayuki Miyashita
  • Patent number: 5503732
    Abstract: A method for manufacturing a substrate useful as a color filter for LCD and having window-shaped coating films and a frame-shaped, functional coating film at the regions not occupied with the window-shaped coating films, which comprises the steps of:(a) forming a functional coating film on a transparent substrate having electrically conductive circuits on a surface thereof,(b) superposing a photomask having a predetermined pattern on the surface of the coating film formed in step (a), and exposing the thus masked coating film to light,(c) subjecting the intermediate product to developing to leave a frame-shaped coating film, and(d) subjecting the resulting substrate formed through steps (a) to (c) to electro-deposition to form electro-deposition coating films on the electrically conductive circuits, enables production of coating films of fine pattern with improved precision.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: April 2, 1996
    Assignee: Shinto Paint Co., Ltd.
    Inventors: Susumu Miyazaki, Tsuyoshi Nakano, Yoshikatsu Okada, Yasuhiko Teshima, Miki Matsumura
  • Patent number: 5486282
    Abstract: A tool and process for electroetching metal films or layers on a substrate employs a linear electrode and a linear jet of electrolyte squirted from the electrode. The electrode is slowly scanned over the film by a drive mechanism. The current is preferably intermittent. In one embodiment a single wafer surface (substrate) is inverted and the jet is scanned underneath. In another embodiment wafers are held vertically on opposite sides of a holder and two linear electrodes, oriented horizontally and on opposite sides of the holder, are scanned vertically upward at a rate such that the metal layers are completely removed in one pass. The process is especially adapted for fabricating C4 solder balls with triple seed layers of Ti-W (titanium-tungsten alloy) on a substrate, phased Cr-Cu consisting of 50% chromium (Cr) and 50% copper (Cu), and substantially pure Cu. Solder alloys are through-mask electrodeposited on the Cu layer. The seed layers conduct the plating current.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: January 23, 1996
    Assignee: IBM Corporation
    Inventors: Madhav Datta, Ravindra Shenoy
  • Patent number: 5458763
    Abstract: A wiring pattern forming method in which side etch of a wiring pattern at the time of etching the substrate copper foil of a copper plating pattern is reduced to hold down an increase in line resistance, the wiring pattern forming method including the steps of: providing a plating resist pattern of which open area comprises a wiring pattern on the surface of a copper-clad laminate which is obtained by providing a copper foil on an insulating substrate; plating such open area with copper to form a copper plating pattern; then plating a crevice between the copper plating pattern and the plating resist pattern with a solder film by alternately repeating application of a current for a predetermined time period and suspension of the current application for a predetermined time period; and etching away the copper foil by using the solder film as an etching resist to form the wiring pattern.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: October 17, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shiro Kobayashi, Toshinari Takada, Haruo Akahoshi, Tomoyuki Miyazaki, Kanji Yamamoto
  • Patent number: 5385638
    Abstract: A method of manufacturing a stamper includes the steps of coating a flat surface of a substrate with photosensitive material; directing light to a specified position on the photosensitive material to expose it; developing the photosensitive material to make a minute photoresist pattern; etching the substrate to a specified depth with a mask of the photoresist pattern; removing the photoresist as the mask to make a glass master; arbitrarily forming a first nickel layer on a surface of the glass master; forming an intermediate layer of a metal having a smaller linear expansion coefficient than nickel over the first nickel layer; forming a second nickel layer on the intermediate layer to form a conductive film having a two- or three-stratum structure; arbitrarily subjecting the whole substrate to a process to make nickel passive; forming an electroformed layer on the conductive film by an electroforming process; and separating the conductive film from the glass master.
    Type: Grant
    Filed: May 3, 1993
    Date of Patent: January 31, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hitoshi Isono, Hirotoshi Takemori
  • Patent number: 5368704
    Abstract: A micromachined valve and valve array having one or more pores which are electrochemically opened and closed by dissolving and redepositing a barrier layer across a tiny opening or pore in substrate. The pore is spanned by two electrodes which apply a voltage to an electrolytic barrier layer material which dissolves in an electrolyte. Each open pore has a distinct flow rate related to its minimal cross-sectional area which together can form a binary sized array with each subsequent member in the array having a flow rate twice as large as the preceding member in the array. Any integral multiple of the smallest flow rate may be achieved by opening an appropriate combination of the pores with addressing logic. In a preferred embodiment, each bit in a binary representation of the desired flow rate acts as a switch for a pore having a flow rate corresponding to the bit position.
    Type: Grant
    Filed: August 6, 1993
    Date of Patent: November 29, 1994
    Assignee: Teknekron Corporation
    Inventors: Marc J. Madou, Michael J. Tierney
  • Patent number: 5366613
    Abstract: An electrochemical fine processing method for forming a pattern of a substance having different etching resistance against an etching solution from that of an article by bringing the minute forward end of the counter electrode close to the surface of the article. The counter electrode is applied a predetermined electric potential and the electrochemical reaction is repeating in a minute region of the article in the vicinity of the counter electrode to form an optional pattern. After forming the pattern, the article is etched in an etching solution having a property of different etching rate for the pattern forming portion and a portion other than the pattern forming portion. It become possible to form a fine pattern directly onto the surface of an article to be processed having surface unevenness.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: November 22, 1994
    Assignee: Seiko Instruments Inc.
    Inventors: Masayuki Suda, Toshihiko Sakuhara, Masataka Shinogi, Fumiharu Iwasaki, Akito Ando
  • Patent number: 5200056
    Abstract: A thin film magnetic read/write head is manufactured using a multi-layered sacrificial mask in a pole tip alignment process. The sacrificial mask includes a layer of metal deposited upon the magnetic upper pole tip. Subsequent sacrificial mask layers include nickel-iron alloy or photoresist. Following an ion milling alignment process, residual sacrificial mask layers are removed using a process in which the medal layer is selectively chemically etched away from the thin film magnetic head.
    Type: Grant
    Filed: February 7, 1992
    Date of Patent: April 6, 1993
    Assignee: Seagate Technology Inc.
    Inventors: Uri Cohen, Nurul Amin
  • Patent number: 5141623
    Abstract: A thin film magnetic read/write head is manufactured using a multi-layered sacrificial mask in a pole tip alignment process. The sacrificial mask includes a layer of metal deposited upon the magnetic upper pole tip. Subsequent sacrificial mask layers include nickel-iron alloy or photoresist. Following an ion milling alignment process, residual sacrificial mask layers are removed using a process in which the medal layer is selectively chemically etched away from the thin film magnetic head.
    Type: Grant
    Filed: February 15, 1990
    Date of Patent: August 25, 1992
    Assignee: Seagate Technology, Inc.
    Inventors: Uri Cohen, Nurul Amin
  • Patent number: 5122237
    Abstract: A high molecular humidity sensor and manufacturing method thereof in which polypyrrole being of conductive high molecule is electrochemically polymerized and then reduced whereby ionic conductive property is given go that humidity sensibility becomes excellent.The high molecular humidity sensor of the invention is characterized in that it is a structure in which polypyrrole doped with dodecylsulfate anion DS.sup.- is stuck in film form on the surface of fine electrode, and cations Na.sup.+, K.sup.+ are permeated to said polypyrrole whereby salt is formed, and humidity sensibility is exhibited in region of 10.sup.4 -10.sup.6 .OMEGA., and humidity sensing speed becomes within several tens seconds to several minutes.
    Type: Grant
    Filed: January 22, 1991
    Date of Patent: June 16, 1992
    Assignee: Korea Institute of Science and Technology
    Inventors: Chung Y. Kim, Hee-Woo Rhee, Inseok Hwang, Jai K. Kim
  • Patent number: 5110421
    Abstract: A process for selectively plating separate surfaces of a component. The process includes electroplating a first material onto a first surface, applying a masking agent to the component, tumbling a plurality of components to remove the masking agent from a second surface, electroplating a second material onto the second surface, the masking agent preventing electroplating on the first surface, and then removing the masking agent from the first surface.
    Type: Grant
    Filed: May 24, 1991
    Date of Patent: May 5, 1992
    Assignee: The Torrington Company
    Inventor: Alan L. Gabrielson
  • Patent number: 5098527
    Abstract: A method of making a pattern on an electrically conductive material such as a printed circuit comprises(i) electrodepositing on an electrically conductive surface a film of an organic polymer having, per average molecule, more than one reactive functional group,(ii) forming on the electrodeposited film a predetermined pattern of a heat-curable resist having, per average molecule, more than one group reactive with the reactive groups in the electrodeposited film on heating, thereby leaving predetermined areas of the electrodeposited film uncovered,(iii) removing the uncovered areas of the electrodeposited film by treatment with a solvent therefor, thereby forming a surface comprising bare conductive material in predetermined areas and, in other predetermined areas, conductive material coated by areas of the electrodeposited film covered by the resist, and(iv) heating to complete adhesion of the resist to the electrically conductive surface through the areas of the electrodeposited film covered by the resist,st
    Type: Grant
    Filed: September 18, 1989
    Date of Patent: March 24, 1992
    Assignee: Ciba-Geigy Corporation
    Inventors: Christopher P. Banks, Edward Irving
  • Patent number: 5092968
    Abstract: A method for use in photochemical machining of titanium or zirconium substrate articles. A coating of silver is deposited onto the substrate and a photoresist is applied onto this coating. The photoresist is selectively patterned and removed from unexposed areas thereof. The silver coating is then selectively removed from the substrate at areas not covered by the photoresist without removing material from the substrate. Photochemical etching is then performed to remove material from the substrate at areas thereof not covered by the silver coating. The remaining silver coating may then be removed to yield a titanium or zirconium workpiece having the desired pattern etched into the surface thereof.
    Type: Grant
    Filed: June 3, 1991
    Date of Patent: March 3, 1992
    Assignee: United Technologies Corporation
    Inventor: Brian A. Manty
  • Patent number: 5078834
    Abstract: A method and arrangement for providing damping of undesired modes of piezoelectric vibrators is disclosed that eliminates the tedious and often inaccurate methods of known mass-loading techniques. Instead, the arrangement relies on physically altering a controlled amount of the piezoelectric material located at a predetermined point to effect the selective damping needed to minimize the undesired responses and to minimally interfere with the desired mode of operation.
    Type: Grant
    Filed: May 4, 1989
    Date of Patent: January 7, 1992
    Assignee: Motorola, Inc.
    Inventor: Robert S. Witte