Simultaneous Deplating And Plating Patents (Class 205/87)
  • Publication number: 20140262791
    Abstract: Coating bath compositions and processes useful in depositing organic polymeric coatings on metal substrates at low voltages are provided, the baths comprising one or more dispersed organic film forming polymers; and an etchant; wherein the principle film forming polymer is stabilized in the bath by the presence of anionic surfactant, but can be readily anodically deposited under low voltage. The invention also relates to processes of depositing a coating and metal substrates coated using the baths and processes of the invention.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Manesh N. SEKHAREN, Shawn E. DOLAN, Brian J. MARVIN, Bashir M. AHMED, John D. McGEE, Omar L. ABU-SHANAB, Derek A. HICKEY
  • Publication number: 20130075265
    Abstract: Methods for electrochemically processing microfeature wafers using at least one counter electrode in a vessel, a supplementary electrode and a supplementary virtual electrode. The supplementary electrode is configured to operate independently from the counter electrode in the vessel, and it can be a thief electrode and/or a de-plating electrode depending. The supplementary electrode can further be used as another counter electrode during a portion of a plating cycle or polishing cycle. The supplementary virtual electrode is located in the processing zone, and it is configured to counteract an electric field offset relative to the wafer associated with an offset between the wafer and the counter electrode.
    Type: Application
    Filed: November 20, 2012
    Publication date: March 28, 2013
    Applicant: APPLIED MATERIALS INC.
    Inventor: Applied Materials Inc.
  • Patent number: 8315036
    Abstract: A ceramic electronic component includes a ceramic body and a plurality of external electrodes disposed at a surface of the ceramic body. The external electrodes include a plating layer containing glass particles each coated with a metal film. The plating layer is formed by co-deposition of a plating metal and the metal-coated glass particles.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: November 20, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Makoto Ogawa, Akihiro Motoki, Junichi Saito, Shunsuke Takeuchi, Kenichi Kawasaki
  • Patent number: 8282805
    Abstract: An improved process for treating an electrically conductive surface of a workpiece by cleaning or coating the surface is provided, comprising the steps of deploying the electrically conducting surface of the workpiece to form a cathode in an electrolytic cell; establishing a DC voltage between the cathode and an anode; forming a working gap between the anode and the cathode, and establishing a seal around the working gap to form a sealed treatment zone; delivering into the working gap an electrically conductive medium selected from the group consisting of: (A) an aqueous electrolyte from which a foam is created; (B) a foam; and a mixture of components (A) and (B), so that electrically conductive medium consisting of a foam comprising a gas/vapor phase and a liquid phase fills the working gap, wherein said electrically conductive medium enters the electrolytic cell through tubes having discharge ends oriented at approximately ten degrees from parallel to the workpiece, and wherein turbulence is created within
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: October 9, 2012
    Inventor: Edward O. Daigle
  • Patent number: 8142636
    Abstract: The present invention relates to a method of electrochemically desorbing or adsorbing a cryptate [18F] fluoride complex using a substituent substituted cryptand A. The present invention also relates to an apparatus and a kit for performing this method. A: which can be used for nucleophilic radiofluorination.
    Type: Grant
    Filed: June 9, 2007
    Date of Patent: March 27, 2012
    Assignee: GE Healthcare Limited
    Inventor: Alan Peter Clarke
  • Publication number: 20110250522
    Abstract: A stainless steel member for a separator of a solid polymer fuel cell which has excellent cell properties with little deterioration in performance over long periods of operation without worsening of the corrosion resistance of a stainless steel separator is provided. A stainless steel member has a stainless steel base metal, and a passive film and electrically conductive precipitates both provided on a surface of the stainless steel base metal. The electrically conductive precipitate penetrates the passive film and includes a substance originating from the stainless steel base metal. An electrically conductive layer comprising a nonmetallic electrically conductive substance is preferably provided on the surface of the passive film, and the electrically conductive layer is preferably electrically connected to the stainless steel base member through the electrically conductive precipitates.
    Type: Application
    Filed: April 6, 2011
    Publication date: October 13, 2011
    Applicant: SUMITOMO METAL INDUSTRIES, LTD
    Inventors: Hideya KAMINAKA, Junko IMAMURA, Akira SEKI, Kouichi TAKEUCHI
  • Publication number: 20110002359
    Abstract: A sensor, in particular for the spatially resolved detection, includes a substrate, at least one micropatterned sensor element having an electric characteristic whose value varies as a function of the temperature, and at least one diaphragm above a cavity, the sensor element being disposed on the underside of the at least one diaphragm, and the sensor element being contacted via connecting lines, which extend within, on top of or underneath the diaphragm. In particular, a plurality of sensor elements may be formed as diode pixels within a monocrystalline layer formed by epitaxy. Suspension springs, which accommodate the individual sensor elements in elastic and insulating fashion, may be formed within the diaphragm.
    Type: Application
    Filed: April 23, 2007
    Publication date: January 6, 2011
    Inventors: Hubert Benzel, Simon Armbruster, Arnim Hoechst, Christoph Schelling, Ando Feyh
  • Publication number: 20100314255
    Abstract: There is provided a substantially permanent stainless steel cathode plate suitable for use in electrorefining of metal cathodes, the cathode being composed of a low-nickel duplex steel or a lower grade “304” steel, wherein operational adherence of an electrodeposition thereon is enabled by altering various qualities of the cathode surface. There is also provided a method of producing the above duplex or Grade 304 cathode plates, such that the desired operational adherence of the deposit upon the plate is not so strong as to prevent the deposit being removed during subsequent handling.
    Type: Application
    Filed: August 24, 2010
    Publication date: December 16, 2010
    Applicant: Xstrata Queensland Limited
    Inventor: Wayne Keith Webb
  • Publication number: 20100075145
    Abstract: Metal-polymer hybrid nanomaterials are provided. The hybrid nanomaterials comprise nanotubes or nanowires and metal layers formed on the inner or outer surfaces of the nanotubes or the outer surfaces of the nanowires. The nanotubes or nanowires include a light-emitting ?-conjugated polymer and the metal layers are composed of a metal whose surface plasmon energy level is close to the energy band gap of the nanotubes or nanowires. Further provided are a method for preparing the hybrid nanomaterials, a method for controlling the optical properties of the hybrid nanomaterials, and an optoelectronic device using the hybrid nanomaterials. Energy transfer and electron transfer based on surface plasmon resonance increases the number of excitons in the conduction band of the nanotubes or nanowires including the light- emitting polymer, resulting in a remarkable increase in the luminescence intensity of the metal-polymer hybrid nanomaterials.
    Type: Application
    Filed: September 16, 2008
    Publication date: March 25, 2010
    Inventors: Jinsoo Joo, Dong-Hyuk Park
  • Patent number: 7670473
    Abstract: The present invention is directed to a top surface of a workpiece surface influencing device and a method of using the same. The top surface of the workpiece surface influencing device is adapted for use in an electrochemical mechanical processing apparatus in which a solution becomes disposed onto a conductive surface of a workpiece and electrochemical mechanical processing of the conductive surface is performed while relative movement and physical contact exists between the top surface and the conductive surface. The top surface comprises a ceramic material that presents a substantially planar contact area to the conductive surface, the ceramic material having a hardness greater than that of the conductive surface. A plurality of channels are formed through the top surface.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: March 2, 2010
    Inventors: Cyprian E. Uzoh, Bulent M. Basol
  • Patent number: 7608538
    Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: October 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Qiang Huang, John P. Hummel, Lubomyr T. Romankiw, Mary B. Rothwell
  • Patent number: 7311811
    Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: December 25, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Homayoun Talieh, Cyprian Uzoh, Bulent M. Basol
  • Patent number: 7273535
    Abstract: A method and apparatus for plating a metal onto a substrate. The apparatus includes a fluid basin configured to contain a plating solution, an anode fluid volume positioned in a lower portion of the fluid basin, a cathode fluid volume positioned in an upper portion of the fluid basin, an ionic membrane positioned to separate the anode fluid volume from the cathode fluid volume, a plating electrode centrally positioned in the anode fluid volume, and a deplating electrode positioned adjacent the plating electrode in the anode fluid volume.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: September 25, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Nicolay Y. Kovarsky, Dmitry Lubomirsky, Yevgeniy (Eugene) Rabinovich
  • Patent number: 7252750
    Abstract: A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: August 7, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Wen Liu, Jung-Chih Tsao, Ke-Wei Chen, Ying-Lang Wang
  • Patent number: 7025860
    Abstract: An apparatus for performing an electrochemical process on a metallic surface of a workpiece, comprised of a substantially incompressible workpiece support plate. A platen for supporting the workpiece support plate, has at least one opening coupled to a source of electrolyte for receiving an electrolyte solution therethrough and placing the electrolyte solution in contact with the support plate and workpiece. A first conductive element is coupled to, a first potential and positioned proximate the metallic surface, and the carrier is configured to position the workpiece proximate the support plate.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: April 11, 2006
    Assignee: Novellus Systems, Inc.
    Inventor: Saket Chadda
  • Patent number: 6905588
    Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: June 14, 2005
    Assignee: ASM Nutool, Inc.
    Inventors: Cyprian Emeka Uzoh, Homayoun Talieh, Bulent Basol
  • Patent number: 6887364
    Abstract: A method for manufacturing a multiple walled tube comprising a rolling of a plated metal strip through at least two complete revolutions to form a tube having at least a double wall which has a plated layer on the inside of the tube, said rolling being followed by a heating of the tube to cause the surface of the tube walls, which are in contact with one another, to be brazed and wherein said metal strip is plated on one side, the other side being formed by the steel of the metal strip and wherein said brazing is realized by brazing directly the plated side on the steel.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: May 3, 2005
    Assignee: TI Group Automotive Systems Limited
    Inventors: Lamande Pascal, Pierini Vincenzo, Volvert Albert
  • Patent number: 6884334
    Abstract: The present invention relates to a containment chamber that is used for carrying out multiple processing steps such as depositing on, polishing, etching, modifying, rinsing, cleaning, and drying a surface on the workpiece. In one example of the present invention, the chamber is used to electro chemically mechanically deposit a conductive material on a semiconductor wafer. The same containment chamber can then be used to rinse and clean the same wafer. As a result, the present invention eliminates the need for separate processing stations for depositing the conductive material and cleaning the wafer. Thus, with the present invention, costs and physical space are reduced while providing an efficient apparatus and method for carrying out multiple processes on the wafer surface using a containment chamber.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: April 26, 2005
    Assignee: ASM NuTool, Inc.
    Inventors: Konstantin Volodarsky, Boguslaw A. Nigorski, Rimma Volodarsky, Douglas W. Young, Cyprian Uzoh, Homayoun Talieh
  • Patent number: 6881318
    Abstract: A method for depositing a metal on a substrate is provided. The metal is deposited by sequentially applying a electrodeposition pulse followed by an electrodissolution pulse to the substrate. After each electrodissolution pulse an before the next electrodeposition pulse there is provided at least one time interval of zero electrical voltage or current, also known as an “off-time”, between the pulses. The first two electrodeposition pulses should preferably have the same time durations. Thereafter, the time durations of subsequent electrodeposition pulses are gradually decreased to provide a void-free and seam-free deposition of metal in high aspect ratio features.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: April 19, 2005
    Assignee: Applied Materials, Inc.
    Inventors: H. Peter W. Hey, Yezdi Dordi
  • Patent number: 6848977
    Abstract: The present invention provides a polishing pad for electrochemical mechanical polishing of conductive substrate. The pad comprises a plurality of grooves formed in a polishing surface of the polishing pad, the grooves being adapted to facilitate the flow of polishing fluid over the polishing pad. The conductive layers are respectively formed in the grooves and are in electrical communication with each other.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: February 1, 2005
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Lee Melbourne Cook, David B. James, John V. H. Roberts
  • Patent number: 6838149
    Abstract: An abrasive article is described. The article is suitable for the deposition and mechanical polishing of a conductive material, and comprises: a polishing layer having a textured surface comprising a binder and a second surface opposite the textured surface, the polishing layer further comprising a first channel extending therethrough; a backing having a first backing surface and a second backing surface, the first backing surface associated with the second surface of the polishing layer, the backing comprising a second channel coextensive with the first channel and extending through the backing from the first backing surface to the second backing surface; the first channel and the second channel dimensioned with respect to one another so that the textured surface of the polishing layer is outside of a line of sight.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: January 4, 2005
    Assignee: 3M Innovative Properties Company
    Inventor: Paul S. Lugg
  • Publication number: 20040245109
    Abstract: A film carrier tape for mounting electronic devices thereon has a tin-bismuth alloy deposit in which the bismuth content in the deposit is substantially uniform along a thickness direction thereof. The film carrier tape can be produced by plating at least a part of a wiring pattern with a tin-bismuth alloy and washing the tin-bismuth alloy deposit formed by plating with a water-ejecting washing nozzle within 6 seconds after the plating is completed. A plating apparatus for use in the above production includes a washing nozzle for washing the film carrier tape within 6 seconds after the film carrier tape has exited a plating tank.
    Type: Application
    Filed: December 12, 2003
    Publication date: December 9, 2004
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventor: Akira Fujimoto
  • Patent number: 6802955
    Abstract: An electrochemical apparatus is provided which deposits material onto or removes material from the surface of a workpiece. The apparatus comprises a polishing pad and a platen which is in turn comprised of a first conductive layer in contact with the polishing pad and coupled to a first potential, a second conductive layer coupled to a second potential, and a first insulating layer disposed between the first and second conductive layers. At least one electrical contact is positioned within the polishing pad and is electrically coupled to the second conductive layer. A reservoir is provided which places an electrolyte solution in contact with the polishing pad and the workpiece. A carrier positions and/or presses the workpiece against the polishing pad.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: October 12, 2004
    Assignee: Speedfam-Ipec Corporation
    Inventors: Ismail Emesh, Periya Gopalan, Phillip M. Rayer, II, Bentley J. Palmer
  • Patent number: 6793797
    Abstract: A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: September 21, 2004
    Assignee: Taiwan SEmiconductor Manufacturing Co., Ltd
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai, Winston Shue, Mong-Song Liang
  • Publication number: 20040112753
    Abstract: The present invention provides methods of polishing and/or cleaning copper interconnects using bis(perfluoroalkanesulfonyl) imide acids or copper tris(perfluoroalkanesulfonyl) methide acids compositions.
    Type: Application
    Filed: December 16, 2002
    Publication date: June 17, 2004
    Inventors: Susrut Kesari, William M. Lamanna, Michael J. Parent, Lawrence A. Zazzera
  • Patent number: 6706166
    Abstract: A method for improving an electrodeposited metal film uniformity and preventing metal deposition and peeling of deposited metal from an electrode during an electrodeposition and electropolishing process including providing a first anode electrode assembly and a semiconductor wafer plating surface disposed in an electrolyte bath including a plating metal for deposition onto the semiconductor wafer plating surface; providing at least one additional anode electrode assembly including the plating metal disposed peripheral to the first anode electrode assembly for selectively applying the cathodic electrical potential during an electropolishing process; and, periodically alternating between an electrodeposition process and electropolishing process with respect to the semiconductor wafer plating surface such that the plating metal is preferentially plated onto the at least one additional electrode assembly.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: March 16, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai
  • Patent number: 6652726
    Abstract: A method for reducing or avoiding semiconductor wafer peripheral defects and contamination during and following electrodeposition including providing a wafer chuck assembly sealably attached to a back side of a semiconductor wafer leaving an exposed peripheral portion of the back side of the semiconductor wafer the backside parallel to a front side of the semiconductor wafer comprising a process surface; contacting at least the semiconductor process surface with a process solution; and, simultaneously directing a pressurized flow of gas onto the exposed peripheral portion such that the pressurized flow of gas covers the exposed peripheral portion including being radially directed outward toward the periphery of the semiconductor wafer.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: November 25, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventor: Shih-Wei Chou
  • Patent number: 6645549
    Abstract: A process for providing bond enhancement and an etch resist for a printed circuit board is provided. A sheet comprising at least a layer of copper is immerses in a first immersion tin solution comprising a tin metal and a complexing agent in an acidic medium for a time sufficient to deposit a first heavy tin deposit on the sheet. The sheet is then immersed in a second immersion tin solution comprising stannous tin ions and stannic tin ions and a complexing agent in an acidic medium for a time sufficient to deposit a second thin tin deposit on the sheet. The second thin tin deposit has a thickness less than a thickness of the first heavy tin deposit. A rough surface texture providing mechanical adhesion sites results. The board is then treated with a coupling agent, such as silane, for enhanced bonding to a subsequent epoxy or other polymer prepreg. Additionally, the first heavy tin deposit may serve as an etch resist in subsequent fabrication of the provided circuit board.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: November 11, 2003
    Assignee: Parlex Corporation
    Inventors: Darryl J. McKenney, Arthur J. Demaso, Kathy A. Gosselin, Craig S. Wilson
  • Publication number: 20030183530
    Abstract: A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.
    Type: Application
    Filed: March 26, 2002
    Publication date: October 2, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chou, Ming-Hsing Tsai, Winston Shue, Mong-Song Liang
  • Patent number: 6585875
    Abstract: A process for cleaning an electrically conducting surface (3) by arranging for the surface to form the cathode of an electrolytic cell in which the anode (1) is maintained at a DC voltage in excess of 30V and an electrical arc discharge (electro-plasma) is established at the surface of the workpiece by suitable adjustment of the operating parameters, characterized in that the working gap between the anode and the cathode is filled with an electrically conductive medium consisting of a foam (9) comprising a gas/vapor phase and a liquid phase. The process can be adapted for simultaneously coating the metal surface by including ions of the species required to form the coating in the electrically conductive medium.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: July 1, 2003
    Assignee: CAP Technologies, LLC
    Inventor: Danila Vitalievich Ryabkov
  • Patent number: 6582579
    Abstract: The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on a top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: June 24, 2003
    Assignee: NuTool, Inc.
    Inventor: Cyprian Uzoh
  • Patent number: 6551483
    Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: April 22, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan Reid, Robert Contolini
  • Patent number: 6518182
    Abstract: A process of performing via-filling efficiently and by a simple procedure is disclosed. The via-filling process comprises providing a substrate having blind via-holes, making the substrate electrically conductive, and plating the substrate in an acid copper plating bath which comprises the following components (A) to (E): (A) copper sulfate at a concentration of 100-300 g/L, (B) copper sulfate at a concentration of 30-150 g/L, (C) a first component (polymer component) such as polyethylene glycol, polypropylene glycol, and Pluronic surfactants, at a concentration of 10-1000 mg/L, (D) a second component (carrier component) such as sodium sulfoalkyl sulfonates and bis-sulfo organic compounds at a concentration of 0.1-20 mg/L, and (E) a third component (leveler component) such as polyalkylene imines, 1-hydroxyethyl-2-alkyl imidazoline chlorides, auramine and its derivatives at a concentration of 0.05-10 mg/L.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: February 11, 2003
    Assignee: Ebara-Udylite Co., Ltd.
    Inventors: Masami Ishikawa, Hideki Hagiwara, Ryoichi Kimizuka
  • Publication number: 20030019755
    Abstract: A method for depositing a metal on a substrate is provided. The metal is deposited by sequentially applying a electrodeposition pulse followed by an electrodissolution pulse to the substrate. After each electrodissolution pulse an before the next electrodeposition pulse there is provided at least one time interval of zero electrical voltage or current, also known as an “off-time”, between the pulses. The first two electrodeposition pulses should preferably have the same time durations. Thereafter, the time durations of subsequent electrodeposition pulses are gradually decreased to provide a void-free and seam-free deposition of metal in high aspect ratio features.
    Type: Application
    Filed: July 26, 2001
    Publication date: January 30, 2003
    Applicant: Applied Materials, Inc.
    Inventors: H. Peter W. Hey, Yezdi Dordi
  • Patent number: 6355153
    Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: March 12, 2002
    Assignee: Nutool, Inc.
    Inventors: Cyprian Emeka Uzoh, Homayoun Talieh, Bulent Basol
  • Patent number: 6350362
    Abstract: A method and an apparatus are described for regulating the concentration of metal ions in an electrolytic fluid, which is used for the deposition of metal with insoluble anodes and additionally contains compounds of an electrochemically reversible redox system. With the oxidized form of said system, metal is dissolved in an ion generator 1, traversed by the fluid, so that these compounds are thereby reduced. For the deposition of metal, the dissolved metal ions on the item to be treated are reduced. The compounds of the redox system in the reduced form are oxidized again on the insoluble anodes in the electroplating system 13. In order to keep the concentration of the metal ions in the electrolytic fluid constant, at least a portion of the electrolytic fluid, contained in the electroplating system, is conducted through one or a plurality of electrolytic auxiliary cells 6.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: February 26, 2002
    Assignee: Atotech Deutschland GmbH
    Inventors: Jens-Eric Geisler, Ralf-Peter Wachter, Lorenz Kopp, Manfred Maurer
  • Publication number: 20010051211
    Abstract: Embodiments include a manufacturing method and a plating apparatus for film carrier tapes, in which the plating process does not cause hollowed-out portions in a copper foil at end sections of the solder resist or of the adhesive. A plating apparatus 44 is formed from a first plating bath 46, a second plating bath 48 and a transfer path 54. Plating liquid 60 in the first plating bath 46 is set to a liquid temperature level lower than that of the plating liquid 60 in the second plating bath 48. The transfer path 54 is formed from sprockets that can transfer the film carrier tape 20. In the plating apparatus 44 thus constructed, the deposition amount is small in the first plating bath 46, and therefore a plated layer may be uniformly formed on exposed portions. After a plated layer is formed, the film carrier tape 20 is brought in the second plating bath 48 to form a new plated layer over the plated layer that has been formed.
    Type: Application
    Filed: January 27, 2001
    Publication date: December 13, 2001
    Inventor: Toshihiko Kobayashi
  • Patent number: 6279502
    Abstract: A semiconductor device is fabricated by the steps of coating an underlayer formed on a semiconductor substrate with chemically amplified resist, exposing the resist to light, bringing the resist into contact with an alkaline developing solution with applying a magnetic field to the alkaline developing solution for conducting development to form a resist pattern, and etching the underlayer on the semiconductor substrate using the resist pattern as a mask.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: August 28, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsukasa Azuma
  • Patent number: 6176992
    Abstract: The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer. The steps that are used when making this application include applying the conductive material to the predetermined area of the wafer using an electrolyte solution disposed on a surface of the wafer, when the wafer is disposed between a cathode and an anode, and preventing accumulation of the conductive material to areas other than the predetermine area by mechanically polishing the other areas while the conductive material is being applied.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: January 23, 2001
    Assignee: Nutool, Inc.
    Inventor: Homayoun Talieh
  • Patent number: 6143155
    Abstract: Simultaneous non-contact plating and planarizing of copper interconnections in semiconductor wafer manufacturing is performed by providing relative motion between a bipolar electrode and a metallized surface of a semiconductor wafer without necessary physical contact with the wafer or direct electrical connection thereto.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: November 7, 2000
    Assignee: SpeedFam IPEC Corp.
    Inventors: John A. Adams, Gerald A. Krulik, Everett D. Smith
  • Patent number: 6132586
    Abstract: Plating of metal interconnections in semiconductor wafer manufacturing is performed by providing relative motion between a bipolar electrode assembly a single metallized surface of a semiconductor wafer without necessary physical contact with the wafer or direct electrical connection thereto.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: October 17, 2000
    Assignee: Integrated Process Equipment Corporation
    Inventors: John A. Adams, Gerald A. Krulik, Everett D. Smith
  • Patent number: 5958604
    Abstract: An electrolytic process for metal-coating the pre-cleaned surface of a workpiece of an electrically conducting material, which process comprises:i) providing an electrolytic cell with a cathode comprising the workpiece and an anode comprising the metal for metal-coating of the surface of the workpiece;ii) introducing an electrolyte into the zone created between the anode and the cathode by causing it to flow under pressure through at least one opening in the anode impinge on the cathode; andiii) applying a voltage between the anode and the cathode and operating in a regime in which the electrical current decreases or remains substantially constant with increase in the voltage applied between the anode and the cathode, and in a regime in which discrete gas bubbles are present on the surface of the workpiece during treatment.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: September 28, 1999
    Assignee: Metal Technology, Inc.
    Inventors: Vitalig M. Riabkov, Valerij L. Steblianko
  • Patent number: 5700366
    Abstract: An electrolytic process for simultaneously cleaning and metal-coating the surface of a workpiece of an electrically conducting material, which process comprises: i) providing an electrolytic cell with a cathode comprising the surface of the workpiece and an anode comprising the metal for metal-coating of the surface of the workpiece; ii) introducing an electrolyte into the zone created between the anode and the cathode by causing it to flow under pressure through at least one opening in the anode and thereby impinge on the cathode; and iii) applying a voltage between the anode and the cathode and operating in a regime in which the electrical current decreases or remains substantially constant with increase in the voltage applied between the anode and the cathode, and in a regime in which discrete gas bubbles are present on the surface of the workpiece during treatment.
    Type: Grant
    Filed: September 3, 1996
    Date of Patent: December 23, 1997
    Assignee: Metal Technology, Inc.
    Inventors: Valerij Leontievich Steblianko, Vitalij Makrovich Riabkov
  • Patent number: 5662788
    Abstract: A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: September 2, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu Sandhu, Chris Chang Yu
  • Patent number: 5269904
    Abstract: The invention is a single-bath electrolytic de-oxidation and anodization process in which a workpiece surface such as an aluminum surface is electrolytically de-oxidized and then anodized to form an adhesive oxide layer in the same electrolytic chemical bath without removing the workpiece from the bath. Upon completion of the anodization step, the piece is rinsed in a water bath. The invention further includes recirculating the electrolytic bath through a filter to suppress contaminant levels in the bath to prevent metal ion or organic contaminants from the de-oxidation step from compromising the integrity of the anodization step.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: December 14, 1993
    Assignee: Northrop Corporation
    Inventors: Calvin C. Fong, Rimas Viktora