Forming Or Treating Josephson Junction Article Patents (Class 216/3)
  • Patent number: 11342492
    Abstract: Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include a non-superconducting structure having a hollow region. A first superconducting structure may be disposed inside the hollow region of the non-superconducting structure, and a second superconducting structure may be disposed around the non-superconducting structure outside the hollow region.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 24, 2022
    Assignee: Synopsys, Inc.
    Inventors: Jamil Kawa, Victor Moroz, Stephen Robert Whiteley
  • Patent number: 11289637
    Abstract: A qubit includes a substrate, and a first capacitor structure having a lower portion formed on a surface of the substrate and at least one first raised portion extending above the surface of the substrate. The qubit further includes a second capacitor structure having a lower portion formed on the surface of the substrate and at least one second raised portion extending above the surface of the substrate. The first capacitor structure and the second capacitor structure are formed of a superconducting material. The qubit further includes a junction between the first capacitor structure and the second capacitor structure. The junction is disposed at a predetermined distance from the surface of the substrate and has a first end in contact with the first raised portion and a second end in contact with the second raised portion.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 29, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vivekananda P. Adiga, Martin O. Sandberg, Jerry M. Chow, Hanhee Paik
  • Patent number: 10665769
    Abstract: Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Roman Caudillo, Zachary R. Yoscovits, Lester Lampert, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, James S. Clarke
  • Patent number: 10552758
    Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10516248
    Abstract: A system includes a substrate, a high-temperature superconductor compound film disposed on the substrate, an array of superconducting regions formed within the film, a plurality of Josephson junctions formed within the film, where each Josephson junction of the plurality of Josephson junctions is formed between adjacent superconducting regions within the array of superconducting regions, and a voltage source connected to the array of superconducting regions. The plurality of Josephson junctions are separated by a distance such that they emit coherent radiation in the terahertz frequency range responsive to a voltage applied to the array of superconducting regions.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 24, 2019
    Assignee: United States of America as represented by Secretary of the Navy
    Inventors: Benjamin J. Taylor, Teresa H. Emery
  • Patent number: 10445651
    Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jared Barney Hertzberg, Werner A. Rausch, Sami Rosenblatt, Rasit O. Topaloglu
  • Patent number: 10388715
    Abstract: Provided is a display apparatus capable of reducing generation of defects during manufacturing of the display apparatus or while in use after being manufactured. The display apparatus includes a substrate including a bending area between a first area and a second area, the substrate being bent in the bending area about a bending axis; an inorganic insulating layer over the substrate and including a first feature that is either a first opening or a first groove, the first feature positioned to correspond to the bending area; and an organic material layer at least partially filling the first feature, and including a second feature that is a second opening or a second groove, the second feature extending along an edge of the substrate.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 20, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yoonsun Choi, Hyunchul Kim
  • Patent number: 10262275
    Abstract: A cascading selective microwave switch (cascade) includes a set of Josephson devices, each Josephson device in the set having a corresponding operating bandwidth of microwave frequencies, wherein different operating bandwidths have different corresponding center frequencies. A series coupling is formed between first Josephson device from the set and an nth Josephson device from the set. the series coupling causes the first Josephson device in an open state to reflect back to an input port of the first Josephson device a signal of a first frequency from a frequency multiplexed microwave signal (multiplexed signal) and the nth Josephson device in a closed state to transmit a signal of an nth frequency in the multiplexed signal from an input port of the nth Josephson device to an output port of the nth Josephson device.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Baleegh Abdo
  • Patent number: 10205081
    Abstract: A device and method for converting magnetic flux to voltage uses a Fraunhofer pattern of a 1D array of long Josephson junctions. The 1D array of Josephson junctions may include from 1 to 109 junctions formed in a planar geometry with a bridge width within the range of 4-10 ?m.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: February 12, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Shane A. Cybart, Travis J. Wong, Robert C. Dynes, Ethan Y. Cho
  • Patent number: 10008655
    Abstract: A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, George A Keefe, Chad T. Rigetti, Mary E. Rothwell
  • Patent number: 10003005
    Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact through the second dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with the first contact, and forming a second contact through the second dielectric layer to a second end of the base electrode.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: June 19, 2018
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Christopher F. Kirby, Michael Rennie, Aurelius L. Graninger
  • Patent number: 9929334
    Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Ryan M. Martin, Jeffrey W. Sleight
  • Patent number: 9859684
    Abstract: A grating device includes a support substrate, an optical material layer 11 disposed on the support substrate and having a thickness of 0.5 ?m or more and 3.0 ?m or less, a ridge optical waveguide formed by a pair of ridge grooves in the optical material layer and having a light-receiving surface for receiving a semiconductor laser light and a light-emitting surface for emitting light having a desired wavelength, a Bragg grating 12 comprising convexes and concaves formed in the ridge optical waveguide, and a propagating portion 13 disposed between the light-receiving surface and the Bragg grating. The relationships represented by the following Formulas (1) to (4) are satisfied: 0.8 nm???G?6.0 nm??(1); 10 ?m?Lb?300 ?m??(2); 20 nm?td?250 nm??(3); and nb?1.8??(4).
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 2, 2018
    Assignee: NGK INSULATORS, LTD.
    Inventors: Jungo Kondo, Shoichiro Yamaguchi, Tetsuya Ejiri, Keiichiro Asai, Naotake Okada
  • Patent number: 9716219
    Abstract: A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, George A. Keefe, Chad T. Rigetti, Mary E. Rothwell
  • Patent number: 9177814
    Abstract: A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, George A. Keefe, Chad T. Rigetti, Mary E. Rothwell
  • Patent number: 9031684
    Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Han Cheng, Chin-Hsiang Lin, Chi-Ming Yang, Chun-Lin Chang, Chih-Hong Hwang
  • Patent number: 8951808
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap contact connector.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: February 10, 2015
    Assignee: D-Wave Systems Inc.
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Patent number: 8431338
    Abstract: A self-directed and self-assembled nanomedicine of quantized conductive junction and its preparation process are introduced. In the present disclosure, bio-organic medicine proteins are prepared into a quantized conductive junction with a nanostructure quantum dot and a polymer monolayer on an inorganic silicon surface by seven cooperative modes; and the preparation process of this inorganic-organic-biological hetero-polymer nano-structure component with free radical electrons, aromatic hetercycle structures, bio-fluorescence, and redox bioactivity is consist of making unitary, binary, ternary, and/or quaternary liquid biochemical medicines ingredients of an antioxidase antioxidant, a ?-adrenergic receptor agonist, a P2-purinergic receptor agonist, and/or a phenylalkylamine calcium channel blocker into a solid state quantized conductance junctions using L16(2)15 and L9(3)4 orthogonal protocol.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: April 30, 2013
    Assignee: Zhonshan Hospital, Fudan University
    Inventor: Yan Fang
  • Publication number: 20110287944
    Abstract: Methods of forming superconducting devices are disclosed. In one embodiment, the method can comprise depositing a protective barrier layer over a superconducting material layer, curing the protective barrier layer, depositing a photoresist material layer over the protective barrier layer and irradiating and developing the photoresist material layer to form an opening pattern in the photoresist material layer. The method can further comprise etching the protective barrier layer to form openings in the protective barrier layer based on the opening pattern, etching the superconductor material layer based on the openings in the protective barrier layer to form openings in the superconductor material layer that define a first set of superconductor material raised portins and stripping the photoresist material layer and the protective barrier layer.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 24, 2011
    Inventors: Erica Folk, Patrick B. Shea, Andrew C. Loyd
  • Patent number: 7879510
    Abstract: A method for etching quartz is provided herein. In one embodiment, a method of etching quartz includes providing a filmstack in an etching chamber, the filmstack having a quartz layer partially exposed through a patterned layer, providing at least one fluorocarbon process gas to a processing chamber, biasing a quartz layer disposed on a substrate support in the processing chamber with a plurality of power pulses less than 600 Watts and etching the quartz layer through a patterned mask. The method for etching quartz described herein is particularly suitable for fabricating photomasks having etched quartz portions.
    Type: Grant
    Filed: January 8, 2005
    Date of Patent: February 1, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Scott Alan Anderson, Ajay Kumar
  • Patent number: 6803637
    Abstract: A micromechanical component having a substrate made from a substrate material having a first doping type, a micromechanical functional structure provided in the substrate and a cover layer to at least partially cover the micromechanical functional structure. The micromechanical functional structure has zones made from the substrate material having a second doping type, the zones being at least partially surrounded by a cavity, and the cover layer has a porous layer made from the substrate material.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: October 12, 2004
    Assignee: Robert Bosch GmbH
    Inventors: Hubert Benzel, Heribert Weber, Hans Artmann, Frank Schaefer
  • Publication number: 20040020893
    Abstract: A method of producing an optical grating component including only a single continuous grating field formed in a longitudinal waveguide rib, the method including the steps of defining a grating in an optic chip including a portion thereof through which the longitudinal waveguide rib is to extend, and then defining the lateral edges of the longitudinal rib in the optic chip, whereby any portion of the grating extending laterally beyond the lateral width of the rib is removed in the step of defining the lateral edges of the rib leaving a single continuous grating field that has straight lateral grating boundaries that are laterally aligned with the straight lateral edges of the rib.
    Type: Application
    Filed: January 14, 2003
    Publication date: February 5, 2004
    Applicant: BOOKHAM TECHNOLOGY, PLC.
    Inventors: John Paul Drake, Andrew Tomlinson, Abdel Karim Zekak
  • Patent number: 6605225
    Abstract: A three-dimensional element is fabricated from a high-temperature superconductor. The method and apparatus can fabricate, for example, a single-electron tunnel device or an intrinsic Josephson device which utilize the layer structure peculiar to the high-temperature superconductor, with machining from the side surface of a monocrystal or thin film. In the focused-ion beam etching, a substrate holder which is rotatable about 360°, is rotated, at the minimum, through an angle of about 90°, and the thin film or monocrystal on the substrate is etched from the side surface thereof so as to fabricate the element. After the thin film or monocrystal is machined from above by means of an focused-ion beam to thereby form a bridge having a junction length, the sample is rotated by about 90° (270°). Subsequently, a multi-layer current path layer is formed through side-surface machining. The junction length is accurately controlled through measurement of the current path length from an image display.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: August 12, 2003
    Assignee: Japan Science and Technology Corporation
    Inventors: Tsutomu Yamashita, Sang-Jae Kim
  • Patent number: 6511918
    Abstract: The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas atmosphere at a temperature of over 130° C. and in the presence of at least one halogen compound and at least one oxidizing agent. The concentration of the oxidizing agent is thereby set higher than the concentration of the halogen compound.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: January 28, 2003
    Assignee: Infineon Technologies AG
    Inventors: Stephan Wege, Kerstin Krahl
  • Publication number: 20020096487
    Abstract: A method comprising etching a material under plasma etching conditions using an etching composition which has a GWP of no greater than about 3000 and which comprises at least one etchant compound having a formula selected from the group consisting of F—CO—[(CR1R2)m—CO]n−F and F—CO—R3—CO—F, and wherein:
    Type: Application
    Filed: December 31, 1997
    Publication date: July 25, 2002
    Inventors: TIMOTHY R. DEMMIN, MATTHEW H. LULY, MOHAMMED A. FATHIMULLA
  • Patent number: 6358857
    Abstract: In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: March 19, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Daryl C. New
  • Patent number: 6339047
    Abstract: Methods of treating superconducting composites to enhance their wettability in solder, and composites having enhanced wettability. It has been found that wettability can be substantially enhanced by stripping a thin layer off the surface of the composite before incorporating it into a laminated component. This layer can be stripped, for example, by chemically etching the composite, for example in a solution of nitric acid and ammonium bifluoride.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: January 15, 2002
    Assignee: American Semiconductor Corp.
    Inventors: Craig J. Christopherson, David M. Olen, Deborah L. Ouellette, Thomas De Santos, Eric R. Podtburg, Sy-Jenq Loong
  • Patent number: 6207067
    Abstract: A method for fabricating an oxide superconducting device includes the steps of: forming a V-shaped groove on a substrate by a converging ion beam and forming a barrier with reduced superconductivity on the oxide superconducting thin-film on the groove to form a Josephson Junction, wherein the irradiation ion amount of the converging ion beam is varied according to the position of the beam within the groove in such a manner that an inclination angle of the inclined portion of the substrate is fixed. An oxide superconducting device (a Josephson Junction device) having a high degree of flexibility in arrangement and with high reproducibility, and having a high degree of uniformity is provided.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: March 27, 2001
    Assignees: Mitsubishi Denki Kabushiki Kaisha, International Superconductivity Technology Center
    Inventors: Naoki Yutani, Katsumi Suzuki, Youichi Enomoto, Jian-Guo Wen
  • Patent number: 6110392
    Abstract: The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: August 29, 2000
    Assignee: TRW Inc.
    Inventors: George L. Kerber, Michael Leung
  • Patent number: 5981443
    Abstract: A bicrystal substrate is formed by joining end faces of a first single crystal substrate and a second single crystal substrate, the end faces having different crystal orientations. A high critical temperature superconducting thin film is then epitaxially formed on the bicrystal substrate. The superconducting thin film is etched so as to form a first superconducting electrode on the first single crystal substrate, a second superconducting electrode on the second single crystal substrate, and a superconducting bridge across a joint between the first and second single crystal substrates and connecting the first electrode and the second electrode. A conductive film is formed on the superconducting bridge by vapor deposition, and is then etched so as to form a weak link on a part of the superconducting bridge over the joint.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: November 9, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Zhongmin Wen
  • Patent number: 5599465
    Abstract: A method is provided for producing superconducting Josephson devices using a chemical etching solution which comprises forming a mask on a predetermined portion of a MgO substrate, and immersing the MgO substrate having the mask in an aqueous acid solution in which the volume ratio of phosphoric acid to sulfuric acid is approximately 10:1 or more, so as to form a step at the boundary between the masked region and the unmasked region.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: February 4, 1997
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chan H. Park, Jin P. Hong
  • Patent number: 5580466
    Abstract: An object of the present invention is to, in methods of processing metal plates and lead frames, enable workpieces to be finely processed into a satisfactory configuration with high dimensional accuracy without suffering the effect of heat produced under irradiation of a laser beam. According to the present invention, resist films (1) are first coated on both surfaces of a metal plate (1), and a laser beam (202) is then irradiated to the metal plate (101) from surfaces of the resist films (1) to form a multiplicity of discontinuous through holes (3) in line, while leaving joints (6) as not-processed portions between the adjacent through holes (3). Openings (2) formed in each resist film (1) by the laser cutting are joined with each other to serve as an etching pattern. Next, etching is carried out to etch side walls (6) defining the through holes and also to remove the joints (6), thereby interconnecting the through holes (3) formed in line to form a gap (303a) of a desired shape.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: December 3, 1996
    Assignee: Hitachi Construction Machinery Co., Ltd.
    Inventors: Nobuhiko Tada, Naoki Miyanagi, Yoshiaki Shimomura, Shigeyuki Sakurai, Yoshinari Nagano
  • Patent number: 5571778
    Abstract: A superconductor junction material is disclosed which comprises a substrate of a single crystal, and at least flux flow element, and optionally at least one Josephson junction element, provided on the surface, each of the flux flow and Josephson junction elements being formed of a superconducting oxide layer having a weak link. The flux flow and Josephson junction elements are prepared by vacuum deposition at different oxygen partial pressures.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: November 5, 1996
    Assignees: Superconductivity Research Laboratory of International Superconductivity Technology Center, Sharp Corporation
    Inventors: Manabu Fujimoto, Katsumi Suzuki, Youichi Enomoto, Shoji Tanaka
  • Patent number: 5560836
    Abstract: The present invention relates to a method or forming a step on a deposition surface of a substrate for depositing it thin film on it. The method comprises steps of etching a portion of the deposition surface of the substrate and conducting heat treatment of the substrate so as to recover crystallinity of the etched surface. The method can comprise steps of etching a portion of the deposition surface of the substrate and further etching the etched portion of the deposition surface of the substrate slightly so as to remove a degraded surface.
    Type: Grant
    Filed: November 9, 1994
    Date of Patent: October 1, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Tatsuoki Nagaishi
  • Patent number: 5550101
    Abstract: A superconducting magnetoresistive element has superconducting portions having a high critical current density and weak-coupling portions having a low critical current density. The superconducting portions and weak-coupling portions are alternately arranged and connected in series. The superconducting magnetoresistive element is fabricated, for example, by forming semiconductor films at a plurality of sites on a substrate in a manner that the semiconductor films are spaced from each other, then forming a superconducting thin film all over the substrate and processing the superconducting thin film into a line pattern which passes over the plurality of semiconductor films, and heat-treating the substrate to diffuse a constituent element of the semiconductor films in the superconducting thin film. Portions of the superconducting thin film overlying the semiconductor films become the weak-coupling portions and the rest portions of the superconducting thin film become the superconducting portions.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: August 27, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaya Nagata, Hideo Nojima, Masayoshi Koba
  • Patent number: 5462762
    Abstract: A method of fabricating a superconducting quantum interference device (DC-SQUID) constructed from short weak links with untrafine wires. The method comprises the following steps: successive forming a niobium nitride film and a silicon nitride film on a substrate; oblique etching of the niobium nitride film and said silicon nitride film with respect to the substrate by a reactive ion etching process using a mixture of oxygen and CF.sub.4 gases to form an olique edge; and successive forming a barrier thin film and a counterelectrode of niobium on the said edge. The short weak links wire fabricated by field evaporation technique. The counterelectrode material were field-evaporated and formed the conductive paths in the pinholes in the insulating thin film.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: October 31, 1995
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yoshio Onuma, Katsuyoshi Hamasaki
  • Patent number: 5462919
    Abstract: For manufacturing a superconducting thin film having at least one non-superconducting region at and near its surface portion, an oxide superconductor thin film is formed on a surface of the substrate. The oxide superconductor thin film is heated in high vacuum environment so that oxygen of the oxide superconductor crystals escapes from the surface of the oxide superconductor thin film and a surface portion of the oxide superconductor thin film having a substantial thickness changes into non-superconducting layer of a compound oxide which is composed of the same constituent elements as those of the oxide superconductor but includes the oxygen amount less than that of the oxide superconductor and a thin superconducting channel is formed under the non-superconducting layer.
    Type: Grant
    Filed: February 18, 1994
    Date of Patent: October 31, 1995
    Assignee: Sumitomo Electric Industries,Ltd.
    Inventors: So Tanaka, Michitomo Iiyama
  • Patent number: 5446016
    Abstract: A method for forming a patterned oxide superconductor thin film on a substrate comprises steps of forming a metal or semi-metal layer on a portion of the substrate, on which the oxide superconductor thin film will be formed, forming a layer of a material including silicon on a portion of the substrate, on which an insulating layer will be formed, removing the metal or semi-metal layer and depositing an oxide superconductor thin film over the substrate.
    Type: Grant
    Filed: February 15, 1994
    Date of Patent: August 29, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: So Tanaka, Takao Nakamura, Michitomo Iiyama
  • Patent number: 5418213
    Abstract: A method for forming an oxide superconductor thin film having different thickness portions, in a process for manufacturing a superconductor device, includes the step of forming an oxide superconductor thin film having a uniform thickness on a substrates. A portion of the oxide superconductor thin film is etch-removed so that the oxide superconductor thin film has a thin thickness portion. Preferably, before the etching, the oxide superconductor thin film is coated with a metal layer, and the oxide superconductor thin film and the metal layer are etched together by means of a physical dry etching process.
    Type: Grant
    Filed: May 18, 1993
    Date of Patent: May 23, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Saburo Tanaka, Hideo Itozaki, Shuji Yazu
  • Patent number: 5411937
    Abstract: A novel method for fabricating nanometer geometry electronic devices is described. Such Josephson junctions can be accurately and reproducibly manufactured employing photolithographic and direct write electron beam lithography techniques in combination with aqueous etchants. In particular, a method is described for manufacturing planar Josephson junctions from high temperature superconducting material.
    Type: Grant
    Filed: May 17, 1993
    Date of Patent: May 2, 1995
    Assignee: Sandia Corporation
    Inventors: Joel R. Wendt, Thomas A. Plut, Jon S. Martens