Abstract: A light detection device includes an APD, a plurality of temperature compensation diodes, and a circuit unit. The plurality of temperature compensation diodes have different breakdown voltages lower than a breakdown voltage of the APD. The circuit unit puts any one of the plurality of temperature compensation diodes into a breakdown state. The circuit unit includes a plurality of terminals and a terminal. The plurality of terminals are respectively connected to electrodes of the mutually different temperature compensation diodes. The terminal is electrically connected to the APD and electrodes of the temperature compensation diodes.

Abstract: A device includes a number of irreversibly programmable memory points. Each irreversibly programmable memory point includes a first semiconductor zone and a gate located on the first zone. A conductive area defines the gates of the memory points. First and second semiconductor areas are respectively located on either side of a vertical alignment with the conductive area. The first zones are alternately in contact with the first and second areas.

Abstract: A semiconductor device contains a Zener-triggered transistor having a Zener diode vertically integrated in a first current node of the Zener-triggered transistor. The first current node includes an n-type semiconductor material contacting a p-type semiconductor material in a substrate. The Zener diode includes an n-type cathode contacting the first current node, and a p-type anode contacting the n-type cathode and contacting the p-type semiconductor material. The semiconductor device may be formed using an implant mask, with an opening for the Zener diode. Boron and arsenic are implanted into the substrate in an area exposed by the opening in the implant mask. The substrate is subsequently heated to diffuse and activate the implanted boron and arsenic. The Zener-triggered transistor may be used in an ESD circuit or a snubber circuit.

Abstract: Methods of forming a portion of an integrated circuit include forming a patterned mask having an opening and exposing a surface of a semiconductor material, forming a first doped region at a first level of the semiconductor material through the opening, and isotropically removing a portion of the patterned mask to increase a width of the opening. The methods further include forming a second doped region at a second level of the semiconductor region through the opening after isotropically removing the portion of the patterned mask, wherein the second level is closer to the surface of the semiconductor material than the first level.

Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

Abstract: Disclosed are a semiconductor structure of an ESD protection device with low capacitance and a method for manufacturing the same. The method for manufacturing a semiconductor structure of an ESD protection device, comprising: forming a buried layer with a first doping type and a buried layer with a second doping type in a first region and a second region at a top surface of a semiconductor substrate with a first doping type, respectively; forming an epitaxial layer with a second doping type on the buried layer with the first doping type and the buried layer with the second doping type, wherein the buried layer with the first doping type and the buried layer with the second doping type are buried between the semiconductor substrate and the epitaxial layer, a first doped region with a first doping type is formed at a top of a third region on the buried layer with the second doping type located on the epitaxial layer.

Abstract: Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a leadframe; a semiconductor die coupled to the leadframe; a conductor comprising a metal layer on the semiconductor die, the conductor comprising at least one bridge portion and at least two slots, a first slot having a first tip and a second slot having a second tip, a distance between the first and second tips defining a width of one of the at least one bridge portion, wherein the conductor is separated from the leadframe by at least a thickness of the semiconductor die, and the thickness is about 0.2 millimeters (mm) to about 0.7 mm; and at least one magnetic sensor element arranged on the die relative to and spaced apart from the one of the at least one bridge portion and more proximate the conductor than the leadframe.

Abstract: A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film or a low conductive film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of the insulating film or the low conductive film. The conducting elements can vary in at least one of composition, doping, conductivity, size, thickness, shape, and distance from the device channel along a lateral length of the insulating film or the low conductive film, or in a direction that is perpendicular to the lateral length.

Abstract: This application provides a method of manufacturing an n-p-n nitride-semiconductor light-emitting device which includes a current confinement region (A) using a buried tunnel junction layer and in which a favorable luminous efficacy can be obtained and to provide the n-p-n nitride-semiconductor light-emitting device. The p-type activation of a p-type GaN crystal layer stacked below a tunnel junction layer is performed in an intermediate phase of a manufacturing process in which the p-type GaN crystal layer is exposed to atmosphere gas with the tunnel junction layer partially removed, before the tunnel junction layer is buried in an n-type GaN crystal layer. In the intermediate phase of the manufacturing process in which the p-type GaN crystal layer is exposed, p-type activation is efficiently performed on the p-type GaN crystal layer, and a p-type GaN crystal layer with low electric resistance can be obtained.

Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.

Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.

Abstract: The present invention discloses a short-gate tunneling field effect transistor having a non-uniformly doped vertical channel and a fabrication method thereof. The short-gate tunneling field effect transistor has a vertical channel and the channel region is doped in such a slowly-varied and non-uniform manner that a doping concentration in the channel region appears as a Gaussian distribution along a vertical direction and the doping concentration in the channel near the drain region is higher while the doping concentration in the channel near the source region is lower; and double control gates are formed at both sides of the vertical channel and the control gates form an L-shaped short-gate structure, so that a gate underlapped region is formed in the channel near the drain region, and a gate overlapped region is formed at the source region.

Abstract: Diode string configurations are provided that employ one or more guard bars (GBARS) positioned adjacent an end diode structure of a diode string to create a parasitic silicon-controlled rectifier (SCR) coupling between the end diode structure and the guard bar/s that operates to discharge current of an ESD event through a lateral parasitic bipolar transistor of the SCR and away from the individual diodes of the diode string. One or more of the disclosed guard bars may be positioned adjacent to a diode on a first end of a diode string to create a lateral SCR coupling for ESD discharge away from all of the diodes in the diode string without requiring positioning of a last diode on an opposite end of the same diode string adjacent the first terminal diode.

Abstract: Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different.

Abstract: Provided is an epitaxial silicon wafer free of epitaxial defects caused by dislocation clusters and COPs with reduced metal contamination achieved by higher gettering capability and a method of producing the epitaxial wafer. A method of producing an epitaxial silicon wafer includes a first step of irradiating a silicon wafer free of dislocation clusters and COPs with cluster ions to form a modifying layer formed from a constituent element of the cluster ions in a surface portion of the silicon wafer; and a second step of forming an epitaxial layer on the modifying layer of the silicon wafer.

Abstract: A chip diode includes a plurality of diode cells formed on a semiconductor substrate, each having a diode junction region; and parallel connection portions provided on the substrate to connect the diode cells in parallel and including a first electrode formed in one side of the substrate and having at least two extending portions extending only to another side of the substrate. At least two diode junction regions are formed along each of the extending portions. At least two extending portions are formed to have line symmetry and at least four diode junction regions are formed to have point symmetry and line symmetry in a plane view. A space is formed in the center of at least the four diode junction regions. Fluctuations in characteristics of the diode are suppressed even when a large stress is applied to a pad of a diode package for electrical connection with the exterior.

Abstract: A bidirectional Zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode.

Abstract: ESD protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base well region having a first conductivity type, a collector region of the opposite conductivity type, and a second base well region having a dopant concentration greater than the first base well region, and a portion of the second base well region is disposed between the first base well region and the collector region. A third base well region with a different dopant concentration is disposed between the collector region and the second base well region. At least a portion of the first base well region is disposed between a base contact region and an emitter region within the second base well region.

Abstract: A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.

Abstract: According to one embodiment, a semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes a first second conductivity type region, and a second second conductivity type region. The first second conductivity type region is provided between the first trenches. The second second conductivity type region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer.

Abstract: A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor.

Abstract: An asymmetrical bidirectional protection component formed in a semiconductor substrate of a first conductivity type, including: a first implanted area of the first conductivity type; a first epitaxial layer of the second conductivity type on the substrate and the first implanted area; a second epitaxial layer of the second conductivity type on the first epitaxial layer, the second layer having a doping level different from that of the first layer; a second area of the first conductivity type on the outer surface of the epitaxial layer, opposite to the first area; a first metallization covering the entire lower surface of the substrate; and a second metallization covering the second area.

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor device may include a semiconductor element disposed on a substrate and including an insulating layer and a gate electrode, a doped region having a first conductivity-type on the substrate, a conductive interconnection electrically connected to the gate electrode, and a first contact plug having a second conductivity-type and electrically connecting the conductive interconnection and the doped region to each other and constituting a Zener diode by junction with the doped region.

Abstract: Monolithic integration of high-frequency GaN-HEMTs and GaN-Schottky diodes. The integrated HEMTs/Schottky diodes are realized using an epitaxial structure and a fabrication process which reduces fabrication cost. Since the disclosed process preferably uses self-aligned technology, both devices show extremely high-frequency performance by minimizing device parasitic resistances and capacitances. Furthermore, since the Schottky contact of diodes is formed by making a direct contact of an anode metal to the 2DEG channel the resulting structure minimizes an intrinsic junction capacitance due to the very thin contact area size. The low resistance of high-mobility 2DEG channel and a low contact resistance realized by a n+GaN ohmic regrowth layer reduce a series resistance of diodes as well as access resistance of the HEMT.

Abstract: A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a solvent in the solution is volatilized until the solution reaches the anode or cathode; and the remaining light emitting material is deposited on the anode or cathode to form a light emitting layer. A burning step for reduction in film thickness is not required after the solution application. Therefore, the manufacturing method, which requires low cost and is easy but which has high throughput, can be provided.

Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.

Abstract: A submount for a semiconductor light emitting device includes a semiconductor substrate having a cavity therein configured to receive the light emitting device. A first bond pad is positioned in the cavity to couple to a first node of a light emitting device received in the cavity. A second bond pad is positioned in the cavity to couple to a second node of a light emitting device positioned therein. Light emitting devices including a solid wavelength conversion member and methods for forming the same are also provided.

Abstract: A method of assembling a packaged integrated circuit (IC) includes printing a viscous dielectric polymerizable material onto a die pad of a leadframe having metal terminals positioned outside the die pad. An IC die having a top side including a plurality of bond pads is placed with its bottom side onto the viscous dielectric polymerizable material. Bond wires are wire bonded between the plurality of bond pads and the metal terminals of the leadframe.

Abstract: A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.

Abstract: According to an embodiment, a semiconductor device includes a base including a mounting portion having conductivity, and a terminal insulated from the mounting portion. The device also includes a semiconductor element provided on the mounting portion and having a first face and a second face opposite to the first face, the semiconductor element having an electrode electrically connected to the terminal on the first face, and contacting the mounting portion via the second face, and a resistance element electrically connecting the mounting portion to the terminal. A resistance value of the resistance element is greater than a reciprocal of the product ?C, wherein C is a capacitance value between the mounting portion and the terminal, and ? is an angular frequency of an electrical signal output from the semiconductor element.

Abstract: A light emitting diode package includes an electrically insulated base, first and second electrodes, an LED chip, a voltage stabilizing module, and an encapsulative layer. The base has a first surface and an opposite second surface. The first and second electrodes are formed on the first surface of the base. The LED chip is electrically connected to the first and second electrodes. The voltage stabilizing module is formed on the first surface of the base, positioned between and electrically connected to the first and second electrodes. The voltage stabilizing module connects to the LED chip in reverse parallel and has a polarity arranged opposite to that of the LED chip. The voltage stabilizing module has an annular shape and encircles the first electrode. The encapsulative layer is formed on the base and covers the LED chip.

Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.

Abstract: A semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes first and second regions. The first region is provided between the first trenches. The second region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second region has less second conductivity type impurities than the first region.

Abstract: A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.

Abstract: A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, radio-frequency shielding structures may be formed over the components. The radio-frequency shielding structures may be formed from a layer of metallic paint. Components may be covered by a layer of dielectric. Channels may be formed in the dielectric between blocks of circuitry. The metallic paint may be used to coat the surfaces of the dielectric and to fill the channels. Openings may be formed in the surface of the metallic paint to separate radio-frequency shields from each other. Conductive traces on the surface of the printed circuit board may be used in connecting the metallic paint layer to internal printed circuit board traces.

Abstract: Disclosed herein is a metal e-fuse device that employs an intermetallic compound programming mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines.

Abstract: Example methods and apparatus for Antimonide-based backward diode millimeter-wave detectors are disclosed. A disclosed example backward diode includes a cathode layer adjacent to a first side of a non-uniform doping profile, and an Antimonide tunnel barrier layer adjacent to a second side of the spacer layer.

Abstract: A light emitting device having a vertical structure, a package thereof and a method for manufacturing the same, which are capable of damping impact generated in a substrate separation process, and achieving an improvement in mass productivity, are disclosed. The method includes growing a semiconductor layer having a multilayer structure over a substrate, forming a first electrode on the semiconductor layer, separating the substrate including the grown semiconductor layer into unit devices, bonding each of the separated unit devices on a sub-mount, separating the substrate from the semiconductor layer, and forming a second electrode on a surface of the semiconductor layer exposed in accordance with the separation of the substrate.

Abstract: A resistive memory comprises a tunnel barrier. The tunnel barrier is in contact with a memory material which has a memory property that can be changed by a write signal. Because of the exponential dependence of the tunnel resistance on the parameters of the tunnel barrier, a change in the memory property has a powerful effect on the tunnel resistance, whereby the information stored in the memory material can be read. A solid electrolyte (ion conductor), for example, is suitable as a memory layer, wherein the ions thereof can be moved relative to the interface with the tunnel barrier by the write signal. The memory layer, however, can also be, for example, a further tunnel barrier, the tunnel resistance of which can be changed by the write signal, for example by displacement of a metal layer present in this tunnel barrier. The invention further provides a method for storing and reading information to and from a memory.

Abstract: A novel electrical circuit protection design with dielectrically-isolated diode configuration and architecture is disclosed. In one embodiment of the invention, a plurality of diodes connected in series is monolithically integrated in a single piece of semiconductor substrates by utilizing dielectrically-isolated trenching and silicon-on-insulator substrates, which enable formation of “silicon islands” to insulate a diode structure electrically from adjacent structures. In one embodiment of the invention, the plurality of diodes connected in series includes at least one Zener diode, which provides a clamping voltage approximately equal to its breakdown voltage value in case of a voltage spike or a power surge event.

Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.

Abstract: An object of the present invention is to effectively add Ge in the production of GaN through the Na flux method. In a crucible, a seed crystal substrate is placed such that one end of the substrate remains on the support base, whereby the seed crystal substrate remains tilted with respect to the bottom surface of the crucible, and gallium solid and germanium solid are placed in the space between the seed crystal substrate and the bottom surface of the crucible. Then, sodium solid is placed on the seed crystal substrate. Through employment of this arrangement, when a GaN crystal is grown on the seed crystal substrate through the Na flux method, germanium is dissolved in molten gallium before formation of a sodium-germanium alloy. Thus, the GaN crystal can be effectively doped with Ge.

Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Abstract: The solid-state diode comprises a semiconductor substrate having a top side and having two masking regions formed on the top side of the semiconductor substrate and made of a first masking material impermeable to ion implantation, the masking regions comprising two mutually opposite limiting edge portions. The solid-state diode comprises an n-doped cathode region formed in the semiconductor substrate and extending up into the intermediate region between the mutually opposite limiting edge portions of the masking regions, the n-doped cathode region comprising a cathode connection field. The diode comprises a p-doped anode region formed in the semiconductor substrate, extending up into the intermediate region between the mutually opposite limiting edge portions of the masking regions and bordering/overlapping on the cathode region, the p-doped anode region comprising an anode connection field.

Abstract: In a semiconductor device including a protection diode for preventing electrostatic breakdown employing a low capacitance protection diode, an occupation area of a Zener diode as a voltage limiting element is not needed on a front surface of a semiconductor substrate. A P+ type embedded diffusion layer is formed in a P+ type semiconductor substrate. This is then covered by a non-doped first epitaxial layer. A high resistivity N type second epitaxial layer is then formed on the first epitaxial layer. The second epitaxial layer is divided by a P+ isolation layer into a first protection diode forming region and a second protection diode forming region. An N+ type embedded layer extending from the front surface of the first epitaxial layer of the first protection diode forming region to the first epitaxial layer and the second epitaxial layer, and so on are then formed. A Zener diode is formed by a P+ type upward diffusion layer extending from the P+ type embedded diffusion layer and the N+ type embedded layer.

Abstract: A semiconductor device including a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. The second diffusion region includes a ring shaped structure or a guard ring includes an inverted region which has the second conductive type. According to such a configuration, it is possible to provide a semiconductor device having the required Zener characteristics with good controllability.

Abstract: Electrostatic discharge (ESD) protection clamps for I/O terminals of integrated circuit (IC) cores comprise a bipolar transistor with an integrated Zener diode coupled between the base and collector of the transistor. Variations in clamp voltage in different parts of the same IC chip or wafer caused by conventional deep implant geometric mask shadowing are avoided by using shallow implants and forming the base coupled anode and collector coupled cathode of the Zener using opposed edges of a single relatively thin mask. The anode and cathode are self-aligned, and the width of the Zener space charge region between them is defined by the opposed edges substantially independent of location and orientation of the ESD clamps on the die or wafer. Because the mask is relatively thin and the anode and cathode implants relatively shallow, mask shadowing is negligible and prior art clamp voltage variations are avoided.