Abstract: A method of forming a plurality of diamonds provides a base, epitaxially forms a first sacrificial layer on the base, and then epitaxially forms a first diamond layer on the first sacrificial layer. The first sacrificial layer has a first material composition, and the first diamond layer is a material that is different from the first material composition. The method then epitaxially forms a second sacrificial layer on the first diamond layer, and epitaxially forms a second diamond layer on the second sacrificial layer. The second sacrificial layer has the first material composition. The base, first and second sacrificial layers, and first and second diamond layers form a heteroepitaxial super-lattice.

Abstract: A device is disclosed. The device includes a source contact in a source contact trench and a drain contact in a drain contact trench, a channel under the source contact and the drain contact, a first spacing layer on a bottom of the source contact trench and a second spacing layer on a bottom of the drain contact trench. The first spacing layer and the second spacing layer are on the surface of the channel. The device also includes a gate electrode below the channel and a dielectric above the gate electrode and underneath the channel.

Abstract: Disclosed is a detection apparatus for a metrology device operable to measure a parameter of interest from scattered radiation having been scattered from a sample. The detection device comprises a detector comprising an array of pixels. The array of pixels comprises imaging pixels for detecting an image from which the parameter of interest is determined, and direction detecting pixels for detecting the angle of incidence of said scattered radiation on said detector.

Abstract: Disclosed herein is a detector, comprising: a plurality of pixels, each pixel configured to count numbers of X-ray photons incident thereon whose energy falls in a plurality of bins, within a period of time; an X-ray absorption layer; wherein the X-ray absorption layer comprises an electrical contact within each of the pixels, and a focusing electrode surrounding the electrical contact and configured to direct to the electrical contact charge carriers generated by an X-ray photon incident within confines of the focusing electrodes; and wherein the detector is configured to add the numbers of X-ray photons for the bins of the same energy range counted by all the pixels.

Abstract: An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

Abstract: A terahertz detector circuit can include a high electron mobility transistor (HEMT) having multiple gates that can be controlled by gate signals to generate a gate-induced modulation pattern in a two-dimensional electron gas (2DEG) of the HEMT. When the gate induced modulation pattern substantially matches a signal induced modulation pattern generated by an incident terahertz signal then a detection efficiency of the incident terahertz signal is improved. Accordingly, an electronically tunable THz detector with high efficiency can be realized. When these THz detectors are arranged in an array and electrically coupled, THz images and/or multi-spectral THz images may be generated.

Abstract: Photo-detection device (100) including a semiconductor substrate (110) made of CdxHg1-xTe, with an N-doped region (120), a P-doped region (130), and a concentrated casing (150) only located in the P-doped region and having an average cadmium concentration greater than the average cadmium concentration in the N-doped region. According to the invention, the concentrated casing (150) has a cadmium concentration gradient, defining therein at least one intermediate gap zone (151) and at least one high gap zone (152), and the intermediate gap zone (151) is in direct physical contact with an electrical contact block (170). A significant reduction in the dark current and an optimal charge carrier collection are thus combined.

Abstract: A thin film transistor substrate includes a first semiconductor layer disposed on a substrate and having a first channel area, a first source area and a first drain area. A first gate electrode is disposed above the first semiconductor layer and overlaps the first channel area. A first electrode layer is disposed above the first gate electrode and electrically connects to at least one of the first source area and the first drain area. A second insulating layer is disposed between the first gate electrode and the first electrode layer. The second insulating layer includes an inorganic control layer and a first inorganic layer arranged on the inorganic control layer. The inorganic control layer has a lower density than a density of the first inorganic layer.

Abstract: The present disclosure provides an electronic device including a plurality of first electrodes, a second electrode, a functional layer disposed between each first electrode and the second electrode, and an insulating layer having a slope portion on the first electrode, wherein the functional layer is continuously disposed so as to cover the first electrode, a neighboring first electrode, and the insulating layer covering the first electrode and the neighboring first electrode, the functional layer on the first electrode has a layer thickness smaller than a height from an upper surface of the first electrode to an upper surface of the insulating layer, and the functional layer on the slope portion of the insulating layer has a layer thickness of 20 nm or more in a direction perpendicular to a slope surface of the slope portion.

Abstract: A photodiode for use in detecting X-rays and/or gamma rays is disclosed. The photodiode comprises InGaP arranged and configured to absorb X-rays and/or gamma-rays incident on the photodiode and generate charge-carriers in response thereto. The detector may be provided in an X-ray or gamma-ray photon counting spectrometer.

Abstract: A method of forming a plurality of diamonds provides a base, epitaxially forms a first sacrificial layer on the base, and then epitaxially forms a first diamond layer on the first sacrificial layer. The first sacrificial layer has a first material composition, and the first diamond layer is a material that is different from the first material composition. The method then epitaxially forms a second sacrificial layer on the first diamond layer, and epitaxially forms a second diamond layer on the second sacrificial layer. The second sacrificial layer has the first material composition. The base, first and second sacrificial layers, and first and second diamond layers form a heteroepitaxial super-lattice.

Abstract: Provided is a solid-state image pickup element that includes a pixel, a light-receiving-surface-sided trench, and a light-receiving-surface-sided shielding member. A plurality of protrusions is formed on the light-receiving surface of the pixel in the solid-state image pickup element. In addition, the light-receiving-surface-sided trench is formed around the pixel having the plurality of protrusions formed, at the light-receiving surface in the solid-state image pickup element. In addition, the light-receiving-surface-sided member is buried in the light-receiving-surface-sided trench formed around the pixel having the plurality of protrusions formed on the light-receiving surface in the solid-state image pickup element. In addition, the photoelectric conversion region of a near-infrared-light pixel expands to the surface side opposed to the light-receiving surface of the photoelectric conversion region of a visible-light pixel.

Abstract: An avalanche photodiode (APD) is provided with a mixed composite charge layer. A novel structure of InAlAs is designed with the mixed layer. A single P-type field control layer is divided into three layers of different materials with each two forming a heterojunction structure. By controlling the relative concentration distributions and thicknesses of the first, second, and third P-type field control layers along with a mesa shape formed through chemical selective etching, a part of the second P-type field control layer is exposed to the air with a part of the first one etched out at the same time through this single structure having the mesa shape. Thus, the field of a multiplication layer is further confined at center to concentrate electric-field so that fringe field is low but not collapsed. Hence, the overall speed is increased, the intensity high, and sensitivity good while response is fast and efficiency high.

Abstract: Disclosed herein are techniques for wafer-to-wafer bonding for manufacturing light emitting diodes (LEDs). In some embodiments, a method of manufacturing LEDs includes etching a semiconductor material to form a plurality of adjacent mesa shapes. The semiconductor material includes one or more epitaxial layers. The method also includes forming a passivation layer within gaps between the adjacent mesa shapes and bonding a base wafer to a first surface of the semiconductor material.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a transistor device. The method may be performed by forming an anode and a cathode over an electron supply layer disposed on a semiconductor material. A doped III-N semiconductor material is formed over the electron supply layer, and an insulating material is formed over the electron supply layer and the doped III-N semiconductor material. The insulating material continuously extends from over the anode to over the cathode. The insulating material is patterned to form sidewalls of the insulating material that define an opening over the doped III-N semiconductor material. A gate structure is formed directly between the sidewalls of the insulating material and over the doped III-N semiconductor material.

Abstract: In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.

Abstract: A high voltage device includes: a semiconductor layer, an isolation structure, a first deep well, a second deep well, a drift well, a first well, a second well, a body region, a body contact, a high voltage well, a gate, and a source and a drain. The high voltage well is formed in the second deep well, and the high voltage well is not in contact with any of the first deep well, the first well, and the second well, wherein at least part of the high voltage well is located right below all of a drift region to suppress a latch-up current generated in the high voltage device.

Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

Abstract: A nitride semiconductor device includes: a Si substrate having a surface and a rear surface; a first nitride semiconductor layer arranged on the surface of the Si substrate and constituting an electron transit layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and constituting an electron supply layer; a gate electrode arranged on the second nitride semiconductor layer; a source electrode and a drain electrode arranged on the second nitride semiconductor layer so as to be separated from the gate electrode with the gate electrode interposed therebetween, and electrically connected to the second nitride semiconductor layer; at least one recess formed on the Si substrate and recessed from the rear surface toward the surface of the Si substrate; and a thermal conductor embedded in the at least one recess and made of material having a thermal conductivity higher than a thermal conductivity of the Si substrate.

Abstract: An image sensor with an absorption enhancement semiconductor layer is provided. In some embodiments, the image sensor comprises a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked. The absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers. The absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer. Further, the image sensor comprises a plurality of protrusions and a photodetector. The protrusions are defined by the back-side semiconductor layer, and the photodetector is defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.

Abstract: An image sensor with an absorption enhancement semiconductor layer is provided. In some embodiments, the image sensor comprises a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked. The absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers. The absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer. Further, the image sensor comprises a plurality of protrusions and a photodetector. The protrusions are defined by the back-side semiconductor layer, and the photodetector is defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.

Abstract: A method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors (HPTs) integrated in a wafer are disclosed and may include receiving optical signals via optical fibers operably coupled to a top surface of the chip. Electrical signals may be generated utilizing HPTs that detect the optical signals. The electrical signals may be amplified via voltage amplifiers, or transimpedance amplifiers, the outputs of which may be utilized to bias the HPTs by a feedback network. The optical signals may be coupled into opposite ends of the HPTs. A collector of the HPTs may comprise a silicon layer and a germanium layer, a base may comprise a silicon germanium alloy with germanium composition ranging from 70% to 100%, and an emitter including crystalline or poly Si or SiGe.

Abstract: A circuit that includes: a photodiode configured to absorb photons and to generate photo-carriers from the absorbed photons; a first MOSFET transistor that includes: a first channel terminal coupled to a first terminal of the photodiode and configured to collect a portion of the photo-carriers generated by the photodiode; a second channel terminal; and a gate terminal coupled to a first control voltage source; a first readout circuit configured to output a first readout voltage; a second readout circuit configured to output a second readout voltage; and a current-steering circuit configured to steer the photo-carriers generated by the photodiode to one or both of the first readout circuit and the second readout circuit.

Abstract: A semiconductor device includes a substrate having a main surface inclined in an off-direction from a {0001} surface, and a semiconductor layer. The semiconductor layer includes a level difference for alignment mark. An epitaxial layer is disposed on a first portion of the main surface, the first portion being situated on an off-angle upstream side of the level difference, and on a second portion of the main surface, the second portion being situated on an off-angle downstream side of the level difference. A value of |WL?WR| is 1 ?m or less, in which WL represents a distance from a center of the level difference to a boundary between an off-angle upstream side corner portion of the level difference and a main surface or a {0001} facet plane generated on the main surface, and WR represents a distance from the center of the level difference to a boundary between an off-angle downstream side corner portion of the level difference and the main surface or the {0001} facet plane generated on the main surface.

Abstract: A method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors (HPTs) integrated in a wafer are disclosed and may include receiving optical signals via optical fibers operably coupled to a top surface of the chip. Electrical signals may be generated utilizing HPTs that detect the optical signals. The electrical signals may be amplified via voltage amplifiers, or transimpedance amplifiers, the outputs of which may be utilized to bias the HPTs by a feedback network. The optical signals may be coupled into opposite ends of the HPTs. A collector of the HPTs may comprise a silicon layer and a germanium layer, a base may comprise a silicon germanium alloy with germanium composition ranging from 70% to 100%, and an emitter including crystalline or poly Si or SiGe. The optical signals may be demodulated by communicating a mixer signal to a base terminal of the HPTs.

Abstract: An image sensor with an absorption enhancement semiconductor layer is provided. In some embodiments, the image sensor comprises a front-side semiconductor layer, an absorption enhancement semiconductor layer, and a back-side semiconductor layer that are stacked. The absorption enhancement semiconductor layer is stacked between the front-side and back-side semiconductor layers. The absorption enhancement semiconductor layer has an energy bandgap less than that of the front-side semiconductor layer. Further, the image sensor comprises a plurality of protrusions and a photodetector. The protrusions are defined by the back-side semiconductor layer, and the photodetector is defined by the front-side semiconductor layer, the absorption enhancement semiconductor layer, and the back-side semiconductor layer.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent infrared (IR) photodiode structures on the substrate. Each IR photodiode structure may include a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, the superlattice may have the first conductivity type. The CMOS image sensor may further include a semiconductor layer on the superlattice, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent infrared (IR) photodiode structures on the substrate. Each IR photodiode structure may include a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, the superlattice may have the first conductivity type. The CMOS image sensor may further include a semiconductor layer on the superlattice, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

Abstract: A method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors (HPTs) integrated in a wafer are disclosed and may include receiving optical signals via optical fibers operably coupled to a top surface of the chip. Electrical signals may be generated utilizing HPTs that detect the optical signals. The electrical signals may be amplified via voltage amplifiers, or transimpedance amplifiers, the outputs of which may be utilized to bias the HPTs by a feedback network. The optical signals may be coupled into opposite ends of the HPTs. A collector of the HPTs may comprise a silicon layer and a germanium layer, a base may comprise a silicon germanium alloy with germanium composition ranging from 70% to 100%, and an emitter including crystalline or poly Si or SiGe. The optical signals may be demodulated by communicating a mixer signal to a base terminal of the HPTs.

Abstract: The present technique relates to a solid-state imaging device, a solid-state imaging device manufacturing method, and an electronic apparatus that are capable of providing a solid-state imaging device that can prevent generation of RTS noise due to miniaturization of amplifying transistors, and can achieve a smaller size and a higher degree of integration accordingly. A solid-state imaging device (1-1) includes: a photodiode (PD) as a photoelectric conversion unit; a transfer gate (TG) that reads out charges from the photodiode (PD); a floating diffusion (FD) from which the charges of the photodiode (PD) are read by an operation of the transfer gate (TG); and an amplifying transistor (Tr3) connected to the floating diffusion (FD). More particularly, the amplifying transistor (Tr3) is of a fully-depleted type.

Abstract: Provided is a semiconductor device in which electron mobility is improved by applying sufficiently large tensile stress in a predetermined direction without occurrence of cracks in a nitride semiconductor. The semiconductor device includes: substrate (101), electron transit layer (103) that is disposed on substrate (101) and is formed by GaN; and electron supply layer (104) that is disposed on electron transit layer (103) and is formed by AlGaN. A coefficient of thermal expansion of substrate (101) is different between a first direction in a main surface of substrate (101) and a second direction that is perpendicular to the first direction in the main surface, and tensile stress occurs in electron transit layer (103).

Abstract: A device that detects single optical and radiation events and that provides improved blue detection efficiency and lower dark currents than prior silicon SSPM devices. The sensing element of the devices is a photodiode that may be used to provide single photon detection through the process of generating a self-sustained avalanche. The type of diode is called a Geiger photodiode or signal photon-counting avalanche diode. A CMOS photodiode can be fabricated using a “buried” doping layer for the P-N junction, where the high doping concentration and P-N junction is deep beneath the surface, and the doping concentration at the surface of the diode may be low. The use of a buried layer with a high doping concentration compared to the near surface layer of the primary P-N junction allows for the electric field of the depletion region to extend up near the surface of the diode. With a low doping concentration through the bulk of the diode, the induced bulk defects are limited, which may reduce the dark current.

Abstract: An optical modulator may include a leftmost waveguide, a rightmost waveguide, and a dielectric layer disposed therebetween. In one embodiment, the waveguides may be disposed on the same plane. When a voltage potential is created between the rightmost and leftmost waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) structure that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. As opposed to a horizontal SISCAP structure where the dielectric layer is disposed between upper and lower waveguides, arranging the dielectric layer between waveguides disposed on the same plane results in a vertical SISCAP structure. In one embodiment, the leftmost and rightmost waveguide are both made from crystalline silicon.

Abstract: The present invention provides a charge transport film which is prepared through subjecting a coating film including at least one charge transporting agent to an atmospheric pressure plasma treatment, wherein electron transfer between the charge transport film and a substance that contacts with the charge transport film is promoted, and deterioration in performance due to diffusion and mixing or crystallization of low molecular weight components, such as a charge transporting agent, incorporated in a cured film is suppressed also in the case of film formation by a wet method, and which exhibits excellent charge transportability and stability over time; a production method with good productivity; and a light-emitting element and photoelectric conversion element equipped with the charge transport film, the atmospheric pressure plasma treatment being preferably a treatment that applies plasma, which is generated using a plasma generating apparatus and conveyed using an inert gas, to the coating film.

Abstract: A method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors (HPTs) integrated in a CMOS SOI wafer are disclosed and may include receiving optical signals via a top surface of a photonically-enabled CMOS chip; and generating electrical signals in the chip utilizing one or more HPTs that detect optical signals. The HPTs may comprise a base and a split collector, with the split collector comprising a silicon-on-insulator (SOI) layer and a germanium layer. The thickness of the germanium layer may be such that carriers in the base do not interact with defects from an interface between the SOI layer and the germanium layer. The electrical signals may be amplified by amplifiers, the outputs of which may be utilized to bias the HPTs by a feedback network. An electrode formed longitudinally in the direction of light travel through the HPTs may bias the base of the HPTs.

Abstract: A heterojunction bipolar transistor includes a collector layer composed of a semiconductor containing GaAs as a main component; a base layer including a first base layer and a second base layer the first base layer forming a heterojunction with the collector layer and being composed of a semiconductor containing a material as a main component, the material being lattice-mismatched to the main component of the collector layer, the first base layer having a film thickness less than a critical thickness at which a misfit dislocation is introduced, the second base layer being joined to the first base layer and composed of a semiconductor containing a material as a main component, and the material being lattice-matched to the main component of the collector layer; and an emitter layer that forms a heterojunction with the second base layer.

Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.

Abstract: Provided is a method of forming a gate insulating film for use in a MOSFET for a power device. An AlN film is formed on a SiC substrate of a wafer W and then the formation of an AlO film and the formation of an AlN film on the formed AlO film are repeated, thereby forming an AlON film having a laminated structure in which AlO films and AlN films are alternately laminated. A heat treatment is performed on the AlON film having the laminated structure.

Abstract: A barrier-type photo-detector, such as an infra-red detector, is disclosed. The detector may include an absorber layer having predetermined majority and minority carrier types with corresponding energy bands; and a Barrier made, at least in part, of a semiconductor with a Barrier energy gap and corresponding conduction and valence bands, a first side of said Barrier adjacent a first side of said absorber layer. Metal contact regions may be disposed on the barrier layer, the metal contact regions delineating pixels where image data may be read out from the photo-detector; wherein the Barrier is configured so as to allow minority carrier current flow while blocking majority carrier current flow between the absorber layer and the metal contact regions.

Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein. and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.

Abstract: A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric.

Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.

Abstract: A device includes a device isolation region formed into a semiconductor substrate, the device isolation region having gaps for photo-sensitive devices, a dummy gate structure formed over the substrate, the dummy gate structure comprising at least one structure that partially surrounds a doped pickup region formed into the device isolation region, and a via connected to the doped pickup region.

Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.

Abstract: A low noise infrared photodetector has an epitaxial heterostructure that includes a photodiode and a transistor. The photodiode includes a high sensitivity narrow bandgap photodetector layer of first conductivity type, and a collection well of second conductivity type in contact with the photodetector layer. The transistor includes the collection well, a transfer well of second conductivity type that is spaced from the collection well and the photodetector layer, and a region of first conductivity type between the collection and transfer wells.

Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.

Abstract: A method of manufacturing an organic light-emitting element. A first layer is formed above a substrate, and exhibits hole injection properties. A bank material layer is formed above the first layer using a bank material. Banks are formed by patterning the bank material layer, and forming a resin film on a surface of the first layer by attaching a portion of the bank material layer to the first layer, the banks defining apertures corresponding to light-emitters, the resin material being the same as the bank material. A functional layer is formed by applying ink to the apertures that contacts the resin film. The ink contains an organic material. The functional layer includes an organic light-emitting layer. A second layer is formed above the functional layer and exhibits electron injection properties. The hole injection properties of the first layer are then degraded by applying electrical power to an element structure.

Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.

Abstract: To provide a light emitting device high in reliability with a pixel portion having high definition with a large screen. According to a light emitting device of the present invention, on an insulator (24) provided between pixel electrodes. an auxiliary electrode (21) made of a metal film is formed, whereby a conductive layer (20) made of a transparent conductive film in contact with the auxiliary electrode can be made low in resistance and thin. Also, the auxiliary electrode (21) is used to achieve connection with an electrode on a lower layer, whereby the electrode can be led out with the transparent conductive film formed on an EL layer. Further, a protective film (32) made of a film containing hydrogen and a silicon nitride film which are laminated is formed, whereby high reliability can be achieved.

Abstract: A semiconductor arrangement is provided that includes one or more substrate structures. One or more nitride-based material structures are used in fabricating nitride-based devices. One or more intermediary layers are interposed between the one or more substrate structures and the one or more nitride-based material structures. The one or more intermediary layers support the lattice mismatch and thermal expansion coefficients between the one or more nitride-based material structure and the one or more substrate structures. Several new electronic devices based on this arrangement are described.