Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.

Abstract: In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template may expand the lattice constant in the light emitting layer over the range of lattice constants available from conventional growth templates. Strain is defined as follows: a given layer has a bulk lattice constant abulk corresponding to a lattice constant of a free standing material of a same composition as that layer and an in-plane lattice constant ain-plane corresponding to a lattice constant of that layer as grown in the structure. The amount of strain in a layer is |(ain-plane?abulk)|/abulk. In some embodiments, the strain in the light emitting layer is less than 1%.

Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.

Abstract: Disclosed is a photoelectric surface including: a first group III nitride semiconductor layer that produces photoelectrons according to incidence of ultraviolet rays; and a second group III nitride semiconductor layer provided adjacent to the first group III nitride semiconductor layer and made of a thin-film crystal having c-axis orientation in a thickness direction, the second group III nitride semiconductor layer having an Al composition higher than that of the first group III nitride semiconductor layer.

Abstract: A gallium nitride-based compound semiconductor light-emitting device is disclosed which includes an n-type semiconductor layer of a gallium nitride-based compound semiconductor, a light-emitting layer of a gallium nitride-based compound semiconductor and a p-type semiconductor layer of a gallium nitride-based compound semiconductor formed on a substrate in this order, and has a negative electrode and a positive electrode provided on the n-type semiconductor layer and the p-type semiconductor layer, respectively. The negative electrode includes a bonding pad layer and a contact metal layer which is in contact with the n-type semiconductor layer, and the contact metal layer is composed of a Cr—Al alloy.

Abstract: The present invention relates to integrated structures of III-V and Silicon materials for making optoelectronic devices on chip compatible with complimentary metal oxide semiconductor (CMOS). As a result, various light generation, detection, switching, modulation, filtering, multiplexing, signal manipulation and beam splitting devices could be fabricated in semiconductor material such as silicon on insulator (SOI) and other material substrate.

Abstract: A field effect transistor including an i-type first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer and having a band gap energy higher in magnitude than that of the first semiconductor layer. The first semiconductor layer and second semiconductor layer are each made of a gallium nitride-based compound semiconductor layer. A gate electrode is formed on the second semiconductor layer and a second electrode is formed on the first semiconductor layer. Thus, the field effect transistor is constructed in such a manner as the first semiconductor layer and second semiconductor layer are interposed between the gate electrode and the second electrode. Thus field effect transistor is able to discharge the holes that are accumulated in the channel from the elemental structure and to improve the withstand voltage of the field effect transistor.

Abstract: A heterostructure is provided which includes a substantially relaxed SiGe layer present atop an insulating region that is located on a substrate. The substantially relaxed SiGe layer has a thickness of from about 2000 nm or less, a measured lattice relaxation of from about 50 to about 80% and a defect density of less than about 108 defects/cm2. A strained epitaxial Si layer is located atop the substantially relaxed SiGe layer and at least one alternating stack including a bottom relaxed SiGe layer and an top strained Si layer located on the strained epitaxial Si layer.

Abstract: A gate wiring electrode is formed into a ladder-like pattern. Moreover, between source electrodes and drain electrodes in the entire Switch MMIC, the gate wiring electrodes are disposed. Furthermore, at a cross part between the gate wiring electrode and the source electrode or the drain electrode, a nitride film having a large relative dielectric constant and a polyimide or a hollow part having a small relative dielectric constant are disposed. Accordingly, a capacitance at the cross part is reduced. Thus, a second harmonic wave level can be lowered. Moreover, a leak of a high-frequency signal between the drain electrode and the source electrode can be prevented. Thus, a third harmonic level can be lowered. Consequently, distortion characteristics of the Switch MMIC can be significantly improved.

Abstract: A solid-state image sensor of the present invention has a plurality of pixel cells that generate signal charges in accordance with incident light. It is characterized by having a gettering region within the area of a pixel cell. The gettering region, which is disposed closely to the photoelectrical conversion layer, makes direct and efficient use of gettering capability in the pixel region in the solid-state image sensor. As a result, it is possible to effectively eliminate metal contaminant contained in the pixel region, thereby remarkably reducing dark outputs occurring from the metal contaminant.

Abstract: A boron phosphide-based semiconductor device enhanced in properties includes a substrate (11) composed of a {111}-Si single crystal having a surface {111} crystal plane and a boron phosphide-based semiconductor layer formed on the surface of the substrate and composed of a polycrystal layer (12) that is an aggregate of a plurality of a triangular pyramidal single crystal entities (13) of the boron phosphide-based semiconductor crystal, where in each single crystal entity has a twining interface that forms an angle of 60° relative to a <110> crystal direction of the substrate.

Abstract: Provided are a vertical GaN-based LED and a method of manufacturing the same. The vertical GaN-based LED includes an n-electrode. An AlGaN layer is formed under the n-electrode. An undoped GaN layer is formed under the AlGaN layer to provide a two-dimensional electron gas layer to a junction interface of the AlGaN layer. A GaN-based LED structure includes an n-type GaN layer, an active layer, and a p-type GaN layer that are sequentially formed under the undoped GaN layer. A p-electrode is formed under the GaN-based LED structure. A conductive substrate is formed under the p-electrode.

Abstract: An optical device for sensing an incident optical wave within a wavelength range includes a first array and a second array of electrodes superposed on a substrate, and a sensor connected to the contacts. The arrays are interdigitated. Each array includes its own parameters: contact width, contact thickness, groove width, and a groove dielectric constant. A structure associated with the arrays resonantly couples the incident wave and a local electromagnetic resonance or hybrid mode including at least a surface plasmon cavity mode (CM). For coupling the CM, an aspect ratio of contact thickness to spacing between electrodes is at least 1. A preferred structure for coupling a hybrid mode for high bandwidth and responsivity includes a higher dielectric constant in alternating grooves. The substrate may include silicon, including silicon-on-insulator (SOI). An SOI device having a alternating grooves with a higher dielectric, e.g., silicon oxide, provides 0.25 A/W and 30 GHz bandwidth.

Abstract: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1,0 ?m thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1,0-?m thick and its surface dislocation density is less than 106/cm2.

Abstract: An AlGaInP layer is formed on a substrate made of GaAs, and an AlGaAs layer is formed on the AlGaInP layer via a buffer layer therebetween. The buffer layer has a thickness of about 1.1 nm and is made of AlGaInP whose Ga content is smaller than that of the AlGaInP layer. The buffer layer may alternatively be made of AlGaAs whose Al content is smaller than that of the AlGaAs layer.

Abstract: A light-emitting diode is built on a silicon substrate doped with a p-type impurity to possess sufficient conductivity to provide a current path. The p-type silicon substrate has epitaxially grown thereon two superposed buffer layers of aluminum nitride and n-type indium gallium nitride. Further grown epitaxially on the buffer layers is the main semiconductor region of the LED which comprises a lower confining layer of n-type gallium nitride, an active layer for generating light, and an upper confining layer of p-type gallium nitride. In the course of the growth of the main semiconductor region there occurs a thermal diffusion of aluminum, gallium and indium from the buffer layers into the p-type silicon substrate, with the consequent creation of an alloy layer of the diffused metals. Representing p-type impurities in the p-type silicon substrate, these metals do not create a pn junction in the substrate which causes a forward voltage drop.

Abstract: A process for fabricating a III-nitride power semiconductor device which includes forming a gate structure while providing a protective body over areas that are to receive power electrodes.

Abstract: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry in the substrate operatively coupled to the image sensor. The imager die can further include external contacts electrically coupled to the integrated circuitry and a cover over the curved image sensor.

Abstract: A semiconductor light-emitting device fabricated in a nitride material system has an active region disposed over a substrate. The active region comprises a first aluminium-containing layer forming the lowermost layer of the active region, a second aluminium-containing layer forming the uppermost layer of the active region, and at least one InGaN quantum well layer disposed between the first aluminium-containing layer and the second aluminum-containing layer. The aluminium-containing layers provide improved carrier confinement in the active region, and so increase the output optical power of the device.

Abstract: The present invention provides a heterojunction photodiode which includes a pn or Schottky-barrier junction formed in a first material region having a bandgap energy Eg1. When reverse-biased, the junction creates a depletion region which expands towards a second material region having a bandgap energy Eg2 which is less than Eg1. This facilitates signal photocurrent generated in the second region to flow efficiently through the junction in the first region while minimizing the process-related dark currents and associated noise due to near junction defects and imperfect surfaces which typically reduce photodiode device performance. The heterojunction photodiode can be included in an imaging system which includes an array of junctions to form an imager.

Abstract: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in stresses may reduce defect formation and cracking in the gallium nitride material region, as well as reducing warpage of the overall structure. The gallium nitride material-based semiconductor structures may be used in a variety of applications such as transistors (e.g. FETs) Schottky diodes, light emitting diodes, laser diodes, SAW devices, and sensors, amongst others devices.

Abstract: An avalanche photodiode has improved low-noise characteristics, high-speed response characteristics, and sensitivity. The avalanche photodiode includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a semiconductor multiplication layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a semiconductor light-absorbing layer interposed between the semiconductor multiplication layer and the second conductivity type semiconductor layer. The avalanche photodiode further comprises a multiplication suppressing layer which suppresses multiplication of charge carriers in the semiconductor light-absorbing layer, located between the semiconductor light-absorbing layer and the second conductivity type semiconductor layer.

Abstract: A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.

Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.

Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.

Abstract: A method of manufacturing a group III-V crystal is made available by which good-quality group III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. A method of manufacturing a group III-V crystal, characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Additionally, a method of manufacturing a group III-V crystal, characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.

Abstract: The present invention provides a photoresist stripper including about 5 wt % to about 20 wt % alcohol amine, about 40 wt % to about 70 wt % glycol ether, about 20 wt % to about 40 wt % N-methyl pyrrolidone, and about 0.2 wt % to about 6 wt % chelating agent.

Abstract: A tunable QWIP FPA device that is configured for spectral tunability for performing the likes of imaging and spectroscopy is disclosed. A selected bias voltage is applied across the contacts associated with a particular detector layer/channel of the device, where each applied bias corresponds to a particular target spectrum/color for detection. Each detector layer/channel can be coarse tuned for a bimodal or dual-band operation (e.g., MWIR/LWIR). Also, each detector layer/channel is configured for continuous or fine tuning within a particular mode (e.g., MWIR/MWIR). Thus, dynamic bias-controlled tuning is enabled. Asymmetric quantum well configurations enable this tunability.

Abstract: A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and is controllable through the manipulation of spontaneous polarization fields obtained according to the characteristics of the III-nitride material. The field effect transistor produced can be made to be a nominally on device where the in-plane lattice constants of the material forming the interface match. A nominally off device may be produced where one of the material layers has an in-plane lattice constant that is larger than that of the other layer material. The layer materials are preferably InAlGaN/GaN layers that are particularly tailored to the characteristics of the present invention.

Abstract: A group III-V nitride-based semiconductor substrate has: a first layer made of GaN single crystal; and a second layer formed on the first layer, the second layer made of group III-V nitride-based semiconductor single crystal represented by AlxGa1-xN, where 0<x?1, wherein a top surface and a back surface of the substrate are flattened.

Abstract: A group III-V nitride-based semiconductor substrate having a group III-V nitride-based semiconductor thick film with a same composition in the entire film. The thick film has a first region with a predetermined impurity concentration and a second region with an impurity concentration lower than the first region.

Abstract: Provided are a vertical GaN-based LED and a method of manufacturing the same. The vertical GaN-based LED includes an n-electrode. An AlGaN layer is formed under the n-electrode. An undoped GaN layer is formed under the AlGaN layer to provide a two-dimensional electron gas layer to a junction interface of the AlGaN layer. A GaN-based LED structure includes an n-type GaN layer, an active layer, and a p-type GaN layer that are sequentially formed under the undoped GaN layer. A p-electrode is formed under the GaN-based LED structure. A conductive substrate is formed under the p-electrode.

Abstract: A method of making a bulk crystal substrate of a GaN single crystal includes the steps of forming a molten flux of an alkali metal in a reaction vessel and causing a growth of a GaN single crystal from the molten flux, wherein the growth is continued while replenishing a compound containing N from a source outside the reaction vessel.

Abstract: The nitride semiconductor device according to one embodiment of the present invention comprises: a silicon substrate; a first aluminum gallium nitride (AlxGa1?xN (0?x?1)) layer formed as a channel layer on the silicon substrate in an island shape; and a second aluminum gallium nitride (AlyGa1?yN (0?y?1, x<y)) layer formed as a barrier layer of a first conductive type or i-type on the first aluminum gallium nitride layer.

Abstract: III-nitride material structures including silicon substrates, as well as methods associated with the same, are described. Parasitic losses in the structures may be significantly reduced which is reflected in performance improvements. Devices (such as RF devices) formed of structures of the invention may have higher output power, power gain and efficiency, amongst other advantages.

Abstract: A photodetector is described. The photodetector is comprised of a substrate, a first n-type III-V compound semiconductor layer located on the substrate, an n++-type III-V compound semiconductor layer located on a first portion of the first n-type III-V compound semiconductor layer with a second portion of the first n-type III-V compound semiconductor layer exposed, a p-type III-V compound semiconductor layer located on the n++-type compound semiconductor layer, an undoped III-V compound semiconductor layer located on the p-type III-V compound semiconductor layer, a second n-type III-V compound semiconductor layer located on the undoped III-V compound semiconductor layer, a conductive transparent oxide layer located on the second n-type III-V compound semiconductor layer, a first electrode located on a portion of the conductive transparent oxide layer, and a second electrode located on a portion of the second portion of the first n-type III-V compound semiconductor layer.

Abstract: An optical device with a quantum well is provided. The optical device includes an active layer made of a Group III-V semiconductor compound and having a quantum well of a bandgap grading structure in which conduction band energy and valence band energy change linearly with a slope with the content change of predetermined components while an energy bandgap between the conduction band energy and the valence band energy is maintained at a predetermined value; and two barrier layers, one of which is positioned on an upper surface of the active layer and the other is positioned on a lower surface of the active layer, and which are made of a Group III-V semiconductor compound and have higher conduction band energy and lower valence band energy than the active layer. A driving voltage is decreased and luminous efficiency and reliability are enhanced.

Abstract: A III–V group nitride system semiconductor self-standing substrate has: a first III–V group nitride system semiconductor crystal layer that has a region with dislocation lines gathered densely, the dislocation lines being gathered substantially perpendicular to a surface of the substrate, and a region with dislocation lines gathered thinly; and a second III–V group nitride system semiconductor crystal layer that is formed up to 10 ?m from the surface of the substrate on the first III–V group nitride system semiconductor crystal layer and that has a dislocation density distribution that is substantially uniform.

Abstract: To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A third semiconductor layer having a lattice property substantially identical to that of the first semiconductor layer may be formed over the first semiconductor pattern. The third semiconductor layer may then be etched to form a second semiconductor pattern. A gate may be formed on the second semiconductor pattern. The contact surface between the second semiconductor pattern and the gate pattern may consequently increased to reduce a current loss. Further, the lattice properties may be changed to improve electron mobility of the semiconductor layers.

Abstract: A semiconductor light-receiving device has a substrate including upper, middle and lower regions in its front side. A p-type layer on the lower region has a top surface including a portion on a level with the middle region. An electrode covers at least part of the boundary between the portion of the p-type layer and the middle region. An n-type layer on the p-type layer has a top surface including a portion on a level with the upper region. Another electrode covers at least part of the boundary between the portion of the n-type layer and the upper region.

Abstract: Electromagnetic energy is detected with high efficiency in the spectral range having wavelengths of about 1–2 microns by coupling an absorber layer having high quantum efficiency in the spectral range having wavelengths of about 1–2 microns to an intrinsic semiconducting blocking region of an impurity band semiconducting device included in a solid state photon detector.

Abstract: An avalanche photodiode has improved low-noise characteristics, high-speed response characteristics, and sensitivity. The avalanche photodiode includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, a semiconductor multiplication layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a semiconductor light-absorbing layer interposed between the semiconductor multiplication layer and the second conductivity type semiconductor layer. The avalanche photodiode further comprises a multiplication suppressing layer which suppresses multiplication of charge carriers in the semiconductor light-absorbing layer, has a thickness of 0.6 ?m or less, and is located between the semiconductor light-absorbing layer and the second conductivity type semiconductor layer. The thickness of the semiconductor light-absorbing layer is 0.5 ?m or more.

Abstract: A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel.

Abstract: A nitride compound semiconductor element having improved characteristics, productivity and yield. A nitride compound semiconductor element includes: a sapphire substrate; a first single crystalline layer of AlN formed on said sapphire substrate; a second single crystalline layer formed on said first single crystalline layer, said second single crystalline layer being made of AlxGa1-xN (0.8?x?0.97) and having a thickness of equal to or more than 0.3 ?m and equal to or less than 6 ?m; and a device structure section of a nitride semiconductor formed on said second single crystalline layer.

Abstract: An n-type buffer layer composed of n-type GaN, an n-type cladding layer composed of n-type AlGaN, an n-type optical confinement layer composed of n-type GaN, a single quantum well active layer composed of undoped GaInN, a p-type optical confinement layer composed of p-type GaN, a p-type cladding layer composed of p-type AlGaN, and a p-type contact layer composed of p-type GaN are formed on a substrate composed of sapphire. A current blocking layer formed in an upper portion of the p-type cladding layer and on both sides of the p-type contact layer to define a ridge portion is composed of a dielectric material obtained by replacing some of nitrogen atoms composing a Group III–V nitride semiconductor with oxygen atoms.

Abstract: An optical device includes an antimonide-containing substrate, and an antimonide-containing n-doped layer provided on the substrate. The optical device further includes an antimonide-containing i-doped layer provided on the n-doped layer, an antimonide-containing p-doped layer provided on the i-doped layer, and an antimonide-containing p+-doped layer provided on the p-doped layer.

Abstract: A semiconductor device exhibiting interband tunneling with a first layer with a first conduction band edge with an energy above a first valence band edge, with the difference a first band-gap. A second layer with second conduction band edge with an energy above a second valence band edge, with the difference a second band-gap, and the second layer formed permitting electron carrier tunneling transport. The second layer is between the first and a third layer, with the difference between the third valence band edge and the third conduction band edge a third band-gap. A Fermi level is nearer the first conduction band edge than the first valence band edge. The second valence band edge is beneath the first conduction band edge. The second conduction band edge is above the third valence band edge. The Fermi level is nearer the third valence band edge than to the third conduction band edge.

Abstract: A nitride semiconductor substrate having a rugged surface being lapped by whetting granules to roughness between Rms5 nm and Rms200 nm, which has a function of reducing dislocations of a GaN, InGaN or AlGaN layer epitaxially grown on the lapped substrate by gathering dislocations in the epi-layer to boundaries of holes, pulling the dislocations to bottoms of the holes. Higher roughness of the nitride substrate degrades morphology of an epitaxially-grown layer thereon but reduces dislocation density to a lower level. Morphology of the epi-layer contradicts the dislocation density of the epi-layer. The nitride semiconductor substrate can reduce dislocation density and can be low cost and useful substrates.

Abstract: A semiconductor device having at least one layer of a group III–V semiconductor material epitaxially deposited on a group III–V nucleation layer adjacent to a germanium substrate. By introducing electrical contacts on one or more layers of the semiconductor device, various optoelectronic and microelectronic circuits may be formed on the semiconductor device having similar quality to conventional group III–V substrates at a substantial cost savings. Alternatively, an active germanium device layer having electrical contacts may be introduced to a portion of the germanium substrate to form an optoelectronic integrated circuit or a dual optoelectronic and microelectronic device on a germanium substrate depending on whether the electrical contacts are coupled with electrical contacts on the germanium substrate and epitaxial layers, thereby increase the functionality of the semiconductor devices.

Abstract: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1.0 ?m thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1.0 ?m thick and its surface dislocation density is less than 106/cm2.