Abstract: A lateral junction semiconductor device and method for fabricating the same comprising the steps of taking a semiconductor structure having a stack formed by a plurality of layers of semiconductor material arranged in a series of substantially parallel planes, the semiconductor material within a first layer having an excess of charge carriers of a first polarity at a first concentration, and selectively removing semiconductor material from the first layer to a depth which varies along a first direction substantially parallel with the planes of the layers within the structure, so as to provide a gradation of the concentration of charge carriers of first polarity within an active layer along the first direction. A photon source comprising said lateral junction semiconductor device.

Abstract: The present invention relates to a high performance heterojunction bipolar transistor (HBT) having a base region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 nm thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content. The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.

Abstract: Thermal boundary resistances within nitride semiconductor LEDs are reduced or eliminated by forming a thick nitride epitaxial layer, which can be separated from a growth substrate, and by reducing the number of thermal boundary layers during laser lift-off. The thermal boundary resistances within nitride semiconductor LEDs can also be reduced or eliminated by forming a plurality of thin nitride epitaxial layers.

Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

Abstract: A method is provided of making a semiconductor wafer for a semiconductor junction diode device having a target forward voltage drop and a target reverse breakdown voltage. The method begins by doping a semiconductor substrate of a first conductivity type through the back surface with a first dopant of the first conductivity type in an amount sufficient to form a semiconductor junction diode device having a target forward voltage drop. Next, the substrate is doped through the front surface with a second dopant of the first conductivity type in an amount sufficient to form the semiconductor junction diode device such that it has a target reverse breakdown voltage.

Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

Abstract: A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate recesses in the structure. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.

Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1-100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11-20> direction lying in a range of 0.00 degree to 0.06 degree.

Abstract: A lattice matched silicon germanium (SiGe) semiconductive alloy is formed when a {111} crystal plane of a cubic diamond structure SiGe is grown on the {0001} C-plane of a single crystalline Al2O3 substrate such that a <110> orientation of the cubic diamond structure SiGe is aligned with a <1,0,?1,0> orientation of the {0001} C-plane. A lattice match between the substrate and the SiGe is achieved by using a SiGe composition that is 0.7223 atomic percent silicon and 0.2777 atomic percent germanium. A layer of Si1-xGex is formed on the cubic diamond structure SiGe. The value of X (i) defines an atomic percent of germanium satisfying 0.2277<X<1.0, (ii) is approximately 0.2777 where the layer of Si1-xGex interfaces with the cubic diamond structure SiGe, and (iii) increases linearly with the thickness of the layer of Si1-xGex.

Abstract: A photodiode for detection of preferably infrared radiation wherein photons are absorbed in one region and detected in another. In one example embodiment, an absorbing P region is abutted with an N region of lower doping such that the depletion region is substantially (preferably completely) confined to the N region. The N region is also chosen with a larger bandgap than the P region, with compositional grading of a region of the N region near the P region. This compositional grading mitigates the barrier between the respective bandgaps. Under reverse bias, the barrier is substantially reduced or disappears, allowing charge carriers to move from the absorbing P region into the N region (and beyond) where they are detected. The N region bandgap is chosen to be large enough that the dark current is limited by thermal generation from the field-free p-type absorbing volume, and also large enough to eliminate tunnel currents in the wide gap region of the diode.

Abstract: A semiconductor-based structure includes first and second layers bonded directly to each other at an interface. Parallel to the interface, the lattice spacing of the second layer is different than the lattice spacing of the first layer. The first and second layers are each formed of essentially the same semiconductor. A method for making a semiconductor-based structure includes providing first and second layers that are formed of essentially the same semiconductor. The first and second layers have, respectively, first and second surfaces. The second layer has a different lattice spacing parallel to the second surface than the lattice spacing of the first layer parallel to the first surface. The method includes contacting the first and second surfaces, and annealing to promote direct atomic bonding between the first and second layers.

Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness direction than in an upper portion and in a lower portion.

Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.

Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

Abstract: A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.

Abstract: A GaN heterojunction FET has an AlxGa1-xN first graded layer and an AlyGa1-yN second graded layer, which are formed sequentially on a channel layer. The Al mole fraction x of the first graded layer decreases linearly from, for example, 0.2 at an interface of the first graded layer with the channel layer to 0.1 at an interface thereof with the second graded layer. The Al mole fraction y of the second graded layer increases from, for example, 0.1 at an interface of the second graded layer with the first graded layer to 0.35 at a surface located on the opposite side from the first graded layer. Because the intrinsic polarization of AlGaN depends on the Al mole fraction, fixed negative charge is generated in the AlxGa1-xN first graded layer, and fixed positive charge is generated in the AlyGa1-yN second graded layer.

Abstract: A semiconductor device includes: a first nitride semiconductor layer having at least one projection on an upper surface thereof; a second nitride semiconductor layer formed on a top surface of the projection of the first nitride semiconductor layer and having a higher carrier concentration than the first nitride semiconductor layer; a first electrode formed on the second nitride semiconductor layer so as to overhang like a canopy and functioning as one of a source and a drain; and a second electrode formed to the side of the projection on the first nitride semiconductor layer and functioning as a gate.

Abstract: A photodiode for detection of preferably very long wavelength infrared radiation wherein low energy photons are absorbed in one region and detected in another. In one example embodiment, an absorbing P region is abutted with an N region of lower doping such that the depletion region is substantially (preferably completely) confined to the N region. The N region is also chosen with a larger bandgap than the P region, with compositional grading of a region of the N region near the P region. This compositional grading mitigates the barrier between the respective bandgaps. Under reverse bias, the barrier is substantially reduced or disappears, allowing charge carriers to move from the absorbing P region into the N region (and beyond) where they are detected. The N region bandgap is chosen to be large enough that the dark current is limited by thermal generation from the field-free p-type absorbing volume, and also large enough to eliminate tunnel currents in the wide bandgap region of the diode.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) is disclosed. The MOSFET includes a semiconductor substrate, a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate, an epitaxial layer doped with high concentration impurities over the germanium layer, a gate structure on the epitaxial layer, and source/drain regions with lightly doped drain (LDD) regions in the semiconductor substrate. The germanium layer supplies carriers into the epitaxial layer so that short channel effects are reduced.

Abstract: There is provided a semiconductor device able to increase the mobility of carriers and reduce the current in the OFF state. The semiconductor device includes a gate electrode, an insulating layer on the gate electrode, a first electrode on the insulating layer, a second electrode on the insulating layer at an interval with the first electrode, an organic semiconductor layer disposed in the interval between the first electrode and the second electrode and covering at least part of the first electrode and the second electrode, and a first resistance layer formed on the organic semiconductor layer and having an electrical resistance lower than that of the organic semiconductor layer. The first resistance layer is formed from conductive polymers.

Abstract: A lower electron supply layer is disposed over a lower electron transport layer made of compound semiconductor. The lower electron supply layer is made of n-type compound semiconductor having an electron affinity smaller than that of the lower electron transport layer. An upper electron transport layer is disposed over the lower electron supply layer. The upper electron transport layer is made of compound semiconductor having a doping concentration lower than that of the lower electron supply layer or non-doped compound semiconductor. An upper electron supply layer is disposed over the upper electron transport layer. The upper electron supply layer is made of n-type compound semiconductor having an electron affinity smaller than that of the upper electron transport layer. A source and drain electrodes are disposed over the upper electron supply layer. A gate electrode is disposed over the upper electron supply layer between the source and drain electrodes.

Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the SiGe film. The buffer layer may be aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN). A GaN film is deposited overlying the buffer layer having a second TEC, greater than the first TEC. The SiGe film has a third TEC, with a value in between the first and second TECs. In one aspect, a graded SiGe film may be formed having a Ge content ratio in a range of about 0% to 50%, where the Ge content increases with the graded SiGe film thickness.

Abstract: One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium ions are implanted into a silicon substrate with a desired dose and energy to be located beneath a surface silicon layer in the substrate. The implantation of germanium ions at least partially amorphizes the surface silicon layer. The substrate is heat treated to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. The crystalline silicon layer is strained by a lattice mismatch between the silicon germanium layer and the crystalline silicon layer. Other aspects are provided herein.

Abstract: A semiconductor heterostructure that includes a support substrate with a first in-plane lattice parameter, a buffer structure formed on the support substrate and having on top in a relaxed state a second in-plane lattice parameter, and a multi-layer stack of ungraded layers formed on the buffer structure. This semiconductor hetero-structure possess a lower surface roughness than other heterostructures. In the heterostructure, the ungraded layers are strained layers that comprise at least one strained smoothing layer of a semiconductor material having in a relaxed state a third in-plane lattice parameter which has a value between the first and the second lattice parameter.

Abstract: A method and system for providing a metal oxide semiconductor (MOS) device are described. The method and system include providing a source, a drain, and a channel residing between the source and the drain. At least a portion of the channel includes an alloy layer including an impurity having a graded concentration. The method and system also include providing a gate dielectric and a gate electrode. At least a portion of the gate dielectric resides above the alloy layer. The gate dielectric resides between the alloy layer and the gate electrode.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A method and system for providing a semiconductor device is described. The method and system include providing a compound region and providing a doped region. The compound region includes an alloy having an impurity. The impurity has a graded profile in the compound region. The doped region includes a dopant having a profile. The profile includes a retrograde region. In one aspect, the semiconductor device is a bipolar transistor. In this aspect, the method and system include providing an emitter region, a collector region, and a compound base region. The compound base region resides between the emitter region and the collector region. The compound base region has a collector side and includes an alloy and a dopant having a profile. The profile includes a retrograde region residing on the collector side of the compound base region.

Abstract: A semiconductor device is provided comprising an oxide layer over a first silicon layer and a second silicon layer over the oxide layer, wherein the oxide layer is between the first silicon layer and the second silicon layer. The first silicon layer and the second silicon layer comprise the same crystalline orientation. The device further includes a graded germanium layer on the first silicon layer, wherein the graded germanium layer contacts a spacer and the first silicon layer and does not contact the oxide layer. A lower portion of the graded germanium layer comprises a higher concentration of germanium than an upper portion of the graded germanium layer, wherein a top surface of the graded germanium layer lacks germanium.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in stresses may reduce defect formation and cracking in the gallium nitride material region, as well as reducing warpage of the overall structure. The gallium nitride material-based semiconductor structures may be used in a variety of applications such as transistors (e.g. FETs) Schottky diodes, light emitting diodes, laser diodes, SAW devices, and sensors, amongst others devices.

Abstract: A planar avalanche photodiode includes a small localized contact layer on the top of the device produced by either a diffusion or etching process and a semiconductor layer defining a lower contact area. A semiconductor multiplication layer is positioned between the two contact areas and a semiconductor absorption layer is positioned between the multiplication layer and the upper contact layer. The photodiode has a low capacitance and a low field near the edges of the semiconductor multiplication and absorption layers.

Abstract: A non-volatile memory cell includes an upper electrode; a lower electrode and a state-variable region, in which a conductive state changes only once. The state variable region is formed in a region between the upper electrode and the lower electrode. The state-variable region comprises a first semiconductor layer of a first conductive type; and second semiconductor layers of a second conductive type, opposing to the first conductive type, which are formed on upper and lower surfaces of the first semiconductor layer via PN junctions.

Abstract: The present invention includes a planar avalanche photodiode having a first n-type semiconductor layer defining a planar contact area, and a second n-type semiconductor layer having a p-type diffusion region. Further features of the structure includes an n-type semiconductor multiplication layer, an n-type semiconductor absorption layer, and a p-type contact layer. Further embodiments include a planar avalanche photodiode having a first n-type semiconductor layer defining a planar contact area, an n-type semiconductor multiplication layer, an n-type semiconductor absorption layer and a p-type semiconductor layer electrically coupled to a p-type contact layer.

Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1?100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11?20> direction lying in a range of 0.00 degree to 0.06 degree.

Abstract: Semiconductor devices such as VCSELs, SELs, LEDs, and HBTs are manufactured to have a wide bandgap material near a narrow bandgap material. Electron injection is improved by an intermediate structure positioned between the wide bandgap material and the narrow bandgap material. The intermediate structure is an inflection, such as a plateau, in the ramping of the composition between the wide bandgap material and the narrow bandgap material. The intermediate structure is highly doped and has a composition with a desired low electron affinity. The injection structure can be used on the p-side of a device with a p-doped intermediate structure at high hole affinity.

Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.

Abstract: A composition, comprising organic polymer molecules, and organic nonpolymeric molecules, wherein the composition is a semiconducting solid. The composition includes a distribution of crystal domains of the polymer molecules and inter-domain regions between the crystal domains, a concentration of polymer molecules being higher in the crystal domains than in the inter-domain regions, and a concentration of nonpolymeric molecules being higher in the inter-domain regions than in the crystal domains.

Abstract: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.

Abstract: An image pickup device including an array of a plurality of pixels including photoelectric conversion portions for accumulating signal charges generated by photoelectric conversion and an amplifying transistor for amplifying the signal charges generated by the photoelectric conversion portion to output the amplified signal charges, the device comprising: a junction-type field effect transistor, including a main electrode made of first semiconductor region of a first conduction type connected to control electrode region of the amplifying transistor, and a control electrode region made of second semiconductor region of a second conductive type opposite to the first conductivity type having same electric potential as that of semiconductor region of the second conduction type included in a semiconductor region forming the photoelectric conversion portions; and an electric potential supplying circuit for supplying predetermined electric potential to the main electrode regions of the a junction-type field effect tr

Abstract: An optical device with a quantum well is provided. The optical device includes an active layer made of a Group III-V semiconductor compound and having a quantum well of a bandgap grading structure in which conduction band energy and valence band energy change linearly with a slope with the content change of predetermined components while an energy bandgap between the conduction band energy and the valence band energy is maintained at a predetermined value; and two barrier layers, one of which is positioned on an upper surface of the active layer and the other is positioned on a lower surface of the active layer, and which are made of a Group III-V semiconductor compound and have higher conduction band energy and lower valence band energy than the active layer. A driving voltage is decreased and luminous efficiency and reliability are enhanced.

Abstract: A multiple channel transistor provides a transistor with an improved drive current and speed by using tunable hot carrier effects. A thin gate oxide has a carrier confinement layer formed on top thereof. Holes produced by hot carrier effects are retained by the carrier confinement layer directly above the gate oxide layer. The holes switch on the bottom transistor of the multi-channel transistor, thereby increasing the drive current.

Abstract: In order to reduce dislocation pile-ups in a virtual substrate, a buffer layer 32 is provided, between an underlying Si substrate 34 and an uppermost constant composition SiGe layer 36, which comprises alternating graded SiGe layers 38 and uniform SiGe layers 40. During the deposition of each of the graded SiGe layers 38 the Ge fraction x is linearly increased from a value corresponding to the Ge composition ratio of the preceding layer to a value corresponding to the Ge composition ratio of the following layer. Furthermore the Ge fraction x is maintained constant during deposition of each uniform SiGe layer 40, so that the Ge fraction x varies in step-wise fashion through the depth of the buffer layer. After the deposition of each pair of graded and uniform SiGe layers 38 and 40, the wafer is annealed at an elevated temperature greater than the temperature at which the layers have been deposited.

Abstract: An assembly comprising a semiconductor substrate having a first lattice constant, an intermediate layer having a second lattice constant formed on the semiconductor substrate, and a virtual substrate layer having a third lattice constant formed on the intermediate layer. The intermediate layer comprises one of a combination of III–V elements and a combination of II–VI elements. The second lattice constant has a value that is approximately between the values of the first lattice constant and the third lattice constant.

Abstract: A thin film transistor formed by using a Metal Induced Lateral Crystallization process and method for fabricating the same. The thin film transistor comprises an active layer having source/drain regions and a channel region, a gate electrode, an insulating layer having contact holes for exposing a portion of each of the source/drain regions, and a crystallization inducing pattern exposing a portion of the active layer. The source/drain electrodes are coupled to the source/drain regions through the contact holes, and the crystallization inducing pattern does not couple the source/drain regions to the source/drain electrodes.

Abstract: A semiconductor device exhibiting interband tunneling with a first layer with a first conduction band edge with an energy above a first valence band edge, with the difference a first band-gap. A second layer with second conduction band edge with an energy above a second valence band edge, with the difference a second band-gap, and the second layer formed permitting electron carrier tunneling transport. The second layer is between the first and a third layer, with the difference between the third valence band edge and the third conduction band edge a third band-gap. A Fermi level is nearer the first conduction band edge than the first valence band edge. The second valence band edge is beneath the first conduction band edge. The second conduction band edge is above the third valence band edge. The Fermi level is nearer the third valence band edge than to the third conduction band edge.

Abstract: An n-type buffer layer composed of n-type GaN, an n-type cladding layer composed of n-type AlGaN, an n-type optical confinement layer composed of n-type GaN, a single quantum well active layer composed of undoped GaInN, a p-type optical confinement layer composed of p-type GaN, a p-type cladding layer composed of p-type AlGaN, and a p-type contact layer composed of p-type GaN are formed on a substrate composed of sapphire. A current blocking layer formed in an upper portion of the p-type cladding layer and on both sides of the p-type contact layer to define a ridge portion is composed of a dielectric material obtained by replacing some of nitrogen atoms composing a Group III–V nitride semiconductor with oxygen atoms.

Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness direction than in an upper portion and in a lower portion.

Abstract: A group-III nitride semiconductor stack comprises a single-crystal substrate, a first group-III nitride layer formed on a principal surface of the single-crystal substrate, a graded low-temperature deposited layer formed on the group-III nitride layer and made of nitride in which group-III element composition is continuously changed, and a second group-III nitride layer formed on the graded low-temperature deposited layer.

Abstract: A semiconductor structure having a substrate with a surface layer including strained silicon. The surface layer has a first region with a first thickness less than a second thickness of a second region. A gate dielectric layer is disposed over a portion of at least the first surface layer region.