Abstract: An electronic device includes a substrate, a transistor and a doped well. The substrate includes a first region and a second region different from the first region. The transistor is disposed on the first region of the substrate. The transistor includes a first nitride semiconductor layer disposed on the substrate, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer. The second nitride semiconductor layer has a bandgap greater than that of the first nitride semiconductor layer. The doped well is disposed in the second region.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Abstract: A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; a control electrode provided inside a trench of the semiconductor part; a third electrode provided inside the trench; a diode element provided at the front surface of the semiconductor part; a resistance element provided on the front surface of the semiconductor part via an insulating film, the diode element being electrically connected to the second electrode; a first interconnect electrically connecting the diode element and the resistance element, the first interconnect being electrically connected to the third electrode; and a second interconnect electrically connecting the resistance element and the semiconductor part. The resistance element is connected in series to the diode element. The diode element is provided to have a rectifying property reverse to a current direction flowing from the resistance element to the second electrode.

Abstract: A control circuit applied in a specific element and including a first transistor and an electrostatic discharge (ESD) protection circuit is provided. The specific element has a III-V semiconductor material and includes a control electrode, a first electrode and a second electrode. The first transistor is coupled between the first electrode and the second electrode and has the III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. In response to an ESD event, the ESD protection circuit provides a discharge path to release the ESD current from the control electrode to the second electrode.

Abstract: An electronic device can include a drain terminal, a control terminal, and a source terminal, a first HEMT, and a second HEMT. The first HEMT can include a drain electrode coupled to the drain terminal, a gate electrode coupled to the first control terminal, and a source electrode coupled to the source terminal. The second HEMT can include a drain electrode, a gate electrode, and a source electrode. The drain electrode can be coupled to the drain terminal, and the source electrode can be coupled to the source terminal. In an embodiment, a resistor can be coupled between the gate and source electrodes of the second HEMT, and in another embodiment, the gate electrode of the second HEMT can electrically float. During or after a triggering event, the second HEMT can turn on temporarily to divert some of the charging from the triggering event into the second HEMT.

Abstract: A method and a sensor for detecting or measuring at least one specific component among a plurality of components present in a gaseous or liquid mixture by a sensor having at least one capturing cell with a high-electron mobility transistor including a source and a drain with a grid inserted between the source and the drain, a voltage being applied between the source and the drain, and a current intensity in the capturing cell being recorded. The voltage between the source and the drain is controlled, which varies the intensity of the current, the voltage being controlled according to a voltage model predetermined by experience in order to provide a profile with an intensity which is characteristic of said at least one specific component.

Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

Abstract: A method of fabricating a field-effect transistor in which a native oxide layer is removed prior to etching a gate recess. The cleaning step ensures that the etch of the gate recess starts at the same time across an entire sample, such that a uniform gate recess depth and profile can be achieved across an array of field-effect transistors. This results in a highly uniform switch-off voltage for the field-effect transistors in the array.

Abstract: A semiconductor structure including a group III-N semiconductor material is disposed on a silicon substrate. A group III-N transistor structure is disposed on the group III-N semiconductor material. A well is disposed in the silicon substrate. The well has a first conductivity type. A doped region is disposed in the well. The doped region has a second conductivity type that is opposite to the first conductivity type. A first electrode is connected to the well of the second conductivity type and a second electrode is connected to the doped region having a first conductivity type. The well and the doped region form a PN diode. The well or the doped region is connected to the raised drain structure of the group III-N transistor.

Abstract: A semiconductor device, comprising a nitride semiconductor layer, a switching element, and a driving transistor; the switching element comprises: a first portion of a first electrode formed on the nitride semiconductor layer; a second electrode formed on the nitride semiconductor layer; and a first control electrode formed on the nitride semiconductor layer and located between the first portion of the first electrode and the second electrode; the driving transistor comprises: a second portion of the first electrode formed on the nitride semiconductor layer and connecting the first portions of the adjacent first electrodes to each other; a third electrode formed on the nitride semiconductor layer and transmitting a signal to the first control electrode; and a second control electrode formed on the nitride semiconductor layer and located between the second portion of the first electrode and the third electrode.

Abstract: An electronic device can include an enhancement-mode high electron mobility transistor (HEMT) that includes a source electrode; a drain electrode; and a gate. In an embodiment, the gate can correspond to spaced-apart gate electrodes and a space disposed between the spaced-apart gate electrodes, wherein the first space has a width configured such that, a continuous depletion region forms across all of the width of the first space. In another embodiment, the gate can be a gate electrode having a nonuniform thickness along a line in a gate width direction. In another aspect, a method of using the electronic device can include, during a transient period when the HEMT is in an off-state, flowing current from the drain electrode to the source electrode when Vds>?Vth+Vgs.

Abstract: In a semiconductor device having a heterojunction type superjunction structure, a drain portion and a source portion are electrically connected to one of a two-dimensional electron gas layer and a two-dimensional hole gas layer, and a gate portion is prevented by an insulating region from directly contacting the one of the two-dimensional election gas layer and the two-dimensional hole gas layer.

Abstract: Multiple degenerately-doped silicon layers are implemented within resonant structures to control multiple orders of temperature coefficients of frequency.

Abstract: Provided is a reconfigurable logic device using an electrochemical potential. The device includes first and second semiconductor channels, where an effective magnetic field direction of a channel is controlled by a current direction and which are spaced apart from each other, a first ferromagnetic gate contacting the first semiconductor channel and a second ferromagnetic gate contacting the second semiconductor channel, where a magnetization direction is controlled by a gate voltage, and a control unit configured to calculate a difference value corresponding to a difference between a first determination value and a second determination value, and compare the difference value with a reference value to determine an output value.

Abstract: The present application describes embodiments of a zero-power radio-frequency identification (RFID) sensor chip based on a combination of a surface acoustic wave (SAW) transducer and two-dimensional electron gas (2DEG) or two-dimensional holegas (2DHG) conducting structure, and its use as an ultrasensitive microphone for material and structure sensing. The SAW RFID sensor contains a piezoelectric substrate, on which a multilayer heterojunction structure is deposited. The heterojunction structure comprises at least two layers, a buffer layer and a barrier layer, wherein both layers are grown from III-V single-crystalline or polycrystalline semiconductor materials, such as Ga N/Al Ga N. Interdigitated transducers (IDTs) transducing SAWs are installed on top of the barrier layer.

Abstract: There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.

Abstract: A miniaturized semiconductor device including a transistor in which a channel formation region is formed using an oxide semiconductor film and variation in electric characteristics due to a short-channel effect is suppressed is provided. In addition, a semiconductor device whose on-state current is improved is provided. A semiconductor device is provided with an oxide semiconductor film including a pair of second oxide semiconductor regions which are amorphous regions and a first oxide semiconductor region located between the pair of second oxide semiconductor regions, a gate insulating film, and a gate electrode provided over the first oxide semiconductor region with the gate insulating film interposed therebetween. One or more kinds of elements selected from Group 15 elements such as nitrogen, phosphorus, and arsenic are added to the second oxide semiconductor regions.

Abstract: In accordance with an embodiment, semiconductor component having a compound semiconductor material based semiconductor device connected to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.

Abstract: In accordance with an embodiment, semiconductor component includes a compound semiconductor material based semiconductor device coupled to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.

Abstract: A semiconductor device according to an embodiment includes a normally-off transistor having a first drain, a first source electrically connected to a source terminal, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a voltage terminal, and a second gate electrically connected to the first source, a coil component provided between the voltage terminal and the second drain, and a first diode having a first anode electrically connected to the first drain and the second source, and a first cathode electrically connected to the coil component and the voltage terminal.

Abstract: A semiconductor device according to an embodiment includes a normally-off transistor having a first drain, a first source electrically connected to a source terminal, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second gate, a second source electrically connected to the first drain, and a second drain electrically connected to a voltage terminal, a first capacitor provided between the gate terminal and the second gate, a first diode having a first anode electrically connected to the first capacitor and the second gate, and a first cathode electrically connected to the first source, a coil component provided between the voltage terminal and the second drain, and a second diode having a second anode electrically connected to the first drain and the second source, and a second cathode electrically connected to the coil component and the voltage terminal.

Abstract: Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a material AlxInyGazN (0?x, y, z?1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0<z?1). A gate recess is disposed in a number of adjacent sublayers of the cap layer to achieve a desired threshold voltage for a transistor. Also described are methods for fabricating such semiconductor structures, where gate recesses and/or ohmic recesses are formed by selectively removing adjacent sublayers of the cap layer. The performance of the resulting integrated circuits is improved, while providing design flexibility to reduce production cost and circuit footprint.

Abstract: In one implementation, a group III-V and group IV composite switch includes a group IV transistor in a lower active die, the group IV transistor having a source and a gate situated on a bottom side of the lower active die. The group III-V and group IV composite switch also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a drain of the group IV transistor using a through-semiconductor via (TSV) of the upper active die.

Abstract: In one implementation, a stacked composite device comprises a group IV vertical transistor and a group III-V transistor stacked over the group IV vertical transistor. A drain of the group IV vertical transistor is in contact with a source of the group III-V transistor, a source of the group IV vertical transistor is coupled to a gate of the group III-V transistor to provide a composite source on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on a top side of the stacked composite device. A gate of the group IV vertical transistor provides a composite gate on the top side of the stacked composite device.

Abstract: A semiconductor structure includes a semiconductor layer that is passivated with an aluminum-silicon nitride layer. When the semiconductor layer in particular comprises a III-V semiconductor material such as a group III nitride semiconductor material or a gallium nitride semiconductor material, the aluminum-silicon nitride material provides a superior passivation in comparison with a silicon nitride material.

Abstract: There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a semiconductor on insulator (SOI) substrate including a diode and an insulator layer. The composite semiconductor device also includes a transition body formed over the diode, and a transistor formed over the transition body. The diode is connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two.

Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel layer; a channel supply layer on the channel layer; a source electrode and a drain electrode spaced apart from each other on one of the channel layer and the channel supply layer; a gate electrode on a part of the channel supply layer between the source electrode and the drain electrode; a first depletion-forming layer between the gate electrode and the channel supply layer; and a at least one second depletion-forming layer on the channel supply layer between the gate electrode and the drain electrode. The at least one second depletion-forming layer is electrically connected to the source electrode.

Abstract: There are disclosed herein various implementations of a monolithically integrated component. In one exemplary implementation, such a monolithically integrated component includes an enhancement mode group IV transistor and two or more depletion mode III-Nitride transistors. The enhancement mode group IV transistor may be implemented as a group IV insulated gate bipolar transistor (group IV IGBT). One or more of the III-Nitride transistor(s) may be situated over a body layer of the group IV IGBT, or the III-Nitride transistor(s) may be situated over a collector layer of the IGBT.

Abstract: An embodiment of a cascaded diode having a breakdown voltage exceeding 300V includes an HEMT and a Si Schottky diode. The HEMT includes a gate, a drain, a source, and a two-dimensional electron gas channel region connecting the source and the drain and controlled by the gate. The HEMT has a breakdown voltage exceeding 300V. The Si Schottky diode is monolithically integrated with the HEMT. The Si Schottky diode includes a cathode connected to the source of the HEMT and an anode connected to the gate of the HEMT. The Si Schottky diode has a breakdown voltage less than 300V and a forward voltage less than or equal to 0.4V. The anode of the Si Schottky diode forms the anode of the cascaded diode and the drain of the HEMT forms the cathode of the cascaded diode.

Abstract: A compound semiconductor device includes a substrate, a p-type first semiconductor layer over the substrate and contains antimony, a p-type second semiconductor layer over the first semiconductor layer and contains antimony, an n-type third semiconductor layer over the second semiconductor layer, a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer containing phosphorus and having a thickness in which electrons tunnel between the first semiconductor layer and the second semiconductor layer, a first electrode in ohmic contact with the first semiconductor layer, and a second electrode in ohmic contact with the third semiconductor layer. The first semiconductor layer is made from a material whose contact resistance with the first electrode is lower than contact resistance of the second semiconductor layer.

Abstract: A method for fabricating a photovoltaic device includes forming a first contact on a crystalline substrate, by epitaxially growing a first doped layer having a doping concentration of 1019 cm?3 or greater, a dislocation density of 105 cm?2 or smaller, a hydrogen content of 0.1 atomic percent or smaller, and a thickness configured to reduce Auger recombination in the epitaxially grown doped layer. A first passivation layer is formed on the first doped layer. A second contact is formed on the crystalline substrate on a side opposite the first contact by epitaxially growing a second doped layer having a doping concentration of 1019 cm?3 or greater, a dislocation density of 105 cm?2 or smaller, a hydrogen content of 0.1 atomic percent or smaller and a thickness configured to reduce Auger recombination in the second epitaxially grown doped layer. A second passivation layer is formed on the second doped layer.

Abstract: There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches.

Abstract: A transistor device includes a compound semiconductor body, a normally-on high electron mobility field effect transistor (HEMT) formed in the compound semiconductor body and a protection device monolithically integrated in the same compound semiconductor body as the normally-on HEMT. The normally-on HEMT has a source, a drain, a gate, and a threshold voltage. The protection device has a source and a drain each shared with the normally-on HEMT, a gate and a positive threshold voltage that is less than a difference of the threshold voltage of the normally-on HEMT and a gate voltage used to turn off the normally-on HEMT. The protection device is operable to conduct current in a reverse direction when the normally-on HEMT is switched off. A transistor device including a normally-off HEMT and a monolithically integrated protection device is also provided.

Abstract: A semiconductor device is provided that includes a composite semiconductor body including a high voltage depletion-mode transistor and a low voltage enhancement-mode transistor. The high voltage depletion-mode transistor is stacked on the low voltage enhancement-mode transistor so that an interface is formed between the high voltage depletion-mode transistor and the low voltage enhancement-mode transistor. The low voltage enhancement-mode transistor includes a current path coupled in series with a current path of the high voltage depletion-mode transistor, and a control electrode is arranged at the interface.

Abstract: A semiconductor device of the invention includes an n-GaN layer provided on a substrate, a channel layer provided in contact with the upper surface of the n-GaN layer, an electron supply layer which is provided on the channel layer, and a gate electrode, a source electrode, and a drain electrode which are provided on the electron supply layer. The gate electrode is in contact with an underlying layer made from a nitride semiconductor. The semiconductor device has a ratio defined by the equation L/d1?7, where L is the width of the gate electrode in contact with the underlying layer in a direction between the source electrode and drain electrode; and d1 is the distance between a surface of the n-type gallium nitride layer and a boundary between the gate electrode and the underlying layer.

Abstract: A semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a field effect transistor having a semiconductor layer on the upper surface of the semiconductor substrate, a gate electrode, a drain electrode, and a source electrode; a P-type diffusion region in the semiconductor substrate and extending to the upper surface of the semiconductor substrate; a first N-type diffusion region in the semiconductor substrate and extending t the upper surface of the semiconductor substrate; a first connection electrode connecting the P-type diffusion region to a grounding point; and a second connection electrode connecting the first N-type diffusion region to the gate electrode or the drain electrode. The P-type diffusion region and the first N-type diffusion region constitute a bidirectional lateral diode.

Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.

Abstract: A device includes a semiconductor die. The semiconductor die includes a plurality of semiconductor layers disposed on a GaAs substrate, including a first semiconductor layer having a first band-gap and a second semiconductor layer having a second band-gap. The semiconductor die further includes a contact layer disposed epitaxially upon the first semiconductor layer. The contact layer has a thickness that is less than a critical thickness. The second semiconductor layer is epitaxially disposed upon the contact layer. The contact layer has a third band-gap that is less than the first band-gap and the second band-gap. The semiconductor die further includes a conductive layer disposed upon the contact layer to form an ohmic contact. The conductive layer comprises one or more metal layers compatible with silicon processing techniques.

Abstract: A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.

Abstract: The various embodiments of the present invention provide improved methods and circuits for generating millimeter-wave oscillations. Generating millimeter-wave oscillations may involve providing a semiconductor device comprising at least two terminals and a polar heterojunction formed from two semiconductor materials. A voltage bias may be applied to at least two terminals of the device in which the voltage enhances a two-dimensional electron gas (2DEG) layer at the polar heterojunction and produces a sharply-peaked but spatially-localized electric field within the 2DEG with a large longitudinal component, wherein the longitudinal component of the electric field serves as a nucleation site for a plurality of propagating dipole domains observable as a plurality of self-sustaining millimeter-wave oscillations.

Abstract: There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.

Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.

Abstract: A compound semiconductor device includes a substrate, a p-type first semiconductor layer over the substrate and contains antimony, a p-type second semiconductor layer over the first semiconductor layer and contains antimony, an n-type third semiconductor layer over the second semiconductor layer, a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer containing phosphorus and having a thickness in which electrons tunnel between the first semiconductor layer and the second semiconductor layer, a first electrode in ohmic contact with the first semiconductor layer, and a second electrode in ohmic contact with the third semiconductor layer. The first semiconductor layer is made from a material whose contact resistance with the first electrode is lower than contact resistance of the second semiconductor layer.

Abstract: A transistor with source and drain electrodes formed in contact with an active region and a gate between the source and drain electrodes and in contact with the active region. A first spacer layer is on at least part of the active region surface between the gate and drain electrodes and between the gate and source electrodes. The gate comprises a generally t-shaped top portion that extends toward the source and drain electrodes. A field plate is on the spacer layer and under the overhang of at least one section of the gate top portion. The field plate is at least partially covered by a second spacer layer that is on at least part of the first active layer surface and between the gate and drain and between the gate and source. At least one conductive path electrically connects the field plate to the source electrode or the gate.

Abstract: A semiconductor device according to one embodiment is provided with a first metal substrate, a second metal substrate separated from the first metal substrate, a normally-off transistor of a silicon semiconductor provided on the first metal substrate, and a normally-on transistor of a nitride semiconductor provided on the second metal substrate.

Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.

Abstract: An embodiment of a cascaded diode having a breakdown voltage exceeding 300V includes an HEMT and a Si Schottky diode. The HEMT includes a gate, a drain, a source, and a two-dimensional electron gas channel region connecting the source and the drain and controlled by the gate. The HEMT has a breakdown voltage exceeding 300V. The Si Schottky diode is monolithically integrated with the HEMT. The Si Schottky diode includes a cathode connected to the source of the HEMT and an anode connected to the gate of the HEMT. The Si Schottky diode has a breakdown voltage less than 300V and a forward voltage less than or equal to 0.4V. The anode of the Si Schottky diode forms the anode of the cascaded diode and the drain of the HEMT forms the cathode of the cascaded diode.

Abstract: There are disclosed herein various implementations of a monolithic vertically integrated composite device. Such a composite device may include one or more group IV device fabricated in a group IV semiconductor body formed over a first side of a double sided substrate, and one or more group III-V device fabricated in a group III-V semiconductor body formed over a second side of the double sided substrate opposite the first side. In one implementation, the one or more group IV device may be a PN junction diode or a Schottky diode. In another implementation, the one or more group IV device may be a field-effect transistor (PET). In yet another implementation, such a composite device monolithically integrates one or more group III-V device and a group IV integrated circuit (IC). The one or more group III-V device and one or more group IV device and/or IC may be electrically coupled using one or more of a substrate via and a through-wafer via.

Abstract: A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

Abstract: A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The method of manufacturing the semiconductor device further includes the third step of epitaxially growing, on the surface of the dug-down portion of the silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from the silicon substrate side toward the surface of the mixed crystal layer.