Abstract: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.

Abstract: Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors and integrated circuitry coupled to the image sensors. The method further includes providing a spacer having a web that includes an adhesive and has openings arranged to be aligned with the image sensors. For example, the web can be a film having an adhesive coating, or the web itself can be a layer of adhesive. The method continues by assembling the imager workpiece with the cover substrate such that (a) the spacer is between the imager workpiece and the cover substrate, and (b) the openings are aligned with the image sensors. The attached web is not cured after the imager workpiece and the cover substrate have both been adhered to the web.

Abstract: By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain.

Abstract: A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a sidewall insulating film formed on a side surface of the gate electrode, source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode, and second nickel silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is at least 1/10 of a peak concentration of arsenic contained in the source/drain layers.

Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.

Abstract: High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided.

Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

Abstract: A light sensor having a light conversion element between first and second electrodes is disclosed. The light conversion element includes a body of semiconductor material having first and second surfaces. The body of semiconductor material is of a first conductivity type and has doping elements in a concentration gradient that creates a first electrostatic field having a magnitude that varies monotonically from the first surface to the second surface. A bias circuit applies a variable potential between the first and second electrodes to create a second electrostatic field having a direction opposite to that of the first electrostatic field and a magnitude determined by the potential. One of the electrodes is transparent to light in a predetermined band of wavelengths. The body of semiconductor material can include an epitaxial body having a monotonically increasing concentration of a doping element as a function of the distance from one the surfaces.

Abstract: A solid state imaging device includes a transfer transistor for transferring signal charges generated by photoelectric conversion to a floating diffusion layer, a reset transistor for resetting a potential of the floating diffusion layer, and an amplifying transistor for outputting a signal corresponding to the potential of the floating diffusion layer. A low concentration impurity region having an impurity concentration lower than that of the first conductivity type semiconductor region is formed in part of a surface portion of the first conductivity type semiconductor region which is located below a gate electrode of the amplifying transistor and serves as a well region of the amplifying transistor.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: A non-volatile memory device having an asymmetric channel structure is provided.

Abstract: Crosstalk between the adjacent pixels can be prevented by a structure in which an overflow barrier is provided at the deep portion of a substrate. A partial P type region 150 is provided at the predetermined position of a lower layer region of the vertical transfer register 124 and a channel stop region 126. This P type region 150 is used to adjust potential in the lower layer region of the vertical transfer register 124 and the channel stop region 126 so that the potential may become smaller than that of the lower layer region of the photosensor 122 in a range from the minimum potential position of the vertical transfer register 124 to the overflow barrier 128. Accordingly, since the potential in the lower layer region of the vertical transfer register 124 and the channel stop region 126 at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.

Abstract: Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source.

Abstract: A solid-state image pickup device for preventing crosstalk between adjacent pixels by providing an overflow barrier at the deep potion of a substrate. A partial P type region is provided at the predetermined position of a lower layer region of the vertical transfer register and a channel stop region. This P type region adjusts potential in the lower layer region of the vertical transfer register and the channel stop region. Accordingly, since the potential in the lower layer region of the vertical transfer register and the channel stop region at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.

Abstract: A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric conversion unit, and temporarily accumulating charge generated in the photo-electric conversion unit, a charge hold region (barrier unit) formed in the N-type impurity region so as to contact with the charge accumulation unit, and allowing the charge accumulation unit to accumulate the charge, and a charge accumulating electrode provided to the charge accumulation unit. The charge accumulation unit and the charge hold region are formed to be N?-type.

Abstract: The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain extension (160) comprises an abnormal-angled dopant implantation (135) and a dopant implantation (145). The abnormal-angled dopant implantation (135) uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation (145) uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (105), wherein a portion (170) of the source/drain extension (160) is under the gate (120).

Abstract: High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided.

Abstract: An organic field-effect transistor and a method of making the same include a self-assembled monolayer (SAM) of bifunctional molecules disposed between a pair of electrodes as a channel material. The pair of electrodes and the SAM of bifunctional molecules are formed above an insulating layer, in which each of the bifunctional molecules comprises a functionality at a first end that covalently bonds to the insulating layer, and an end-cap functionality at a second end that includes a conjugated bond. The SAM of bifunctional molecules may be polymerized SAM to form a conjugated polymer strand extending between the pair of electrodes.

Abstract: Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.

Abstract: To provide a polishing composition whereby the stock removal rate of a silicon nitride layer is higher than the stock removal rate of a silicon oxide layer, there is substantially no adverse effect against polishing planarization, and a sufficient stock removal rate of a silicon nitride layer is obtainable, and a polishing method employing such a composition. A polishing composition which has silicon oxide abrasive grains, an acidic additive and water, wherein the acidic additive is such that when it is formed into a 85 wt % aqueous solution, the chemical etching rate of the silicon nitride layer is at most 0.1 nm/hr in an atmosphere of 80° C. Particularly preferred is one wherein the silicon oxide abrasive grains have an average particle size of from 1 to 50 nm, and the pH of the composition is from 3.5 to 6.5.

Abstract: A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.

Abstract: An insulated gate transistor has a semiconductor thin film having a first main surface and a second main surface, a first gate insulating film formed on the first main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type disposed in contact with the semiconductor thin film. A gate threshold voltage of the first conductive gate is controlled by a forward bias of the third semiconductor region with respect to one of the first and second semiconductor regions.

Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.

Abstract: The invention relates to an electrically programmable memory cell comprising a memory transistor having a source and a drain zone and also a storage electrode and a control electrode, and a selection transistor having a source and a drain zone and also a control electrode, the drain zones of the storage and selection transistors being electrically conductively connected to one another. In this case, the drain zone of the selection transistor has a connection zone and an intermediate zone doped more weakly than the connection zone, the intermediate zone being arranged between the connection zone and a channel zone of the selection transistor and serving, during the programming operation, for taking up a programming voltage and thus for protecting a control electrode insulation layer of the selection transistor.

Abstract: Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.

Abstract: A charge transfer element comprising a reverse conductive type well formed on the surface of one conductive type semiconductor substrate, the one conductive type channel region extending in one direction relative to the well, a transfer electrode formed intersecting the channel region, a floating diffusion region formed continuous from the channel region, and an output transistor having a gate connected to the floating diffusion region. In a region where the output transistor is formed, the dopant density profile in the depth direction of the semiconductor substrate exhibits the maximum value relative to a middle region.

Abstract: Electron emitters and a method of fabricating emitters are disclosed, having a concentration gradient of impurities, such that the highest concentration of impurities is at the apex of the emitters and decreases toward the base of the emitters. The method comprises the steps of doping, patterning, etching, and oxidizing the substrate, thereby forming the emitters having impurity gradients.

Abstract: The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor device 200 includes a gate 244 located over a substrate 210, the substrate 210 having a source and a drain 230 located therein. In the same embodiment, located adjacent each of the source and drain 230 are localized halo implants 250, each of the localized halo implants 250 having a vertical implant region 260 and an angled implant region 265. Further, at an intersection of the vertical implant region 260 and the angled implant region 265 is an area of peak concentration.

Abstract: In order to suppress variations in the set currents of a plurality of constant current circuits, there is provided a processing apparatus having a constant current supply unit including a plurality of constant current circuits, a plurality of sample/hold circuits for sampling/holding current values for maintaining currents supplied from the constant current circuits constant, and a constant current source for supplying a reference current for setting a current value to the plurality of sample/hold circuits.

Abstract: The present invention relates to a method for fabricating a complementary metal oxide semiconductor (CMOS) image sensor, wherein a mini-p-well is stably formed in a pixel region being correspondent to a trend of large scale of integration. The method includes the steps of: preparing a substrate defined with a peripheral region and a pixel region; performing a first ion-implantation process by using a first photoresist having a first thickness to thereby form a normal first conductive well in the pixel region; and performing a second ion-implantation process by using a second photoresist having a second thickness to thereby form a mini-well of the first conductive type in the peripheral region, wherein the first thickness is greater than the second thickness.

Abstract: An insulated gate transistor is comprised of a semiconductor thin film, a first gate insulating film formed on a main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film. The insulated gate transistor is controlled by injecting carriers of the second conductivity type into the semiconductor thin film from the third semiconductor region, and thereafter applying a first electric potential to the first conductive gate to form a channel of the first conductivity type on a portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region.

Abstract: In a photoelectric conversion device comprising a first-conductivity type first semiconductor region located in a pixel region, a second-conductivity type second semiconductor region provided in the first semiconductor region, and a wiring for electrically connecting the second semiconductor region to a circuit element located outside the pixel region, a shield is provided on the light-incident side of the wiring, via an insulator in such a way that it covers at least part of the wiring and also the shield comprises a conductor whose potential stands fixed. This photoelectric conversion device may hardly be affected with low-frequency radiated noises as typified by power-source noise.

Abstract: An NMOS field effect transistor (1) is made radiation hard by a pair of guard band implants (115) of limited horizontal extent, extending between the source (30A) and drain (30B) along the edge of the transistor body, and extending only to a limited extent into the field insulator and into the interior of the transistor, leaving an unimplanted area in the center of the body that retains the transistor design threshold voltage.

Abstract: A MOSFET semiconductor device having an asymmetric channel region between the source region and the drain region. In one embodiment, the device comprises a mesa structure on a silicon substrate with the source region being in the substrate and the mesa structure extending from the source region and substrate. The asymmetric channel region can include silicon abutting the source region and a heterostructure material such as Si1-xGex extending to and abutting the drain region. The mole fraction of Ge can increase towards the drain region either uniformly or in steps. In one embodiment, the doping profile of the channel region is non-uniform with higher doping near the source region and lower doping near the drain region.

Abstract: A semiconductor device having a semiconductor layer, includes: a first impurity atom having a covalent bond radius larger than a minimum radius of a covalent bond of a semiconductor constituent atom of a semiconductor layer; and a second impurity atom having a covalent bond radius smaller than a maximum radius of the covalent bond of the semiconductor constituent atom; wherein the first and second impurity atoms are arranged in a nearest neighbor lattice site location and at least one of the first and second impurity atoms is electrically active.

Abstract: Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies between different layers of a multiple layer device. In a preferred embodiment, the variations are such that the field strength is substantially constant along any horizontal or vertical cross section of the termination region.

Abstract: The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type. In order to obtain a drift field in the channel below one or more gates (9, 10a) to improve the charge transfer, the well is provided with a doping profile, so that the average concentration decreases in the direction of charge transport. Such a profile can be formed by covering the area of the well during the well implantation with a mask, thereby causing fewer ions to be implanted below the gates (9, 10a) than below other parts of the channel. By virtue of the invention, it is possible to produce a gate (10a) combining a comparatively large length, for example in the output stage in front of the output gate (9) to obtain sufficient storage capacity, with a high transport rate.

Abstract: In a complete depletion type SOI transistor, the roll-off of a threshold value is suppressed, independently from the formation of an SOI film to be thinner. As for a semiconductor device (1), the impurity concentration in a channel formation portion (10) is implanted not uniformly along the length direction of a gate (2) in the complete depletion type silicon on insulation (SOI) transistor. In other words, high concentration regions (11) where impurity concentrations are higher than that at a central portion in the end parts of the channel formation portion (10) on the side of a source (4) and a drain (5).

Abstract: There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.

Abstract: A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the trench photosensor.

Abstract: An image sensor capable of preventing the degradation of pinned photodiodes and the generation of leakage current between neighboring pinned photodiodes is provided. The disclosed image sensor contains a plurality of pixel units, each pixel unit having a photodiode region. The image sensor includes a semiconductor substrate of a first conductivity type; a device isolation layer formed in the semiconductor substrate; a field stop layer formed beneath the device isolation layer; a trench formed in the semiconductor substrate, wherein the trench surrounds the photodiode region; a first doping region of the first conductivity type formed beneath the surface of the semiconductor substrate and beneath the surfaces of the trench; an insulating member filling the trench; and a second doping region of a second conductivity type formed in the semiconductor substrate under the first doping region.

Abstract: The junction insulated lateral MOSFET is suitable for high/low side switches. A p-conductive wall between an n-conductive source zone and an n-conductive drain zone, together with the source zone and drain zone, extend to an n-conductive substrate. The source zone and the drain zone are surrounded by a p-conductive area.

Abstract: A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with an impurity to increase free carrier conductivity. The source region and the drain region are heavily doped with the impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and each are fabricated of a metal with an energy gap greater than silicon to form Schottky junctions with the channel region.

Abstract: A field effect transistor is disclosed having a relatively high doped region (of the same type dopant as the channel) to reduce the change in the depletion region within the channel with changes in the drain voltage (Vd). Changes in the drain current (Id) with changes in the drain voltage (Vd) is a cause of non-linearity for traditional MOSFET. Because of the additional higher doped region provided in the channel, the depletion region within the higher doped region changes less with changes in the drain voltage (Vd). The higher doped region is situated near the top of the channel, where most of the drain current flows. Thus, the higher doped region dominates the drain current through the device. Since the drain current is less susceptible to changes in drain voltage (Vd), a more linear device results.

Abstract: There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.

Abstract: A power semiconductor module comprises a circuit board made of an insulating substrate of good thermal conductivity formed with interconnect patterns, a plurality of power semiconductor chips mounted on the circuit board, bonding wires for electrically connecting the semiconductor chips and the interconnect patterns, outer lead terminals fixed to the interconnect patterns, and a resin layer for covering at least the chip mounted surface of the circuit board in its entirety so that the tip of each of the outer lead terminals is exposed.

Abstract: A charge transfer device has a charge transfer region under charge transfer electrodes for stepwise conveying charge packets through potential wells to a floating diffusion region, and the charge transfer region has a boundary sub-region contracting toward the floating diffusion region, wherein the final potential well is created at a certain portion in said boundary sub-region close to the floating diffusion region so that each charge packet travels over a short distance, thereby enhancing a charge transfer efficiency.

Abstract: A semiconductor device having a dual gate wherein impurities implanted into one gate region are prevented from reaching the other gate region and diffusing there. A wide gate separating region is secured between a p+ gate region and an n+ gate region. This gate separating region is a non-doped polysilicone region in which impurities such as B, P, and As are not implanted. Therefore, the probability that impurities existing in one gate region may reach the other gate through a gate electrode metal film is extremely low. Consequently, the characteristics of the semiconductor device are maintained in excellent condition.

Abstract: In a solid-state image pickup device, a transfer register 10 is provided with an overflow control gate OFCG and an overflow drain OFD, and the gate electrode 12A of the overflow control gate OFCG is formed so as to be superposed on the lower-layer electrodes St1, 13 of the transfer register 10 side the overflow drain OFD side.

Abstract: There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.