Abstract: A data driving apparatus for a liquid crystal display includes a plurality of data driving integrated circuits adjacent to a liquid crystal display panel for converting input pixel data into pixel voltage signals, one or more multiplexor arrays provided adjacent to the liquid crystal display panel to make a time-division of a plurality of data lines into a plurality of regions to selectively apply the pixel voltage signals from the plurality of data driving integrated circuits to the plurality of data lines.

Abstract: A magnetic sensor apparatus includes a semiconductor substrate and a magnetic impedance device for detecting a magnetic field. The magnetic impedance device is disposed on the substrate. The magnetic sensor apparatus has minimum size and is made with low manufacturing cost. Here, the magnetic impedance device detects a magnetic field in such a manner that impedance of the device is changed in accordance with the magnetic filed when an alternating current is applied to the device and the impedance is measured by an external electric circuit.

Abstract: In an embodiment, an apparatus includes a first field effect transistor including a first source contact region, a first drain contact region and a first plurality of fins overlying a substrate, a first gate overlying the first plurality of fins, the first source contact region coupled to first ends of the first plurality of fins, and a second field effect transistor including a second source contact region, a second drain contact region, and a second plurality of fins overlying the substrate, a second gate overlying the second plurality of fins, and an interconnection contact region overlying the substrate, electrically coupling the first drain contact region and the second source contact region and abutting the first and the second pluralities of fins.

Abstract: A semiconductor memory device includes memory cells, first wirings, a first current driver circuit, and a second current driver circuit. The memory cell includes a magneto-resistive element having a first ferromagnetic film, an insulating film formed on the first ferromagnetic film, and a second ferromagnetic film formed on the insulating film. The first wiring is provided in close proximity to and insulated from the magneto-resistive element. The first current driver circuit supplies a first current to the first wiring in a write operation to produce a magnetic field around the magneto-resistive elements. The second current driver circuit supplies a second current between the first and second ferromagnetic films via the insulating film in a write and a read operation.

Abstract: A ferroelectric capacitor circuit for sensing hydrogen gas having a closed integrated circuit package, a ferroelectric capacitor within the closed integrated circuit package, the ferroelectric capacitor having a bismuth oxide based ferroelectric layer being able to absorb hydrogen gas that is within the closed integrated circuit package, absorbed hydrogen gas chemically reducing a portion of the bismuth oxide based ferroelectric layer into bismuth metal, the ferroelectric capacitor having a ferroelectric voltage, the ferroelectric voltage having a voltage strength, and means for measuring a decrease in the voltage strength of the ferroelectric voltage of the ferroelectric capacitor.

Abstract: A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that includes a constricted current passage between the gate and the source/drain region.

Abstract: A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.

Abstract: A charge splitter for separating an incoming charge packet into two outgoing packets while the charge is in a static state, i.e., not while it is flowing down a channel or over a barrier. A splitting gate may have a biasing charge impressed upon it, such as via the application of voltage or current sources to opposite ends thereof, applying a bias to a semiconductor body portion of the gate structure, or by physically separate the splitting gate into multiple sections that each have different applied voltages or currents When discharge barrier gates are operated, different amounts of charge will thus flow to different output storage gates.

Abstract: In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns and at least two rows, and a gate dielectric layer surrounding each of the plurality of wire channels and a gate electrode surrounding the gate dielectric layer and each of the plurality of wire channels.

Abstract: A multiple channel transistor provides a transistor with an improved drive current and speed by using tunable hot carrier effects. A thin gate oxide has a carrier confinement layer formed on top thereof. Holes produced by hot carrier effects are retained by the carrier confinement layer directly above the gate oxide layer. The holes switch on the bottom transistor of the multi-channel transistor, thereby increasing the drive current.

Abstract: The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across the device. A pair of electrically interconnected diffusions are incorporated within the charge couple path to provide an amount of charge which can be added or subtracted from packets as the packets traverse the CCD.

Abstract: In a semiconductor device an electric field is controlled in direction or angle relative to a gate, or a channel to adjust a gain coefficient of a transistor. In some embodiments, there are provided a first gate forming a channel region in a rectangle or a parallelogram, and a second gate forming a channel region substantially containing a triangle between the channel region formed by the first gate and each of a source region and a drain region. In some embodiments, there is included a channel region formed by the first gate that is sandwiched by the channel region formed by the second gate, all the channel regions together substantially forming a rectangle or a parallelogram. As such, a semiconductor device allowing a gain coefficient ? of an MOS transistor to be modulated by voltage in an analog manner can readily be produced by conventional processing technology and incorporated into any conventional LSIs configured by a CMOS circuit.

Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.

Abstract: An adjustable charge coupled device (CCD) charge splitter includes a channel control structure and an associated plurality of output channels. Control signals applied to the channel control structure determine an amount of charge, which passes into each one of the plurality of output channels.

Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.

Abstract: An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the semiconductor substrate.

Abstract: A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.

Abstract: An image processing apparatus capable of acquiring a high resolution image without a reduction in sensitivity includes a plurality of sensor chips connected to one another, each sensor chip including a first pixel row and a second pixel row, which are formed on the same semiconductor chip. The first pixel row has a plurality of pixels arranged in the main scanning direction, and the second pixel row has a plurality of pixels shifted along the main scanning direction with respect to the first pixel row.

Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.

Abstract: P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.

Abstract: The dependency of threshold voltage on adjusted bias voltage is varied between an N-channel MOSFET and a P-channel MOSFET. A support substrate, an insulating layer disposed on the support substrate, and island-shaped first and second silicon layers separately formed on the insulating layer; a first MOSFET formed of a fully depleted SOI where a first channel part is formed in the first silicon layer; and a second MOSFET formed of a partially depleted SOI where a second channel part is formed in the second silicon layer, the second MOSFET configures a complementary MOSFET with the first MOSFET, are provided. The threshold voltage of the second MOSFET formed of the partially depleted SOI is hardly varied because of a neutral region disposed in the second channel part, even though bias voltage is applied to the support substrate to vary the threshold voltage of the first MOSFET formed of the fully depleted SOI.

Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.

Abstract: A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness.

Abstract: In a solid-state image pick-up device of FIG. 1, a plurality of photoelectric converting devices 100 having almost square light receiving regions are provided like a tetragonal grid over the surface of a semiconductor substrate and a plurality of vertical transfer sections 200 are provided corresponding to the respective photoelectric converting device strings respectively. The vertical transfer section 200 includes a vertical transfer channel and a plurality of vertical transfer electrodes provided on the upper layer of the vertical transfer channel, and the vertical transfer channel is provided in winding shape between the photoelectric converting devices 100 constituting the corresponding photoelectric converting device strings.

Abstract: P type well regions 31 and 32 are formed in N type well regions 21 and 22 respectively. The N type well regions 21 and 22 are formed separately each other. Charge transfer MOS transistors M2 and M3 are formed in the P type well regions 31 and 32 respectively. Thus, parasitic thyristor causing latch-up is nor formed.

Abstract: A local oscillation FET has a source connecting pad, a drain connecting pad and a gate connecting pad. The source connecting pad occupies one corner of a substrate, and the drain and gate connecting pads are placed at the neighboring corners so that the three connecting pads form an L shape on the substrate. As a modification to this configuration, another source connecting pad is placed at the remaining corner of the substrate so that the drain and gate connecting pads are shielded from each other by the two source connecting pads. These device configurations contribute to size reduction of the local oscillation FET.

Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 &mgr;m, and the spacing is not less than 3 &mgr;m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.

Abstract: A charge coupled device includes a plurality of photoelectric conversion regions; a plurality of vertical charge coupled devices (VCCDs) provided between the photoelectric conversion regions for transmission of charges generated at the photoelectric conversion regions in a first direction; and a horizontal charge coupled device (HCCD) coupled to the VCCDs and having a channel region including a plurality of channels for transmission of the charges previously transmitted through the VCCDs in a second direction. The channel region is formed such that one of the plurality of channels has a higher potential than the remaining channels. The remaining channels have potentials that gradually become lower than the highest potential moving in a direction away from the channel with the highest potential. The channel region transmits the charges within the HCCD so that the charges are gathered together centered around the channel having the highest potential during transmission of the charges.

Abstract: A charge coupled device has a hydrogen diffusion path to diffuse hydrogen to a silicon surface. The hydrogen diffusion path extends through a top silicon oxide layer that itself extends through a first aperture in a top silicon nitride layer. The first aperture overlays a conductor formed of polycrystalline silicon at a location that transversely overlays a channel stop. The hydrogen diffusion path extends through the conductor and through an extension of the conductor that itself extends through a second aperture in a lower silicon nitride layer. The lower silicon nitride layer being one part of a gate dielectric film. The gate dielectric film also includes a lower silicon oxide layer disposed between the lower silicon nitride layer and the silicon surface. The hydrogen diffusion path extends through the lower silicon oxide layer to reach the silicon surface.

Abstract: A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing electrode formed above the dielectric films, wherein the shape of a side wall of the insulating film includes a shape reflecting the outer peripheral shape of a side wall of the electrode facing the side wall of the insulating film. The semiconductor device of high integration, low cost and high reliability can be realized.

Abstract: A tunneling magnetoresistive storage unit (TMR unit) includes a hollow cylinder-shaped free-spin element having one open end, a columnlike fixed-spin element formed inside the cylinder-shaped free-spin element, and a thin insulator layer located between them. The spin direction in the fixed-spin element is fixed to a predefined circumferential direction of its column-shaped magnetic substance beforehand and a tunneling current is flowed between the free-spin element and the fixed-spin element. A rotating magnetic field produced as a consequence is used to set the spin direction in the cylinder-shaped free-spin element to one of its circumferential directions. This structure decreases the amount of electric current required for performing data write operation, also enabling miniaturization and a higher level of integration of the TMR unit and a magnetic random-access memory by employing such TMR units.

Abstract: The invention relates to a method of forming reduced feature size spacers. The method includes providing a semiconductor substrate having an area region; patterning a first spacer over a portion of the area region of the substrate, the first spacer having a first thickness and opposing side portions; patterning a pair of second spacers, each second spacer adjacent to a side portion of the first spacer, each second spacer having a second thickness in opposing side portions, wherein the second thickness is less than the first thickness; removing the first spacer; patterning a plurality of third spacers, each third spacer adjacent to one of the side portions of one of the second spacers, each one of the third spacers having a third thickness, wherein the third thickness is less than the second thickness; and removing the second spacers. The invention also relates to a field of effect transistor.

Abstract: In production of a solid-state image pickup device including a semiconductor substrate, a photoelectric converter element group including a plurality of photoelectric converter elements formed in one column in one surface of the semiconductor substrate, a charge transfer path to transfer signal charge accumulated in the photoelectric converter elements, and readout gates to read signal charge from photoelectric converter elements to feed the charge to the charge transfer path, an ON or ONO film electrically insulates each transfer electrode constituting the charge transfer path from the semiconductor substrate and an oxide insulating film insulates a readout gate electrode constituting the readout gate from the semiconductor substrate to thereby improve electric characteristics of the solid-state image pickup device.

Abstract: In the production of an IT-CCD including many photoelectric converters in columns and rows, vertical transfer CCDs for transferring signal charge accumulated in the photoelectric converters to a horizontal transfer CCD, and readout gate regions to control, for each photoelectric converter, readout operation of signal charge from the photoelectric converters to the vertical charge transfer CCDs; one joining channel is formed for each set of two vertical transfer CCDs to combine the CCDs with each other and hence a high-pixel-density solid-state image pickup device can be implemented using ordinary fine patterning technique.

Abstract: As solid-state image pickup devices are spread in the world, improvement of performance and reduction of the production cost thereof are required. It is difficult for the solid-state image pickup devices of a configuration of the prior art to meet the requirements. In a solid-state image pickup device to meet the requirements, a large number of photoelectric converters are disposed in a surface of a semiconductor substrate in of a matrix pattern having a plurality of row and a plurality of column, a vertical charge transfer channel is arranged for each column of the photoelectric converters, and a read-cum-transfer electrode is formed for each row of the photoelectric converters such that the read-cum-transfer electrode surrounds each photoelectric converter element of the associated row of the photoelectric converters in a plan view.

Abstract: A charge transfer device is provided which is capable of reducing a reset field-through noise in a stable manner without being affected by characteristics of transistors and without occurrence of a mustache-shaped pulse-like noise. The charge transfer device is made up of a floating diffusion region used to convert a signal charge transferred from a CCD (Charge Coupled Device) into a voltage, resetting unit used to eject the signal charge accumulated in the floating diffusion region in response to a reset pulse, a first stage source follower used to current-amplify the voltage and second stage source follower in which load is changed in response to the reset pulse and which is used to current-amplify an output voltage of the first stage source follower.

Abstract: By providing a semiconductor device including a charge transfer channel to one end of which electric charges supplied from a charge supply unit are input, and which includes a plurality of branching regions at an intermediate portion, a plurality of gate electrodes provided on the corresponding branching regions of the charge transfer channel via insulating films, an input-signal supply unit for supplying each of the gate electrodes with an input signal, a transfer electrode, provided on the charge transfer channel via a gate insulating film, for performing control so that the electric charges are transferred in a predetermined direction within the charge transfer channel, a conversion unit for coverting the transferred electric charges into a voltage, and a sense amplifier to which an output signal from the conversion unit is input, and by providing a semiconductor circuit which includes such a device, it is possible to reduce the scale of circuitry, increase the calculation speed, and reduce electric power

Abstract: A solid state image pickup device is provided, that improves the transfer efficiency of charges in the horizontal charge transfer path by implementing a selectively arranged matrix of semiconductor layers with differing conductivity type, impurity concentration and orientation. Further, the solid state image pickup device prevents the lowering of the transfer efficiency of charges transferred from the vertical charge transfer path to the horizontal charge transfer path.

Abstract: A method for forming a thin film transistor (TFT) is disclosed. The invention uses metal electroless plating or chemical displacement processes to form metal clusters adjacent the sidewall of amorphous silicon active region pattern so as to crystallize the amorphous silicon amid the subsequently performed metal induced lateral crystallization (MILC) process. The amorphous silicon is crystallized to form polysilicon having parallel grains. Since the amorphous silicon will crystallize with a specific angle which is measured between the grain orientation and the side wall of the amorphous silicon, a tilt channel connecting the source and drain region of the TFT is utilized to upgrade the electron mobility across the tilt channel, wherein the grain orientation of polysilicon in the tilt channel perpendicular to a gate electrode which is subsequently formed above the tilt channel.

Abstract: A charge transfer device which comprises vertical charge transfer devices which transfer charges in the vertical direction, first and second horizontal charge transfer devices which transfer the charges from the vertical charge transfer devices in the horizontal direction, and a shift gate which controls the charges from the vertical charge transfer devices to be supplied to one the first horizontal charge device or the second horizontal charge transfer device, wherein the first. horizontal charge transfer device is a semiconductor region between the vertical charge transfer devices and the second horizontal charge transfer device and includes highly-doped regions having tapered portions whose one ends near the second horizontal charge transfer device are broader than another ends near the vertical charge transfer devices.

Abstract: A process for producing a solid image pickup device is demanded that can enhance a photoelectric conversion region by forming an overflow barrier layer at a deep position and can prevents generation of radiation due to the use of resist as a mask. Upon producing a solid image pickup device having a vertical overflow drain structure, ion implantation is conducted on an entire of a silicon substrate without using a resist mask, so as to form an overflow barrier layer. It is also possible that a trench is formed in a peripheral part of the silicon substrate to surround a pixel region and to separate the overflow barrier layer into the pixel region and an outer peripheral part, and an impurity diffusion layer having a conductive type different from that of the overflow barrier layer is formed on an inner surface of the trench.

Abstract: A charge coupled device includes an integrated circuit substrate and a transfer circuit, in the integrated circuit substrate, that transfers charge signals in the charge coupled device to provide transferred charge signals. An amplifier, in the integrated circuit substrate and electrically coupled to the transfer circuit, amplifies the transferred charge signals to generate amplified charge signals. Related methods are also discussed.

Abstract: The invention relates to a microelectronics and more particularly to a bipolar static induction transistor.

Abstract: A plurality of first basic cells and a plurality of second basic cells are formed on a semiconductor substrate. A gate electrode of each of transistors in the first basic cell has a gate length of the minimum size. A gate electrode of each of transistors in the second basic cell has a second gate length larger than the first gate length. The transistors in the first basic cell are connected to each other, to construct a circuit which is operable at high speed and can be increased in integration density. The transistors in the second basic cell are connected to each other, to construct a circuit which can be reduced in power consumption and is hardly affected by process variations.

Abstract: In forming a photodiode by forming a burying layer on a charge accumulation region, the readout gate channel for the photodiode is separated from a high impurity concentration region of the burying layer of the photodiode, and at least a partial area of the high impurity concentration region is separated from the channel stopper region of the photodiode. Noises of a solid-state image pickup device using buried type photodiodes can be reduced.

Abstract: A CCD solid-state image sensing device has power supply lines formed from a poly-silicon layer and a silicide layer formed on the poly-silicon layer. The silicide layer has a reduced optical reflectivity that inhibits reflections of light on a surface of the power supply line. The silicide layer is silicon combined with a refractory metal, such as tungsten, molybdenum, titanium, or the like. Further, a surface protective film is formed on the power supply lines. The surface protective film includes silicon nitride having an increased quantity of hydrogen that is supplied to an interface between a channel layer and a diffusion layer in order to promote bonding.

Abstract: In a connection part of vertical transfer registers with respect to a horizontal transfer register, transfer electrodes to which clocks &phgr;V1, &phgr;V2A, &phgr;V3A, &phgr;V2B, &phgr;V3B, and &phgr;V1A are applied are arranged in the cited order. In a horizontal transfer register 6, transfer is conducted by 3-phase clocks &phgr;H1A, ØH1B, and &phgr;H2. By activating clocks, signal charges of a channel denoted by A-A′ and channels equivalent thereto are first transferred to undersides of electrodes of &phgr;H1A of the horizontal transfer register. The signal charges are transferred in the rightward direction to underside of electrodes of &phgr;H1B. Subsequently, signal charges of a channel denoted by B-B′ and channels equivalent thereto are transferred to undersides of electrodes of &phgr;H1B of the horizontal transfer register, and mixed with the signal charges previously transferred.

Abstract: A charge transfer structure (30) includes a substrate comprised of semiconductor material and, coupled to a surface of the substrate, a plurality of serially coupled devices each having a gate terminal. The plurality of serially coupled devices include a first single port device (D1) defining a first primary charge storage well, a second single port device (D3) defining a second primary charge storage well, a first two port device (D2) defining a first transfer device, a second two port device (D4) defining a second transfer device, and two instances of a third two port device each defining a cascode device (CD). The ports of these devices are serially coupled together in an order given by D1, D2, CD, D3, D4, CD for transferring charge between the first and second primary charge storage wells. Charge is inserted into and withdrawn from each of the first and second primary charge storage wells through a single diffusion that functions as both an input port and an output port.