Abstract: A semiconductor device includes N fins made of semiconductor regions aligned in parallel with each other in the top view plain, a gate electrode formed on both side surfaces of each of the N fins to cross the fins, source/drain layers formed in each of the N fins by sandwiching the gate electrode, a first wiring connected to one of the source/drain layers via a first contact formed in each of M fins, and a second wiring connected to the other one of the source/drain layers via a second contact formed in each of K fins.

Abstract: A semiconductor device includes: a lower layer interconnection formed on a chip; an upper layer interconnection formed in an upper layer above the lower layer interconnection above the chip; an interconnection via formed to electrically connect the lower layer interconnection and the upper layer interconnection; a via-type electric fuse formed to electrically connect the lower layer interconnection and the upper layer interconnection. The fuse is cut through heat generation, and a sectional area of the fuse is smaller than a sectional area of the upper layer interconnection and a via diameter of the fuse is smaller than that of the interconnection via.

Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

Abstract: Provided is a thin film transistor including a substrate, a source electrode and a drain electrode disposed above the substrate so as to oppose each other, an organic semiconductor film disposed between the source electrode and the drain electrode to generate a channel region, and a gate electrode disposed opposite the organic semiconductor film via a gate insulating film. The gate electrode includes an aperture in the channel region.

Abstract: A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.

Abstract: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern.

Abstract: An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the first interconnect; and an electric current inflow terminal and an electric current drain terminal for cutting the fuse link, formed on the semiconductor substrate and provided in one end and another end of the first interconnect, respectively.

Abstract: Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length.

Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode.

Abstract: Metal induced polycrystallized silicon is used as the anode in a light emitting device, such as an OLED or AMOLED. The polycrystallized silicon is sufficiently non-absorptive, transparent and made sufficiently conductive for this purpose. A thin film transistor can be formed onto the polycrystallized silicon anode, with the silicon anode acting as the drain of the thin film transistor, thereby simplifying production.

Abstract: A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and a dual gate structure are provided. The P-type polymetal gate electrode includes a P-type silicon layer containing P-type impurity, a silicide layer formed on the P-type silicon layer and having a plurality of silicide grains which are discontinuously disposed in a direction substantially parallel with the surface of the semiconductor substrate, a silicon film continuously formed on the surface of the P-type silicon layer exposed on the discontinuous part of the silicide layer and on the surface of the silicide layer, a second metal nitride layer formed on the silicon film, and a metal layer formed on the metal nitride layer.

Abstract: A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other e

Abstract: A solid-state imaging device is provided. The imaging device includes an imaging portion which includes light receiving portions and vertical transfer registers, a horizontal transfer portion, an output part for outputting an electrical signal converted from electric charges transferred from the horizontal transfer portion, a first reference potential applying means, and a second reference potential applying means. The imaging portion, the horizontal transfer portion and the output part are formed in a first conductivity type semiconductor substrate having a second conductivity type region, and a reference potential is applied to the second conductivity type semiconductor region. The first reference potential applying means applies a reference potential to the second conductivity type semiconductor region corresponding to an area where the output part is formed.

Abstract: A double gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used.

Abstract: A semiconductor device includes an active region extending along a first direction on a semiconductor substrate, the active region having a first sidewall and a second sidewall spaced apart and facing each other, a distance between the first and second sidewalls extending along a second direction, and a gate on the active region, the gate having a pair of body portions extending along the second direction and being spaced apart from each other, the second direction being perpendicular to the first direction, a head portion extending along the first direction to connect the body portions, the head portion overlapping a portion of the first sidewall, and a plurality of tab portions protruding from sidewalls of the body portions, the tab portions extending along the first direction and overlapping a portion of the second sidewall.

Abstract: An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region.

Abstract: A device includes: a first electrical contact; a second electrical contact; a semiconducting or semimetallic organic layer disposed at least partially between the first and second electrical contacts; and a tunneling barrier layer disposed at least partially between the semiconducting or semimetallic organic layer and the first electrical contact. The tunneling barrier layer has a thickness effective to enable flow of an electrical current through the tunneling barrier layer responsive to an operative electrical bias applied across the first and second electrical contacts, the electrical current exhibiting negative differential resistance for at least some applied electrical bias values. Circuits are also disclosed that utilize one or more negative differential resistance polymer diodes to implement logic, memory, or mixed signal applications.

Abstract: In relation to the conventional semiconductor device provided with a plurality of FETs, there is room for improving the pair accuracy of the FET-pair. A semiconductor device includes a first FET, a second FET, a third FET and a fourth FET. The four FETs are provided in an active region (certain region). The four have each of gate electrodes, respectively. Each of the gate electrodes are arranged along a circle in this sequence in plan view. The four FETs have the substantially same geometry.

Abstract: A field effect transistor includes a pair of ohmic electrodes and an n-type GaAs layer between the pair of ohmic electrodes and having recesses. Crank-shaped gate fingers are located within the recesses of the n-type GaAs layer between the pair of ohmic electrodes, and each crank-shaped gate finger includes perpendicular-extending portions and parallel-extending portions relative to the [0, 1, 1] crystal orientation of the n-type GaAs layer. The portion of the n-type GaAs layer between the gate fingers continuously extends from input ends of the gate electrodes to terminal ends of the gate electrode. A non-active region is located around each perpendicular-extending portion of the gate fingers.

Abstract: Conductive layers having knots are adjacently formed with uniform distance therebetween. Droplets of the conductive layers are discharged to stagger centers of the droplets in a length direction of wirings so that the centers of the discharged droplets are not on the same line in a line width direction between the adjacent conductive layers. Since the centers of the droplets are staggered, parts of the conductive layers each having a widest line width (the widest width of knot) are not connected to each other, and the conductive layers can be formed adjacently with a shorter distance therebetween.

Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.

Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21 channel 22 channel 23, 25. A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.

Abstract: A microelectronics apparatus comprising a substrate, a pair of grid electrodes coupled to the substrate on opposing sides of a central axis, wherein the grid electrodes are substantially parallel to each other and extend substantially perpendicular from the substrate, and a plurality of ion reflection lenses each coupled to the substrate, wherein each ion reflection lens: (1) is substantially perpendicular to each of the grid electrodes; (2) extends substantially perpendicular from the substrate; and (3) has an aperture aligned with the central axis.

Abstract: An object of the present invention is to realize a numerical aperture higher than that of a pixel having a conventional construction by using a pixel circuit having a novel construction in an electro-optical device. Therefore, it is utilized that the electric potential of a gate signal line in a row except for an i-th row is set to a constant electric potential in a period except for when a gate signal line (106) in the i-th row is selected. A gate signal line 111 in an (i?1)-th row is also used as an electric current supply line for an EL element (103) controlled by the gate signal line (106) in the i-th row. Thus, wiring number is reduced and high numerical aperture is realized.

Abstract: When an STI element isolation structure is formed, it is formed in such a manner that its upper portion protrudes further than the surface of a substrate than by a normal STI method, and a dummy electrode pattern is formed in a gate electrode forming portion. After a source/drain is formed in alignment with a gap portion, a conductive layer formed by filling the gap portion with W is formed, the dummy electrode pattern is removed, and a gate insulating film and a gate electrode are formed.

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate.

Abstract: The present invention discloses a semiconductor source/drain contact structure, which comprises a substrate, a source/drain region disposed in the substrate, at least one non-silicided conductive layer including a barrier layer disposed over and in contact with the source/drain region, and one or more contact hole filling metals disposed over and in contact with the at least one non-silicided conductive layer, wherein a first contact area between the at least one non-silicided conductive layer and the source/drain region is substantially larger than a second contact area between the one or more contact hole filling metals and the at least one non-silicided conductive layer.

Abstract: A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and a dual gate structure are provided. The P-type polymetal gate electrode includes a P-type silicon layer containing P-type impurity, a silicide layer formed on the P-type silicon layer and having a plurality of silicide grains which are discontinuously disposed in a direction substantially parallel with the surface of the semiconductor substrate, a silicon film continuously formed on the surface of the P-type silicon layer exposed on the discontinuous part of the silicide layer and on the surface of the silicide layer, a second metal nitride layer formed on the silicon film, and a metal layer formed on the metal nitride layer.

Abstract: A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are formed through the use of a single mask. An in-process semiconductor device which may be formed using one embodiment of the inventive method is also described.

Abstract: A memory cell includes a semiconductor feature and a phase change material. The semiconductor feature defines a groove that divides the semiconductor feature into a first electrode and a second electrode. The phase change material at least partially fills this groove and acts to electrically couple the first and second electrodes. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to at least one of the first and second electrodes. The semiconductor feature comprises silicon and the groove comprises at least one silicon sidewall with a substantially <111> crystal plane orientation.

Abstract: A phase-changeable memory device includes a substrate having a field effect transistor therein and a phase-changeable material electrically coupled to a source region of the field effect transistor. The phase-changeable material includes a chalcogenide composition containing at least germanium, bismuth and tellurium and at least one dopant selected from a group consisting of nitrogen and silicon.

Abstract: A solid-state imaging device can improve a detection sensitivity of a signal detecting means by decreasing a parasitic capacity of a horizontal signal line. In a solid-state imaging device in which a plurality of pixels are arranged in a matrix fashion, a pixel signal is flowed through a horizontal switch (39) to a horizontal signal line (40) as a signal charge, and a signal is outputted by a signal detecting means connected to the end off the horizontal signal line (40), an insulating gate-type field-effect transistor comprising the horizontal switch (39) includes channels extended at least in two directions between its source electrode connected to the horizontal signal line (40) and other drain electrode.

Abstract: Phase-changeable memory devices and method of fabricating phase-changeable memory devices are provided that include a phase-changeable material pattern of a phase-changeable material that may include nitrogen atoms and/or silicon atoms. First and second electrodes are electrically connected to the phase-changeable material pattern and provide an electrical signal thereto. The phase-changeable material pattern may have a polycrystal line structure.

Abstract: A plurality of low-sensitivity pixels 10 and a plurality of high-sensitivity pixels 20 are arranged like a tetragonal grid respectively, and are provided in positions shifted by ½ of an array pitch from each other in a row direction X and a column direction Y. The detected charges of the low-sensitivity pixel 10 and the high-sensitivity pixel 20 are transferred in the column direction Y by a vertical transfer section 31. The charges of the low-sensitivity pixel 10 and the high-sensitivity pixel 20 which are adjacent to each other in the column direction are transferred through the vertical transfer sections 31 which are different from each other.

Abstract: A charge coupled device (CCD) is disclosed which has a semiconductor body (20) comprising polymer or oligomer semiconductor material in place of the conventional silicon. A back electrode (22) of the device is electrically coupled to the semi-conductor body through a Schottky junction, reducing the availability of holes in the semiconductor body. Shift electrodes forming a shift register are driven by negative electrical potentials and accumulations of holes in p type semiconductor material represent data.

Abstract: A charge transfer device includes a charge transfer unit transferring signal charges, and an electric charge-voltage conversion unit detecting signal charges transferred from a last stage of the charge transfer unit via an output gate unit. An electrode in a last stage of the charge transfer unit is divided into first and second electrodes. A predetermined fixed potential is applied to the first electrode disposed on a side of the electric charge-voltage conversion unit. A transfer clock is applied to the second electrode disposed on a side opposite to the charge transfer unit.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.

Abstract: An SRAM cell. The SRAM cell including: a first gate segment common to a first PFET and a first NFET, a second gate segment common to a second PFET and a second NFET; a first silicide layer contacting a first end of the first gate segment and a drain of the second PFET; a second silicide layer contacting a sidewall contact region of the second gate segment and a drain of the first PFET; a third silicide layer contacting a sidewall contact region of the first gate segment and a drain of the second NFET; a fourth silicide layer contacting a first end of the second gate segment, a drain of the first PFET and a drain of a fourth NFET; and a fifth silicide layer contacting a second end of the first gate segment and a drain of a third NFET.

Abstract: Shift register electrodes are formed in an imaging area and a peripheral area through use of a single layer of conductive film, and a thick insulating film is deposited over those electrodes and planarized. The thick insulating film overlying the shift register electrodes in the peripheral area is kept as it is and on the other hand, the thick insulating film overlying the shift register electrodes is etched to just fill gaps between the shift register electrodes with the film, thereby allowing a light shielding metal layer overlying the shift register electrodes in the peripheral area and insulating films sandwiched therebetween to be formed without discontinuity. Since metal interconnect lines in the peripheral area have a thick and planarized insulating film formed thereunder, parasitic capacitance between diffusion layers/electrodes and the metal interconnect lines can be reduced, leading to reduction in power consumption of image sensor.

Abstract: An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the first interconnect; and an electric current inflow terminal and an electric current drain terminal for cutting the fuse link, formed on the semiconductor substrate and provided in one end and another end of the first interconnect, respectively.

Abstract: A copper conducting wire structure is for use in the thin-film-transistor liquid crystal display (LCD) device. The copper conducting wire structure includes at least a buffer layer and a copper layer. A fabricating method of the copper conducting wire structure includes the following steps. At first, a glass substrate is provided. Next, the buffer layer is formed on the glass substrate. The buffer layer is comprised of a copper nitride. At last, the copper layer is formed on the buffer layer.

Abstract: An optical sensor circuit for generating signals corresponding to received photoelectrons is formed on a single monolithic substrate and includes a charge coupled device (CCD) array. The array is formed of a plurality of pixels constructed by a standard CMOS process. Each pixel is formed of at least one charge well of minority carriers and a gate oxide layer overlaying the at least one charge well. At least two spaced gate electrodes corresponding in position to the at least two charge wells overlays the gate oxide layer. The space between adjacent electrodes defines a gap to transfer charge between adjacent ones of at the least two spaced gate electrodes and the gap is stabilized. A back-illuminated imager is also described in which photocarriers are diverted from devices integrated with the pixel by a PN junction formed in the pixel structure.

Abstract: In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

Abstract: A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilicon line; (d) removing a portion of the polysilicon line and a corresponding portion of the insulating sidewall layer in a contact region of the polysilicon line; and (e) forming a silicide layer on the sidewall of the polysilicon line in the contact region. Also an SRAM cell using the borderless contact structure and a method of fabricating the SRAM cell.

Abstract: The invention relates to a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.

Abstract: Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.

Abstract: In a photosensitive part 10, arranged from pixels A aligned in n rows and m columns, supply wiring lines 13a and 13b, which are electrically connected and apply transfer voltages to transfer electrodes 12a to 12d, formed of polycrystalline silicon, are installed so as to cover parts of the top surfaces of light-shielded pixels D. Dead zones for installing supply wiring lines, which existed priorly at the respective end parts in a horizontal direction of a photosensitive part, can thereby be eliminated and the photosensitive part can be made wide. Also, in the case where a plurality of the solid-state image pickup devices are used upon being made adjacent each other in the horizontal direction, parts at which image pickup is not carried out can be lessened. Also, the amount of lowering of the amounts of incident light on light-shielded pixels D can be corrected based on the output signals from light-shielded pixels D or other pixels A.

Abstract: A photogate-based photosensor for use in a CMOS imager exhibiting improved short wavelength light response. The photogate is formed of a thin conductive layer about 50 to 3000 Angstroms thick. The conductive layer may be a silicon layer, a layer of indium and/or tin oxide, or may be a stack having an indium and/or tin oxide layer over a silicon layer. The thin conductive layer of the photogate permits a greater amount of short wavelength light to pass through the photogate to reach the photosite in the substrate, and thereby increases the quantum efficiency of the photosensor for short wavelengths of light.

Abstract: Provided is a CCD image sensor wherein driving power and power consumption are reduced without increasing unusable regions. Photodiodes are arranged in a honeycomb form. Each vertical charge-transfer channel is made in such a manner that invasion portions, which invade spaces between the respective photoelectric transducers in photoelectric transducer columns positioned at both sides thereof, and non-invasion portions are alternately and continuously arranged, and the channel extends in the vertical direction to meander between the photodiodes arranged in the honeycomb form. Transfer electrodes extending in the horizontal direction to pass between the photodiodes are formed on the semiconductor substrate as monolayer electrodes. By making the transfer electrodes as the monolayer electrodes in this way, multi-layered poly-silicon electrode structure becomes unnecessary.