Abstract: A semiconductor structure includes a three-dimensional stacked transistor structure including first and second field-effect transistors of a first type at a first vertical level and third and fourth field-effect transistors of a second type at a second vertical level disposed over the first vertical level. The semiconductor structure also includes a first gate structure shared between the first and second field-effect transistors at the first vertical level, a second gate structure shared between the third and fourth field-effect transistors at the second vertical level, and a gate contact shared by the first and second gate structures. The wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: A semiconductor device includes a substrate and a fin structure. The fin structure includes a first semiconductor layer on the substrate, and a stack of one or more semiconductor layer structures. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer, the first and second semiconductor layers having a same semiconductor compound.

Abstract: According to one embodiment, a pressure sensor is disclosed. The pressure sensor includes a substrate, and a first capacitor element. The first capacitor element includes a lower electrode provided on the substrate, an upper electrode disposed above the lower electrode, and a film provided over the lower electrode and upper electrode. The lower electrode and the upper electrode are between the substrate and the film. An absolute value of an amount of change in an electrostatic capacitance between the lower electrode and the upper electrode with respect to unit change in an ambient temperature of the first capacitor element is substantially zero.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.

Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.

Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.

Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.

Abstract: Vertical field effect transistors (VFETs) having a gradient threshold voltage and an engineered channel are provided. The engineered channel includes a vertical dog-bone shaped channel structure that is composed of silicon having a germanium content that is 1 atomic percent or less and having a lower portion having a first channel width, a middle portion having a second channel width that is less than the first channel width, and an upper portion having the first channel width. Due to the quantum confinement effect, the middle portion of the vertical dog-bone shaped channel structure has a higher threshold voltage than the lower portion and the upper portion of the vertical dog-bone shaped channel structure. Hence, the at least one vertical dog-bone shaped channel structure has an asymmetric threshold voltage profile. Also, the VFET containing the vertical dog-bone shaped channel structure has improved electrical characteristics and device performance.

Abstract: Semiconductor devices and methods of forming the same include forming a doped dielectric layer on a semiconductor fin. The doped dielectric layer is annealed to drive dopants from the doped dielectric layer into the semiconductor fin. A gate stack is formed on the semiconductor fin.

Abstract: To suppress breakage of a diode. A semiconductor device comprises a stacked body and a first electrode. The stacked body includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, and a fourth nitride semiconductor layer that are stacked in sequence. The first electrode is in contact with a surface of the first nitride semiconductor layer that is opposite to a surface in contact with the second nitride semiconductor layer. The semiconductor device includes a transistor forming region and a diode forming region adjacent to the transistor forming region. The transistor forming region includes a first groove, a second electrode, and a third electrode. The first groove has a bottom portion located in the second nitride semiconductor layer. The second electrode is formed on a surface of the first groove.

Abstract: In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n?-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p?-type diffusion region in the depth direction, on the outer periphery of the p?-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, and forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins providing channels for the one or more vertical transport field-effect transistors. The method also includes forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack including a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer. The gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins.

Abstract: A semiconductor device includes: channel patterns disposed on a substrate; a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and a gate electrode disposed around the channel patterns, wherein the gate electrode includes a first recessed top surface between adjacent channel patterns, wherein the channel patterns are spaced apart from the substrate, and wherein the gate electrode is disposed between the substrate and the channel patterns.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.

Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.

Abstract: Vertical field effect transistor complementary metal oxide semiconductor (VFET CMOS) structures and methods of fabrication include a single mask level for forming the dual source/drains in both the NFET region and the PFET region. The VFET CMOS structures and methods of fabrication further include equal epi-to-channel distances in both the NFET region and PFET regions.

Abstract: A vertical transistor and a method of creating the same are provided. The vertical transistor has a substrate and a gate comprising a two-dimensional (2D) material on top of the substrate. There is a spacer on top of the gate. There is a gate dielectric comprising (i) a first portion on top of the spacer, (ii) a second portion extending down to a first side surface of the spacer and a side surface of the gate, and (iii) a third portion on top of the substrate. There is a channel comprising three portions. There is a first electrode on top of the first portion of the channel and a second electrode on top of the third portion of the channel.

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.

Abstract: Semiconductor devices and fabrication methods are provided. A fabrication method includes: forming a source and drain material layer over a substrate; forming a mask layer over the source and drain material layer and including a first trench exposing a portion of the source and drain material layer; forming a protective layer on sidewalls of the first trench; forming a second trench in the source and drain material layer using the mask layer and the protective layer as an etch mask; removing the protective layer after the second trench is formed; forming a channel material layer and a gate structure on the channel material layer after the protective layer is removed; and removing the mask layer after the channel material layer and the gate structure are formed. The channel material layer is on the sidewalls and the bottom of the first trench and the second trench.

Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

Abstract: A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.

Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.

Abstract: Various embodiments provide a reaction chamber including a support, a receptacle, and a sponge. The support includes a plurality of bars that are spaced from each other by a plurality of openings. Each of the bars has side surfaces that are slanted or tilted downward such that melted material may readily flow through the openings. The support is covered with a coating of silicon carbide to prevent materials from adhering to the support. The receptacle underlies the support and is configured to collect any melted material that is drained through the openings of the support. The sponge is positioned in the receptacle and under the support. The sponge is configured to absorb any melted material that is collected by the receptacle.

Abstract: Vertical field effect transistor complementary metal oxide semiconductor (VFET CMOS) structures and methods of fabrication include a single mask level for forming the dual source/drains in both the NFET region and the PFET region. The VFET CMOS structures and methods of fabrication further include equal epi-to-channel distances in both the NFET region and PFET regions.

Abstract: A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween.

Abstract: A semiconductor device includes an anode electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a conductive portion and a cathode electrode. The first semiconductor region is electrically connected to the anode electrode. The second semiconductor region is provided on the first semiconductor region. The conductive portion is provided in the first semiconductor region and the second semiconductor region with an insulating layer interposed between the conductive portion and the first and second semiconductor regions. The cathode electrode is electrically connected to the conductive portions and is electrically isolated from the second semiconductor region.

Abstract: A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.

Abstract: In general, according to one embodiment, a semiconductor memory device includes: first and second variable resistance elements provided above a semiconductor layer; a first insulation layer provided on top surfaces and side surfaces of the first and the second variable resistance elements; and a first interconnect extending in a first direction and provided on the first insulation layer, at least a portion of the first interconnect being opposed to the side surfaces of the first and second variable resistance elements via the first insulation layer.

Abstract: A method, according to one embodiment, includes: forming an annular cylindrical channel from a single block of electrically conductive material; forming an oxide layer over exposed surfaces of the annular cylindrical channel and exposed surfaces of the block of electrically conductive material; removing a portion of the oxide layer from an exterior base of the annular cylindrical channel, thereby forming a source contact recess which surrounds the base of the annular cylindrical channel; ion-implanting the exposed electrically conductive material substrate at a base of the source contact recess; and depositing a silicide material in the source contact recess, thereby forming a source contact tab.

Abstract: A semiconductor device of an embodiment includes a semiconductor layer having a first plane and a second plane; a first conductivity type first semiconductor region; a first conductivity type second semiconductor region between the first semiconductor region and the first plane; a second conductivity type third semiconductor region and a fourth semiconductor region between the second semiconductor region and the first plane; a first conductivity type fifth semiconductor region between the third semiconductor region and the first plane; a first conductivity type sixth semiconductor region type between the fourth semiconductor region and the first plane; a first conductivity type seventh semiconductor region between the third semiconductor region and the fourth semiconductor region, between the first semiconductor region and the first plane, and having impurity concentration higher than the first conductivity type impurity concentration of the second semiconductor region; first and a second gate electrode; firs

Abstract: An exemplary method of forming a fin field effect transistor that includes first and second etching processes to form a fin structure. The fin structure includes an upper portion and a lower portion separated at a transition. The upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.

Abstract: A method of forming a cylindrical vertical transistor; the method, according to one embodiment, includes: forming a cylindrical pillar from a single block of silicon, forming an oxide layer over an exterior of the cylindrical pillar and exposed surfaces of the block of silicon, coating the oxide layer with a spin-on-glass (SOG), depositing a source mask over a majority of the SOG coating, and removing a portion of the SOG coating and underlying oxide layer, where the portion removed is defined by the source mask. Other systems and methods are also described in additional embodiments herein which provide various different improved processes of forming the cylindrical gate contacts, the source contacts, and/or the drain contacts for vertical transistor structures which also include the aforementioned cylindrical pillar channel structures and cylindrical gate in comparison to conventional surface transistor structures.

Abstract: A vertical field-effect transistor (FET) device is fabricated with a self-aligned bottom insulating spacer for improved electrostatic control. A semiconductor fin is formed on a semiconductor substrate. A lower source/drain region, which is formed of a first type of epitaxial semiconductor material, is epitaxially grown on a surface of the substrate in contact with a bottom portion of the semiconductor fin. A sacrificial epitaxial semiconductor layer is epitaxially grown on top of the lower source/drain region, wherein the sacrificial epitaxial semiconductor layer is formed of a second type of epitaxial semiconductor material which is different from the first type of epitaxial semiconductor material. The sacrificial epitaxial semiconductor layer is selectively oxidized to form a self-aligned bottom insulating spacer comprising an oxide layer. A gate structure is formed contact with sidewalls of the semiconductor fin.

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.

Abstract: A transistor includes a vertical channel fin on a bottom source/drain region. The vertical channel fin includes a base portion and an upper portion. The base portion has a width greater than a width of the upper portion and a top surface height greater than a top surface height of the bottom source/drain region. A gate stack formed on sidewalls of the vertical channel fin. Spacers are formed above the gate stack, one above each sidewall of the vertical channel fin. A top source/drain region is formed between the spacers.

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract: A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.

Abstract: Transistor and methods of forming the same include forming a channel fin on a bottom source/drain region. A dielectric fill is formed around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin. Spacers are formed in the gap. The dielectric fill is etched away. A gate stack is formed on sidewalls of the channel fin directly underneath the spacers.

Abstract: An anti-fuse device includes a program transistor and a read transistor. The program transistor executes a program via insulation breakdown of a gate insulating layer. The read transistor is adjacent to the program transistor and reads the state of the program transistor. At least one of a first gate electrode of the program transistor or a second gate electrode of the read transistor is buried in a substrate.

Abstract: A method of fabricating a semiconductor capacitor is disclosed. The method includes forming a first trench in a semiconductor substrate, forming a dielectric lining layer in the first trench, and depositing a first capacitor conductor plate layer on the dielectric lining layer. The method also includes forming a second trench such that the dielectric lining layer is exposed. The method also includes forming a third trench such that the dielectric lining layer is exposed within the third trench. The method also includes depositing a second capacitor conductor plate layer in the second trench and depositing a third capacitor conductor plate layer in the third trench. The method also includes forming a first electrical contact between the first capacitor conductor plate layer and the second capacitor conductor plate layer and forming a second electrical contact between the first capacitor conductor plate layer and the third capacitor conductor plate layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded.