Abstract: Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.

Abstract: A ceramic electronic device includes a multilayer structure having a parallelepiped shape in which a first dielectric layer of which a main component is ceramic, a first internal electrode layer, a second dielectric layer of which a main component is ceramic, and a second internal electrode layer are stacked in this order, the first internal electrode layer being exposed to a first end face of the parallelepiped shape, the second internal electrode layer being exposed to a second end face of the parallelepiped shape, wherein in the multilayer structure, a conductive layer is provided on a side of the first end face, at a same level in a stacking direction as the second internal electrode, the conductive layer being spaced from the second internal electrode layer. A length of a gap between the second internal electrode layer and the conductive layer is 30 ?m or less.

Abstract: An integrated circuit semiconductor device includes a plurality of cylindrical structures separated from each other on a substrate; and a plurality of supporters having an opening region exposing side surfaces of the plurality of cylindrical structures, the plurality of supporters being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein each of the plurality of supporters has both side surfaces having slopes and has a top width that is less than a bottom width.

Abstract: A display device includes a display panel, and a touch sensing unit on the display panel, the touch sensing unit including a first conductive pattern on the display panel, an insulating layer covering the first conductive pattern, and a second conductive pattern on the insulating layer, partially crossing the first conductive pattern, and having a thickness that is greater than a thickness of the first conductive pattern.

Abstract: The present application discloses a semiconductor device with a decoupling unit and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area adjacent to the array area, a first decoupling unit positioned in the peripheral area of the substrate, a storage unit positioned in the array area of the substrate, a redistribution structure positioned above the peripheral area and the array area of the substrate, a middle insulating layer positioned on the redistribution structure positioned above the peripheral area, and a top conductive layer positioned on the middle insulating layer. The redistribution structure positioned above the peripheral area, the middle insulating layer, and the top conductive layer together configure a second decoupling unit.

Abstract: A charge amplifier that converts a charge signal to a voltage signal includes: a first conductive member through which the charge signal propagates; a second conductive member that is provided along at least a portion of the first conductive member; an insulating member provided between the first conductive member and the second conductive member; a potential controlling voltage signal output circuit that is connected to the second conductive member, and is configured to supply a potential controlling voltage signal to the second conductive member; and an integrating circuit that includes an input terminal and an output terminal, the input terminal being connected to the first conductive member, and is configured to output the voltage signal from the output terminal.

Abstract: A microelectronic device comprises a die comprising a front side and a back side opposite the front side, one or more components of integrated circuitry within a base material of the die and between the front side and the back side of the die, and one or more decoupling capacitors within the back side of the die. The one or more decoupling capacitors comprise a first electrode, a second electrode, and a dielectric material between the first electrode and the second electrode. The microelectronic device further comprises a first conductive via comprising a conductive material extending through the base material, the first conductive via in electrical communication with the first electrode of the one or more decoupling capacitors and the front side of the microelectronic device. Related apparatuses including a decoupling capacitor in a back side, and related electronic systems and methods are also described.

Abstract: A semiconductor includes a semiconductor substrate and pillar type capacitors. The semiconductor substrate includes first connecting pads and second connecting pads. The second connecting pads are disposed on the first connecting pads respectively, and the pillar type capacitors are disposed on the second connecting pads respectively. A first ends of the pillar type capacitors are connected to the second connecting pads respectively, and a second ends of the pillar type capacitors area at the opposite side of the first ends. The distance between the first end and the second end of each of the pillar type capacitors is from 1 micrometer to 1.8 micrometer. A manufacturing method is also provided.

Abstract: Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern including a single via. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first via surrounding a second via. The first and second vias are concentric with one another about a central point of the second via layer.

Abstract: Present disclosure provides a phase change memory structure, including a transistor region, a phase change material over the transistor region, a heater over the transistor region and in contact with the phase change material, and a dielectric layer surrounding the heater and the phase change material. The heater includes a first material having a first thermal conductivity, the first material disposed at a periphery of the heater, and a second material having a second thermal conductivity greater than the first thermal conductivity, the second material disposed at a center of the heater. Present disclosure also provides a method for manufacturing the phase change memory structure described herein.

Abstract: A semiconductor device includes a transistor implemented over an oxide layer, one or more electrical connections to the transistor, one or more dielectric layers formed over at least a portion of the electrical connections, an electrical element disposed over the one or more dielectric layers, the electrical element being in electrical communication with the transistor via the one or more electrical connections, a patterned form of sacrificial material covering at least a portion of the electrical element, and an interface layer covering at least a portion of the one or more dielectric layers and the sacrificial material.

Abstract: A dynamic random access memory (DRAM) and a method of fabricating the same are provided. The DRAM includes a substrate, a plurality of first isolation structures, a plurality of word line structures, a plurality of second isolation structures, and a plurality of third isolation structures. The plurality of first isolation structures are located in the substrate to define a plurality of active areas arranged along a first direction, wherein the plurality of active areas and the plurality of first isolation structures are alternately arranged along the first direction. The plurality of word line structures pass through the plurality of active areas and the plurality of first isolation structures. The plurality of word line structures are arranged along a second direction and extended along a third direction.

Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.

Abstract: In some embodiments, a method includes selecting, a first circuit layout, where the first circuit layout includes a circuit element representation, a design rule, and a target circuit element value. The method further includes receiving a plurality of circuit element values of circuit elements fabricated in each of multiple fabrication facilities using the design rule. The method also includes selecting a fabrication facility and a circuit element value of circuit elements fabricated in the selected fabrication facility using the design rule. Further the method includes determining a circuit element value calculation based on the selected circuit element values, and determining an adjustment value. This adjustment value is further used to customize the design rule. The method then includes generating a second circuit layout comprising the customized design rule, causing the fabrication facility to fabricate a circuit using the second circuit layout.

Abstract: A capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer disposed between the first and second electrodes and being in contact with each of the first and second electrodes. The dielectric layer contains at least one element selected from the group consisting of nitrogen and silicon.

Abstract: The present disclosure provides a semiconductor chip. The semiconductor chip includes a substrate, a main device, a one-time-programmable (OTP) device and a decoupling capacitor array. The substrate includes a first region and a second region. The main device is in the first region, the OTP device and the decoupling capacitor array are in the second region, and the decoupling capacitor array overlies the OTP device.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of one-time-programmable (OTP) cells, a bottom cell plate, a top cell plate and a decoupling capacitor array. The substrate includes a plurality of active areas and at least one isolation structure provided between the active areas to isolate the active areas from one another. The plurality of OTP cells are disposed in the active areas, the bottom cell plate is disposed on the OTP cells, and the top cell plate is disposed over the bottom cell plate. The decoupling capacitor array is disposed between the bottom cell plate and the top cell plate, and overlies the OTP cells.

Abstract: A semiconductor device may include an insulating layer, a pad, a circuit, at least one first wiring, at least one second wiring, at least one third wiring, and a pad contact. The pad may be disposed on the insulating layer. The circuit may be disposed in the insulating layer. The circuit may be positioned below the pad. The first wiring may be disposed between the pad and the circuit. The second wiring may be disposed between the pad and the first wiring. The third wiring may be disposed between the pad and the second wiring. The pad contact may be configured to directly connect the pad to the circuit.

Abstract: A semiconductor memory device includes a semiconductor substrate, a gate structure, a first spacer structure, and a gate connection structure. The semiconductor substrate includes a memory cell region and a peripheral region. The gate structure is disposed on the semiconductor substrate and disposed on the peripheral region. The gate structure includes a first conductive layer and a gate capping layer. The gate capping layer is disposed on the first conductive layer. The first spacer structure is disposed on a sidewall of the first conductive layer and a sidewall of the gate capping layer. The gate connection structure includes a first part and a second part. The first part penetrates the gate capping layer and is electrically connected with the first conductive layer. The second part is connected with the first part, and the second part is disposed on and contacts a top surface of the gate capping layer.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: Provided are a power receiving unit suppressing temperature rise of at least one of a coil and a capacitor, and a power supply system having the power receiving unit. The power receiving unit includes a coil and a capacitor body used for noncontactly receiving the power transmitted from the power supply device, and a receiving side case including therewithin a space housing the coil and the capacitor body. A pace K inside the receiving side case is wholly filled with heat conduction member.

Abstract: A display device includes a display panel, and a touch sensing unit on the display panel, the touch sensing unit including a first conductive pattern on the display panel, an insulating layer covering the first conductive pattern, and a second conductive pattern on the insulating layer, partially crossing the first conductive pattern, and having a thickness that is greater than a thickness of the first conductive pattern.

Abstract: A semiconductor device may include: a semiconductor substrate; an interlayer insulating film; a contact plug penetrating the interlayer insulating film; a first metal layer covering a surface of the interlayer insulating film; a protective insulating film covering a part of of the first metal layer; and a second metal layer covering the surface of the first metal layer. A peripheral region may be a region in which the protective insulating film is located; an active region may be a region in which a plurality of first parts of the contact plug is located; and an intermediate region may be a region which is located between the peripheral region and the active region and in which a second part of the contact plug is located. The first parts may extend toward an edge portion of the protective insulating film, and the second part may extend along the edge portion.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: The present disclosure provides a method for manufacturing a TFT substrate and a method for manufacturing a TFT display apparatus, including the steps of: providing a base substrate; forming a source/drain metal layer on the base substrate; depositing a photoresist layer on the source/drain metal layer and patterning the photoresist layer to form a desired pattern of the photoresist layer; using a BCl3 gas to remove metal oxides generated on surface of the source/drain metal layer with air; and using a mixing gas including a Cl2 gas and the BCl3 gas to etch the source/drain metal layer.

Abstract: A lower dielectric layer is disposed on a semiconductor substrate. A plurality of peripheral lower wirings are disposed on a peripheral region of the semiconductor substrate and in the lower dielectric layer. An upper dielectric layer is disposed on the lower dielectric layer and covers the plurality of peripheral lower wirings. A mold layer is disposed on the upper dielectric layer and includes an etching stopper layer. A peripheral upper wiring penetrates the mold layer and the upper dielectric layer to be connected to at least one of the plurality of peripheral lower wirings. The peripheral upper wiring includes a wiring portion, a first via portion extending downwardly from a bottom surface of the wiring portion, and a second via portion extending downwardly from the bottom surface of the wiring portion.

Abstract: A capacitor structure is disclosed. The capacitor structure includes a substrate, and a first electrode disposed on the substrate, the first electrode including a conductive layer, a first conductive post electrically connected to the conductive layer and a second conductive post electrically connected to the conductive layer. The capacitor structure further includes a planarization layer disposed on and covering the first electrode, the planarization layer disposed in a space between the first conductive post and the second conductive post, a first dielectric layer disposed on the planarization layer and in the space between the first conductive post and the second conductive post, and a second electrode disposed on the first dielectric layer.

Abstract: A semiconductor device may include an insulating layer, a pad, a circuit, at least one first wiring, at least-one second wiring, at least one third wiring, and a pad contact. The pad may be disposed on the insulating layer. The circuit may be disposed in the insulating layer. The circuit may be positioned below the pad. The first wiring may be disposed between the pad and the circuit. The second wiring may be disposed between the pad and the first wiring. The third wiring may be disposed between the pad and the second wiring. The pad contact may be configured to directly connect the pad to the circuit.

Abstract: Present disclosure provides a phase change memory structure, including a transistor region, a phase change material over the transistor region, a heater over the transistor region and in contact with the phase change material, and a dielectric layer surrounding the heater and the phase change material. The heater includes a first material having a first thermal conductivity, the first material disposed at a periphery of the heater, and a second material having a second thermal conductivity greater than the first thermal conductivity, the second material disposed at a center of the heater. Present disclosure also provides a method for manufacturing the phase change memory structure described herein.

Abstract: A semiconductor device structure including a scandium (Sc)- or yttrium (Y)-containing material layer situated between a substrate and one or more overlying layers. The Sc- or Y-containing material layer serves as an etch-stop during fabrication of one or more devices from overlying layers situated above the Sc- or Y-containing material layer. The Sc- or Y-containing material layer can be grown within an epitaxial group III-nitride device structure for applications such as electronics, optoelectronics, and acoustoelectronics, and can improve the etch-depth accuracy, reproducibility and uniformity.

Abstract: A capacitor that includes a conductive porous base material with a porous part; an upper electrode opposite the porous part, the upper electrode having, as its main constituent, a material selected from one of ruthenium, platinum, and an alloy of ruthenium and platinum; and a dielectric layer between the upper electrode and the conductive porous base material.

Abstract: A partial metal fill is provided within the footprint of an ultra-thick-metal (UTM) conductor on a dielectric layer to strengthen the dielectric layer to inhibit delamination of the UTM conductor without inducing significant electrical coupling between the UTM conductor and the partial metal fill.

Abstract: The present disclosure provides a memory cell. The memory cell includes a substrate, a deep trench capacitor formed in the substrate, and a vertical transistor formed on the substrate and electrically connected to the deep trench capacitor. The vertical transistor includes a source region and a drain region stacked on the substrate, a channel region vertically sandwiched between the source region and the drain region, and a gate structure annularly wrapping around the channel region.

Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.

Abstract: A memory device including a plurality of memory cells arranged in a crossbar configuration for a neural network is provided. Each of the memory cells includes a readout transistor, a charging transistor, a discharging transistor, and a stack capacitor array connected to one of source/drain regions of each of the charging transistor and the discharging transistor and a functional gate of the readout transistor for storing analog information.

Abstract: This disclosure provides systems, methods and apparatus for a via structure. In one aspect, an apparatus includes a substrate and a first electromechanical systems device on a surface of the substrate. The first electromechanical systems device includes a first metal layer and a second metal layer. A first via structure can be included on the surface of the substrate. The first via structure includes the first metal layer, the second metal layer, and a third metal layer. The first metal layer of the first electromechanical systems device may be the same metal layer as the first metal layer of the first via structure.

Abstract: A second data transfer line that is coupled to a gate layer of a drive transistor is formed in a layer higher than the gate layer, and a transfer capacitor is formed in a layer higher than a layer having the second data transfer line. A first data transfer line to which a data signal is supplied is formed in a layer higher than a layer having the transfer capacitor.

Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

Abstract: Device structures for a metal-insulator-metal (MIM) capacitor, as well as methods of fabricating a device structure for a MIM capacitor. An active device level is formed on a substrate, a local interconnect level is formed on the active device level, and a metal-insulator-metal capacitor is formed in a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate. The metal-insulator-metal capacitor includes a first plate on the sidewall, a second plate, and an interplate dielectric between the first plate and the second plate.

Abstract: A memory device including a plurality of memory cells arranged in a crossbar configuration for a neural network is provided. Each of the memory cells includes a readout transistor, a charging transistor, a discharging transistor, and a stack capacitor array connected to one of source/drain regions of each of the charging transistor and the discharging transistor and a functional gate of the readout transistor for storing analog information.

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract: An organic light emitting display (OLED) device includes a substrate, a plurality of first electrodes, a plurality of light emitting layers, a second electrode, a power supply line, a third electrode, and an encapsulation member. The third electrode that is formed on the power supply line and the second electrode that is formed on the light emitting layers extend to a contact region that is in a peripheral region of the substrate. The third electrode and the second electrodes have an uneven pattern in the contact region.

Abstract: A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the first direction; a plurality of second contacts alternately arranged between the first contacts and arranged at a predetermined distance in the first direction and the second direction; a plurality of dog bone-type conductive lines connected to the second contacts arranged in the second direction, respectively, among the plurality of second contacts, and having concave parts and convex parts; and a plurality of etching prevention patterns formed over the plurality of conductive lines so as to overlap the conductive lines, respectively.

Abstract: A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the insulating film; forming a dielectric film on the conductive film; forming a plurality of upper electrodes at intervals on the dielectric film; forming a first protective insulating film on the upper electrodes and the dielectric film by a sputtering method; forming a second protective insulating film on the first protective insulating film by an atomic layer deposition method, thereby filling gaps of a grain boundary of the dielectric film with the second protective insulating film; and patterning the conductive film after the second protective insulating film is formed to provide a lower electrode.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device.

Abstract: A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included.

Abstract: Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.