Parallel Interleaved Capacitor Electrode Pairs (e.g., Interdigitized) Patents (Class 257/307)
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Patent number: 7910949Abstract: A power semiconductor device includes a conductive board and a switching element mounted on the conductive board and electrically connected thereto. The power semiconductor device also includes an integrated circuit mounted on the conductive board at a distance from the switching element and electrically connected thereto. The switching element turns ON/OFF a connection between first and second main electrodes in response to a control signal inputted to a control electrode. The integrated circuit includes a control circuit which controls ON/OFF the switching element and a back side voltage detection element which detects a voltage of the back side of the integrated circuit.Type: GrantFiled: October 10, 2007Date of Patent: March 22, 2011Assignee: Mitsubishi Electric CorporationInventors: Yukio Yasuda, Atsunobu Kawamoto, Shinsuke Goudo
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Patent number: 7902583Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.Type: GrantFiled: July 21, 2008Date of Patent: March 8, 2011Assignee: Via Technologies, Inc.Inventor: Chih-Min Liu
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Patent number: 7884409Abstract: A semiconductor device and methods of fabricating the same, wherein insulation layers are interposed to sequentially dispose the semiconductor device on a semiconductor substrate. The semiconductor device includes a first conductive plate, a second conductive plate, a third conductive plate, and a fourth conductive plate. At least two of the first second, third and fourth conductive plates are electrically connected and constitute at least two capacitors.Type: GrantFiled: June 8, 2007Date of Patent: February 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Hae Kim, Myoung-Hwan Oh, Myung-Soo Yeo, Hea-Yean Park
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Patent number: 7876547Abstract: Vertical parallel plate (VPP) capacitor structures that utilize different spacings between conductive plates in different levels of the capacitor stack. The non-even spacings of the conductive plates in the capacitor stack decrease the susceptibility of the capacitor stack of the VPP capacitor to ESD-promoted failures. The non-even spacings may be material specific in that, for example, the spacings between adjacent conductive plates in different levels of the capacitor stack may be chosen based upon material failure mechanisms for plates containing different materials.Type: GrantFiled: May 30, 2007Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Ephrem G. Gebreselasie, Zhong-Xiang He, Steven H. Voldman
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Patent number: 7872293Abstract: A capacitance cell 21 is wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers T1 and T2 orthogonally to opposed lateral end faces out of lateral end faces X1, X2, Y1, and Y2 that section the cell in a plane direction. Contact surfaces of electrode surfaces T1 and T2 with the lateral end faces are second connection terminals T12 and T22. For longitudinal pathways, first and second via contact layers V1 and V2are connected. The first via contact layer V1 interconnects the wiring layers Ma and Mb. The second via contact layer V2 is connected to a wiring layer located outside beyond an upper or lower end face Z2, Z1. The second via contact layer V2 is connected to a first connection terminal T11, T21 located on the upper or lower end faces Z2, Z1. The capacitance cells 21 are linked via the first and second connection terminals so that a capacitance element having a free shape is formed.Type: GrantFiled: July 7, 2006Date of Patent: January 18, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Kazufumi Komura
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Patent number: 7863662Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.Type: GrantFiled: December 22, 2006Date of Patent: January 4, 2011Assignee: NGK Spark Plug Co., Ltd.Inventors: Motohiko Sato, Kazuhiro Hayashi, Kenji Murakami, Motonobu Kurahashi, Yusuke Kaieda, Jun Otsuka, Manabu Sato
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Patent number: 7863666Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.Type: GrantFiled: July 21, 2008Date of Patent: January 4, 2011Assignee: Via Technologies, Inc.Inventor: Chih-Min Liu
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Patent number: 7859080Abstract: The invention provides an electronic component which has an improved breakdown limit value of withstand voltage and improved insulation properties and which can be made compact and provided with a multiplicity of layers and a great capacity. The electronic component includes a first conductor having a bottom conductor formed on a substrate and a raised conductor formed to protrude from the bottom conductor, a dielectric film formed on the raised conductor, and a second conductor formed on the dielectric film to constitute a capacitor element in combination with the raised conductor and the dielectric film.Type: GrantFiled: December 1, 2006Date of Patent: December 28, 2010Assignee: TDK CorporationInventors: Hajime Kuwajima, Akira Furuya, Masahiro Miyazaki, Makoto Shibata
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Patent number: 7859825Abstract: A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.Type: GrantFiled: February 16, 2009Date of Patent: December 28, 2010Assignee: International Business Machines CorporationInventors: Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
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Patent number: 7847330Abstract: A multi-layer non-volatile memory integrally formed on top of a substrate including active circuitry is disclosed. Each layer of memory includes memory cells (e.g., a two-terminal memory cell) having a multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a write voltage across the memory cell. Data stored in the memory cells can be non-destructively determined by applying a read voltage across the memory cells. Data storage capacity can be tailored to a specific application by increasing or decreasing the number of memory layers that are integrally fabricated on top of the substrate (e.g., more than four layers or less than four layers). The memory cells can include a non-ohmic device for allowing access to the memory cell only during read and write operations. Each memory layer can comprise a cross point array.Type: GrantFiled: April 27, 2009Date of Patent: December 7, 2010Inventors: Darrell Rinerson, Christophe Chevallier, Steve Kuo-Ren Hsia
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Patent number: 7838919Abstract: The capacitor structure includes a first electrode having a plurality of teeth protruding in a comb shape from an electrode base of a first electrode line and a second electrode having a plurality of teeth protruding in a comb shape from an electrode base of a second electrode line, both formed in a first wiring layer. The first and second electrodes face each other with their teeth interdigitated with each other via a dielectric. At least one of the teeth of the first electrode is electrically connected with a third electrode line formed in a second wiring layer.Type: GrantFiled: March 27, 2008Date of Patent: November 23, 2010Assignee: Panasonic CorporationInventors: Kiyomi Okamoto, Tetsurou Sugioka, Kazuki Adachi
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Patent number: 7781773Abstract: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.Type: GrantFiled: March 5, 2008Date of Patent: August 24, 2010Assignee: Qimonda AGInventors: Andreas Thies, Klaus Muemmler
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Patent number: 7768055Abstract: Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.Type: GrantFiled: November 30, 2005Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Jeffrey B. Johnson, Jonghae Kim, Jean-Oliver Plouchart, Anthony K. Stamper
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Patent number: 7763925Abstract: A semiconductor device incorporating a capacitor and a method of fabricating the same include a first inter-layer dielectric film formed on a semiconductor substrate, a first electrode pattern formed on the first inter-layer dielectric film, and a capacitor region self-aligned to the first electrode pattern and in which the first inter-layer dielectric film is etched. An MIM capacitor is conformably formed on the sidewall of the first electrode pattern in the capacitor region. In the capacitor region, a first hollow region is formed enclosed by the MIM capacitor and a second electrode pattern fills the first hollow region. The second electrode pattern has a sidewall opposite to the sidewall of the first electrode pattern. The MIM capacitor is conformably formed in the capacitor region that is deepened more than a thickness of an interconnection layer, so that it has a capacitor area wider than an area contacting with the interconnection layer.Type: GrantFiled: May 29, 2007Date of Patent: July 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Jun-Pyo Hong
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Patent number: 7745868Abstract: A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.Type: GrantFiled: November 19, 2007Date of Patent: June 29, 2010Assignee: Elpida Memory, Inc.Inventor: Masahiko Ohuchi
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Patent number: 7741670Abstract: A semiconductor capacitor that includes a plurality of overlapping conductive layers and a field-effect transistor. The plurality of conductive layers include a first and second conductive layers that are spaced apart to creating a capacitance between the plurality of layers. In the semiconductor capacitor, the FET has a source, a drain and a gate. When the FET is in conduction mode, a capacitance is created between the gate and the conductive path in the semiconductor substrate between the source and the drain. The semiconductor capacitor's total capacitance is increased by coupling the drain and the source to the first conductive layer and coupling the gate to the second conductive layer.Type: GrantFiled: September 30, 2005Date of Patent: June 22, 2010Assignee: Broadcom CorporationInventor: Meng-An Pan
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Patent number: 7732889Abstract: A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.Type: GrantFiled: May 24, 2007Date of Patent: June 8, 2010Assignee: Akros Silicon Inc.Inventors: Philip John Crawley, Sajol Ghoshal
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Patent number: 7714371Abstract: A method and apparatus if provided for shielding a capacitor structure formed in a semiconductor device. In a capacitor formed in an integrated circuit, one or more shields are disposed around layers of conductive strips to shield the capacitor. The shields confine the electric fields between the limits of the shields.Type: GrantFiled: November 29, 2005Date of Patent: May 11, 2010Assignee: Black Sand Technologies, Inc.Inventors: Susanne A. Paul, Timothy J. Dupuis, Ali M. Niknejad
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Patent number: 7700984Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.Type: GrantFiled: May 1, 2006Date of Patent: April 20, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventor: Mikio Yukawa
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Publication number: 20100078700Abstract: To realize a semiconductor memory device whose capacitance value per unit area in a memory cell is increased without increase in the area of the memory cell. The memory cell includes a transistor, a memory element, a first capacitor, and a second capacitor. The first capacitor includes a semiconductor film, a gate insulating film, and a gate electrode which are included in the transistor and is formed at the same time as the transistor. The second capacitor includes an electrode which is included in the memory element and an insulating film and an electrode which are formed over the electrode. Further, the second capacitor is formed over the first capacitor. In this manner, the first capacitor and the second capacitor which are connected in parallel with the memory element are formed.Type: ApplicationFiled: September 14, 2009Publication date: April 1, 2010Inventor: Toshihiko Saito
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Patent number: 7675138Abstract: A first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and a second capacitor is formed on the substrate and connected to a second differential node of the differential circuit. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate.Type: GrantFiled: September 30, 2005Date of Patent: March 9, 2010Assignee: Broadcom CorporationInventor: Bo Zhang
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Patent number: 7667256Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structure levels in which in each case elongated interconnects are arranged.Type: GrantFiled: September 21, 2006Date of Patent: February 23, 2010Assignee: Infineon Technologies AGInventors: Martina Hommel, Heinrich Koerner, Markus Schwerd, Martin Seck
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Patent number: 7662695Abstract: Disclosed are a vertical-type capacitor and a formation method thereof. The capacitor includes a first electrode wall and a second electrode wall perpendicular to a semiconductor substrate, and at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall. The first electrode wall includes a plurality of first conductive layers and a plurality of first contacts, the plurality of first conductive layers being interconnected with each other by each of the plurality of first contacts. The second electrode wall includes a plurality of second conductive layers and a plurality of second contacts, the plurality of second conductive layers being interconnected with each other by each of the plurality of second contacts.Type: GrantFiled: May 8, 2008Date of Patent: February 16, 2010Assignee: Dongbu Electronics Co. Ltd.Inventor: Chee Hong Choi
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Patent number: 7663175Abstract: A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.Type: GrantFiled: May 30, 2006Date of Patent: February 16, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Kazufumi Komura, Takayoshi Nakamura, Keiichi Fujimura, Masahito Hirose, Keigo Nakashima, Masaki Nagato
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Patent number: 7659567Abstract: In a semiconductor device, a semiconductor substrate is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. A multi-layered insulating layer is formed on the substrate, and a conductive structure is formed in the insulating layer at the logic-circuit formation section. Capacitors are formed in the insulating layer at the memory formation section. Each of the capacitors includes a lower capacitor electrode, a capacitor dielectric layer formed on the lower capacitor electrode, and an upper capacitor electrode formed on the capacitor dielectric layer, with upper is end faces of the upper capacitor electrodes being coplanar with an upper end face of the conductive structure. Bit-line layers are formed in the insulating layer below the lower capacitor electrodes at the memory formation section.Type: GrantFiled: January 23, 2007Date of Patent: February 9, 2010Assignee: NEC Electronics CorporationInventor: Yasuyuki Aoki
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Patent number: 7659568Abstract: An external electrode structure for a monolithic ceramic capacitor provided with a function as a resistance element is capable of preventing a reduction of the external electrode due to baking in a reducing atmosphere, so that Ni or a Ni alloy can be used in an internal electrode and a good electrical connection between the internal electrode and the external electrode is achieved. The external electrodes disposed on an outer surface of a capacitor main body include an electrically conductive layer and a metal plating layer disposed thereon, and the electrically conductive layer includes a compound oxide, e.g., an In—Sn compound oxide, which reacts with Ni or the Ni alloy, and a glass component.Type: GrantFiled: February 2, 2007Date of Patent: February 9, 2010Assignee: Murata Manufacturing Co., Ltd.Inventors: Mitsuhiro Kusano, Shizuharu Watanabe
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Patent number: 7651908Abstract: A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor hole to expose a first portion of the lower electrode.Type: GrantFiled: February 15, 2007Date of Patent: January 26, 2010Assignee: Samsung Electronic Co., Ltd.Inventors: Gil-Sang Yoo, Byung-Jun Park
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Patent number: 7648878Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.Type: GrantFiled: December 20, 2005Date of Patent: January 19, 2010Assignee: Hynix Semiconductor Inc.Inventor: Tae-Woo Jung
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Patent number: 7645675Abstract: A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.Type: GrantFiled: January 13, 2006Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Hanyi Ding, Ebenezer E. Eshun, Michael D. Gordon, Zhong-Xiang He, Anthony K. Stamper
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Patent number: 7642587Abstract: A flat panel display device including a first region having an organic light emitting diode and a thin film transistor and a second region having a capacitor is disclosed. The capacitor comprises first, second, and third electrodes, where the area of a third capacitor electrode is reduced, thereby ensuring a distance between a first power voltage line and the third capacitor electrode. The total area of the capacitor is compensated by increasing the area of the first capacitor electrode. Thus, the area of the third capacitor electrode is reduced while the total capacitance of the capacitor is maintained, thereby preventing a dark spot caused by a short circuit between the first power voltage line and the third capacitor electrode.Type: GrantFiled: March 28, 2008Date of Patent: January 5, 2010Assignee: Samsung Mobile Display Co., Ltd.Inventor: Jong-Yun Kim
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Patent number: 7642591Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.Type: GrantFiled: April 20, 2006Date of Patent: January 5, 2010Assignee: Micron Technology, Inc.Inventors: R. Jacob Baker, Kurt D. Beigel
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Patent number: 7638830Abstract: An MIM capacitor structure having a metal structure formed thereover is provided. A dielectric layer is disposed over the metal structure and a top layer is disposed over the dielectric layer. A capacitance trench is formed through the top layer and into the dielectric layer. Respective bottom electrodes are formed over the opposing side walls of the capacitance trench. A capacitance dielectric layer is disposed over the respective bottom electrodes, the bottom of the capacitance trench and the remaining top layer. Respective opposing initial via openings are formed adjacent the capacitance trench. Respective trench openings are formed above, continuous and contiguous with the lower portions of the respective opposing initial via openings and exposing portions of the underlying metal structure to form respective opposing dual damascene openings. Planarized metal portions disposed within the dual damascene openings and the capacitance trench form a top electrode.Type: GrantFiled: August 16, 2006Date of Patent: December 29, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ping-Yi Hsin, Zan-Chun Wei
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Patent number: 7635887Abstract: An integrated circuit arrangement includes an undulating capacitor in a conductive structure layer. The surface area of the capacitor is enlarged in comparison with an even capacitor. The capacitor is interlinked with dielectric regions at its top side and/or its underside, so that it can be produced by methods which may not have to be altered in comparison with conventional CMP methods.Type: GrantFiled: August 11, 2006Date of Patent: December 22, 2009Assignee: Infineon Technologies AGInventor: Anton Steltenpohl
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Patent number: 7635888Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: GrantFiled: November 2, 2005Date of Patent: December 22, 2009Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill
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Patent number: 7633111Abstract: A semiconductor structure, for improving rectifier efficiency in passive backscatter transponders or backscatter remote sensors for use in high-frequency electromagnetic fields, is provided. The semiconductor structure has a dielectric layer on whose upper side is arranged a first electrically conductive layer, and a second electrically conductive layer that is spaced apart from the first electrically conductive layer and is arranged essentially below the first electrically conductive layer and is at least partially embedded in the dielectric layer. The dielectric layer has its lower side arranged on a semiconductor substrate of a first conductivity type within which is formed a more highly doped first zone of the first conductivity type which surrounds an even more highly doped second zone of the first conductivity type connected to a reference voltage. Whereby, the first zone can be arranged essentially completely under the first and second electrically conductive layers.Type: GrantFiled: August 5, 2005Date of Patent: December 15, 2009Assignee: Atmel Automotive GmbHInventor: Ulrich Friedrich
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Patent number: 7621041Abstract: The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprises: providing a dielectric composition comprising paraelectric filler and polymer wherein the paraelectric filler has a dielectric constant between 50 and 150; applying the dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating the multilayer film to a circuitized core wherein the dielectric layer of the multilayer film is facing the circuitized core; and removing the carrier film layer from the dielectric layer prior to processing; applying a metallic layer to the dielectric layer wherein the circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing the planar capacitor to form a multilayer structure.Type: GrantFiled: June 13, 2006Date of Patent: November 24, 2009Assignee: E. I. du Pont de Nemours and CompanyInventors: Sounak Banerji, G. Sidney Cox, Karl Hartmann Dietz
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Patent number: 7608881Abstract: A thin-film device comprises: a substrate; a flattening film made of an insulating material and disposed on the substrate; and a capacitor provided on the flattening film. The capacitor incorporates: a lower conductor layer disposed on the flattening film; a dielectric film disposed on the lower conductor layer; and an upper conductor layer disposed on the dielectric film. The thickness of the dielectric film falls within a range of 0.02 to 1 ?m inclusive and is smaller than the thickness of the lower conductor layer. The surface roughness in maximum height of the top surface of the flattening film is smaller than that of the top surface of the substrate and equal to or smaller than the thickness of the dielectric film. The surface roughness in maximum height of the top surface of the lower conductor layer is equal to or smaller than the thickness of the dielectric film.Type: GrantFiled: October 27, 2006Date of Patent: October 27, 2009Assignee: TDK CorporationInventors: Hajime Kuwajima, Masahiro Miyazaki, Akira Furuya
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Patent number: 7598592Abstract: A capacitor structure for an integrated circuit. An insulating layer is disposed on a substrate. A first conductive line is embedded in a first level of the insulating layer. A second conductive line is embedded in a second level of the insulating layer lower than the first level and has a projection onto the substrate completely covered by the first conductive line. A third conductive line is embedded in the second level of the insulating layer and separated from the second conductive line by a predetermined space, and has a projection onto the substrate partially covered by the first conductive line. The second conductive line is coupled to the first conductive line by at least one first conductive plug and has a polarity opposite to the third conductive line.Type: GrantFiled: February 16, 2007Date of Patent: October 6, 2009Assignee: Via Technologies, Inc.Inventors: Chun-Sheng Chen, Ying-Che Tseng
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Patent number: 7595525Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.Type: GrantFiled: September 5, 2006Date of Patent: September 29, 2009Assignee: Texas Instruments IncorporatedInventors: Bill Alan Wofford, Blake Ryan Pasker, Xinfen Chen, Binghua Hu
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Publication number: 20090236649Abstract: An embedded memory device solves the problem of the low reliability of the circuit due to the unstable power source. The embedded memory includes a metal-oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor to increase the stability of the power source ring to stabilize the voltage of the embedded memory and stabilize the voltage for the peripheral circuit of the embedded memory.Type: ApplicationFiled: June 19, 2008Publication date: September 24, 2009Applicant: ALI CORPORATIONInventors: Ming-Yen Huang, Wen-Hung Wu
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Patent number: 7579643Abstract: A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.Type: GrantFiled: February 16, 2007Date of Patent: August 25, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-jun Oh, Kyung-tae Lee, Yoon-hae Kim
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Patent number: 7564089Abstract: There is disclosed a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate, and including a bottom electrode, a dielectric film formed on the bottom electrode, and a top electrode formed on the dielectric film and having a plurality of hole patterns.Type: GrantFiled: August 5, 2004Date of Patent: July 21, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Soichi Yamazaki, Katsuaki Natori, Koji Yamakawa
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Patent number: 7557400Abstract: A semiconductor device has a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and a wiring capacitor which has a first comb-shaped wiring that is formed on said MOS capacitor through an interlayer insulating film, is connected to the gate electrode of said MOS capacitor, and has projecting portions projecting like comb teeth and a second comb-shaped wiring that is formed on said MOS capacitor through the interlayer insulating film, is arranged across an inter-line insulating film from the first comb-shaped wiring, is connected to the drain region and source region, and has projecting portions projecting like comb teeth, wherein the projecting portions of the second comb-shaped wiring are arranged alternately with the projecting portions of the first comb-shaped wiring and arranged perpendicularly to a channel direction connecting tType: GrantFiled: February 2, 2007Date of Patent: July 7, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Wada, Hiroaki Nakano, Hiroshi Ito, Toshimasa Namekawa, Atsushi Nakayama
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Patent number: 7547607Abstract: A method of fabricating an integrated circuit capacitor includes forming a first metal layer on a conductive plug in an interlayer insulating layer on a substrate. At least a portion of the first metal layer is silicided to form a metal silicide layer and a remaining first metal layer on the conductive plug. The remaining first metal layer is removed using a dry etching process. A lower electrode including a second metal layer is then formed on the metal silicide layer. Because the remaining first metal layer is removed, etching and/or other damage to the conductive plug and/or the interlayer insulating layer during a subsequent wet ethching process may be reduced and/or prevented.Type: GrantFiled: July 7, 2005Date of Patent: June 16, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-jin Moon, Gil-Heyun Choi, Sang-Woo Lee, Jae-Hwa Park
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Patent number: 7545022Abstract: A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.Type: GrantFiled: November 1, 2006Date of Patent: June 9, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Yi Chen, Chung-Long Chang, Chih-Ping Chao
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Patent number: 7528433Abstract: A capacitor structure with a cross-coupling design is provided. In the capacitor structure, conductive lines or electrode plates are coupled together by cross coupling an electrode above or below or aside the other electrode. By cross coupling and fewer vias, the largest capacitance value can be obtained within a minimum area. The capacitor structure provided can also be applied to a high-frequency high-speed module or system to enhance noise inhibition capability of a capacitive substrate.Type: GrantFiled: July 7, 2006Date of Patent: May 5, 2009Assignee: Industrial Technology Research InstituteInventors: Uei-Ming Jow, Chang-Sheng Chen, Ying-Jiunn Lai, Chin-Sun Shyu
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Patent number: 7525140Abstract: In an embodiment, a substrate includes a thin film capacitor embedded within. In an embodiment, a plurality of adhesion holes extend through the thin film capacitor. These adhesion holes may improve the adhesion of the capacitor to other portions of the substrate.Type: GrantFiled: December 14, 2005Date of Patent: April 28, 2009Assignee: Intel CorporationInventors: Yongki Min, John Guzek
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Patent number: 7518850Abstract: A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.Type: GrantFiled: May 18, 2006Date of Patent: April 14, 2009Assignee: International Business Machines CorporationInventors: Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
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Patent number: 7508020Abstract: A semiconductor device comprising a substrate and a ferroelectric capacitor formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film interposed between the lower and upper electrodes. The ferroelectric capacitor having sidewalls receded from sidewalls of the upper electrode.Type: GrantFiled: March 22, 2006Date of Patent: March 24, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Kanaya
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Patent number: 7498231Abstract: A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers. The first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers. The memory cell further includes a third electrode layer formed from a third conductive material, and a second layer of a metal-doped chalcogenide material disposed between the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.Type: GrantFiled: January 31, 2007Date of Patent: March 3, 2009Assignee: Micron Technology, Inc.Inventor: Terry L. Gilton