Abstract: Methods for forming a fin field effect transistor (FinFET) device structure are provided. The method includes providing a first fin structure and a second fin structure extending above a substrate and forming an isolation structure over the substrate, and the an upper portion of the first fin structure and an upper portion of the second fin structure protrudes from the isolation structure. The method also includes forming a first transistor and a second transistor on the first fin structure and the second fin structure, and the first transistor includes a first gate dielectric layer. The method further includes forming an inter-layer dielectric (ILD) structure between the first transistor and the second transistor, and a portion of the first gate dielectric layer above the isolation structure is in direct contact with a sidewall of the ILD structure.

Abstract: A high voltage semiconductor device including a P type substrate, a high voltage N type well, a first P type well, a drift region, and a P type doping layer is provided. The high voltage N type well and the P type doping layer, which is formed in a region located below the first P type well and the drift region, are formed in the P type substrate. The first P type well is formed in the high voltage N type well. A bottom of the first P type well and a bottom of the P type doping layer are separated from a surface of the P type substrate by a first depth and a second depth larger than the first depth, respectively. The drift region is formed in the high voltage N type well and extending down from the surface of the P type substrate.

Abstract: A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of interior MOSFET cells and an outer edge region of peripheral MOSFET cells, each interior MOSFET cell of the interior region of the array comprising a pair of interior MOSFET devices coupled to each other at a common drain contact. In an example embodiment, each interior MOSFET device includes a source contact (SCT) trench extended into a substrate contact region of the semiconductor substrate. The SCT trench is provided with a length less than a linear portion of a polysilicon gate of the interior MOSFET device, wherein the SCT trench is aligned to the polysilicon gate having a curvilinear layout geometry.

Abstract: Metal-oxide-semiconductor field-effect transistor (MOSFET) devices are described which have a p-type region between the p-type well regions of the device. The p-type region can be either floating or connected to the p-type well regions by additional p-type regions. MOSFET devices are also described which have one or more p-type regions connecting the p-type well regions of the device. The p-type well regions can be arranged in a various geometric arrangements including square, diamond and hexagonal. Methods of making the devices are also described.

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

Abstract: The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a semiconductor device of lateral double-diffused MOS (LDMOS) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of LDMOS type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.

Abstract: In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a bulk resistivity ??100 Ohm·cm, a front surface and a rear surface, an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate, and a RESURF structure comprising a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

Abstract: A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.

Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.

Abstract: A lateral superjunction MOSFET device includes multiple transistor cells connected to a lateral superjunction structure, each transistor cell including a conductive gate finger, a source region finger, a body contact region finger and a drain region finger arranged laterally within each transistor cell. Each of the drain region fingers, the source region fingers and the body contact region fingers is a doped region finger having a termination region at an end of the doped region finger. The lateral superjunction MOSFET device further includes a termination structure formed in the termination region of each doped region finger and including one or more termination columns having the same conductivity type as the doped region finger and positioned near the end of the doped region finger. The one or more termination columns extend through the lateral superjunction structure and are electrically unbiased.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

Abstract: The present invention can reduce an on-resistance while suppressing reduction in a short circuit capacity. The present invention includes a SiC epitaxial layer, a well region, a source region, a channel resistance adjusting region, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The channel resistance adjusting region is sandwiched between the source region and the SiC epitaxial layer in a surface layer of the well region. The channel resistance adjusting region is a region in which a first impurity region is intermittently formed in a direction intersecting a direction in which the source region and the SiC epitaxial layer sandwich the channel resistance adjusting region.

Abstract: A semiconductor device including a dummy pillar and a plurality of racetrack pillars. The dummy pillar of semiconductor material extends in a first lateral direction. The plurality of racetrack pillars, including the semiconducting material, surrounds the dummy pillar. Each of the plurality of racetrack pillars has a first linear section, which extends in the first lateral direction, and a first rounded section to form a racetrack shape. The plurality of racetrack pillars includes a first racetrack pillar and a second racetrack pillar. The first racetrack pillar is disposed proximate to the dummy pillar and the second racetrack pillar surrounds the first racetrack pillar. The first racetrack pillar is disposed between the dummy pillar and the second racetrack pillar. The semiconductor device includes a plurality of spacing regions including a first spacing region that surrounds the dummy pillar and is disposed between the first racetrack pillar and the dummy pillar.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A method includes forming a gate spacer along sidewalls of a gate structure, forming a source region and a drain region on opposite sides of the gate structure, wherein a sidewall of the source region is vertically aligned with a first sidewall of the gate spacer, depositing a dielectric layer over the substrate, depositing a conductive layer over the dielectric layer, patterning the dielectric layer and the conductive layer to form a field plate, wherein the dielectric layer comprises a horizontal portion extending from the second drain/source region to a second sidewall of the gate spacer and a vertical portion formed along the second sidewall of the gate spacer, forming a plurality of metal silicide layers by applying a salicide process to the conductive layer, the gate structure, the first drain/source region and the second drain/source region and forming contact plugs over the plurality of metal silicide layers.

Abstract: A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.

Abstract: A semiconductor device includes: a first semiconductor layer stacked body including a compound semiconductor; a first field-effect transistor element including a first drain electrode, a first source electrode, and a first gate electrode that are provided on the first semiconductor layer stacked body; a second semiconductor layer stacked body including a compound semiconductor; and a second field-effect transistor element including a second drain electrode, a second source electrode, and a second gate electrode that are provided on the second semiconductor layer stacked body. The second gate electrode forms a Schottky junction or a p-n junction with the second semiconductor layer stacked body, the second drain electrode is connected to the first drain electrode, the second source electrode is connected to the first gate electrode, and the second gate electrode is connected to the first source electrode.

Abstract: A semiconductor device is provided that includes a transistor in a semiconductor body having a main surface. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The body region and the drift zone are disposed along a first direction between the source region and the drain region. The first direction is parallel to the main surface. The semiconductor device further includes a field plate disposed in field plate trenches extending along the first direction in the drift zone, and a field dielectric layer between the field plate and the drift zone. A thickness of the field dielectric layer gradually increases along the first direction from a portion adjacent to the source region to a portion adjacent to the drain region.

Abstract: A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. A control gate structure includes a conductive layer that is spaced apart from the drain region by a first dimension in the lateral direction. A shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source and drain regions, wherein the second dimension is less than one-half of the first dimension.

Abstract: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: The present invention provides a DMOS device and a manufacturing method thereof. The DMOS device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, a drift buried region and a buried region. A first PN junction is formed between the high voltage well and an upper surface of the substrate. From a cross-section view, along the channel direction, a second PN junction is formed between the drift buried region and the buried region or formed between the high voltage well and the buried region. Along the channel direction, the first PN junction and the second PN junction have respective depths. The depth is defined as a distance extending from the upper face of the epitaxial layer downward along a vertical direction. The depth of the second PN junction is shallower than the depth of the first PN junction.

Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an LDMOS device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures. A depth of the first isolation structures is smaller than a depth of the second isolation structures. The multi-gate transistor device includes a plurality of first fin structures and a first gate electrode. The first fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The first gate electrode is intersectionally arranged with the first fin structures, and covers a portion of each first fin structure. The LDMOS device includes a second gate electrode covering on the substrate. The LDMOS device is electrically isolated from the multi-gate transistor device by another second isolation structure.

Abstract: A method for forming a semiconductor device includes forming a buried doped layer in a semiconductor substrate and forming a plurality of first trenches that expose the buried doped layer. A first dielectric layer is formed covering sidewalls of the first trenches, and a doped polysilicon layer is formed covering side surfaces of the first dielectric layer and bottom portions of the first trenches. The method also includes forming a second trench in each of the plurality of first trenches, and each second trench extending through a bottom portion of the doped polysilicon layer and the buried doped layer into a lower portion of the substrate. The method also includes forming a second dielectric layer inside each second trench. An isolation pocket structure is formed that includes the doped buried layer at the bottom and sidewalls that includes the doped polysilicon layer sandwiched between the first and second dielectric layers.

Abstract: A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a PN junction with the first-type substrate. The semiconductor device may further include a diode component configured to form a diode with the second-type well. The diode may be connected to the PN junction in a reverse series connection. The second-type may be N-type if the first-type is P-type, and wherein the second-type may be P-type if the first-type is N-type.

Abstract: A method includes defining, on a surface of a material, a plurality of discrete portions of a surface as surface elements having at least one of a laterally-varying size, a laterally-varying shape, and a laterally-varying spacing. A plurality of portions of the material beneath the surface elements are doped with a single quantity of dopant material per element area. The dopant material within the material beneath the surface elements expands to provide a lateral gradient of dopant material in the material beneath the surface elements.

Abstract: High voltage devices and methods for forming thereof are disclosed. A high voltage device includes a substrate having a device region, where the device region includes a source region and a drain region defined thereon. A transistor is disposed on the device region. The transistor includes a gate disposed over the substrate and in between the source and drain regions. First and second device wells are disposed in the substrate within the device region. The first device well is adjacent to a second side of the gate and the second device well is adjacent to a first side of the gate. Isolation regions are disposed within the substrate. The isolation regions include a device isolation region surrounding the device region and one or more isolation fingers disposed in a first portion of the device region adjacent to the first side of the gate.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a drift region formed in the high-voltage well, a drain region formed in the high-voltage well and spaced apart from the drift region, and a buried region having the first conductivity type formed in the high-voltage well between the drift region and the drain region.

Abstract: A semiconductor device is manufactured by forming a gate electrode adjacent to a body region in a semiconductor substrate, forming a field plate trench in a main surface of the substrate, the field plate trench having an extension length in a first direction parallel to the main surface, and forming a field electrode and a field dielectric layer in the field plate trench so that the field electrode is insulated from an adjacent drift zone by the field dielectric layer. The extension length of the field plate trench in the first direction is less than double an extension length of the field electrode in a second direction that is perpendicular to the first direction and is parallel to the main surface. The extension length in the first direction is more than half the extension length in the second direction.

Abstract: A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor.

Abstract: A dual-well metal oxide semiconductor (MOS) device includes: a semiconductor substrate, an active layer, a first conductive type well, a first conductive type body region, a second conductive type well, a gate, a second conductive type lightly doped diffusion (LDD) region, a second conductive type source, a second conductive type connection region, and a second conductive type drain. The second conductive type well is connected to the first conductive type well in a lateral direction, and a PN junction is formed therebetween right below the gate. The second conductive type connection region is formed right below a spacer of the gate, and is connected to the second conductive type source in a lateral direction to avoid OFF-channel. The second conductive type connection region is formed by a tilt-angle ion implantation process step through the spacer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

Abstract: A super junction semiconductor device includes a semiconductor portion having strip structures in a cell area. Each strip structure has a compensation structure with first and second sections inversely provided on opposite sides of a fill structure. Each section has first and second compensation layers of complementary conductivity types. The strip structures are linear stripes extending through the cell area in a first lateral direction and into an edge area surrounding the cell area in lateral directions. Each strip structure has an end section with a termination portion in the edge area in which the first compensation layer of the first section is connected with the first compensation layer of the second section via a first conductivity layer, and the second compensation layer of the first section is connected with the second compensation layer of the second section via a second conductivity layer.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

Abstract: The present disclosure relates to a high voltage transistor device having a field plate, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to a drift region arranged between the gate electrode and the drain region. A field plate is located within a first inter-level dielectric layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the drift region and vertically extends from the dielectric layer to a top surface of the first ILD layer. A plurality of metal contacts, having a same material as the field plate, vertically extend from a bottom surface of the first ILD layer to a top surface of the first ILD layer.

Abstract: There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.

Abstract: A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure.

Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a substrate and a first fin structure extending above the substrate. The FinFET also includes a first transistor formed on the first fin structure. The first transistor includes a first gate dielectric layer conformally formed on the first fin structure and a first gate electrode formed on the first gate dielectric layer. The FinFET further includes an inter-layer dielectric (ILD) structure formed adjacent to the first transistor. The first gate electrode is in direct contact with a sidewall of the ILD structure.

Abstract: A substrate with a silicon carbide film includes a silicon substrate, a SiC film, and a mask 4. The SiC film has a film 31 including openings 35 on the silicon substrate and a film 32 provided on the upper side of the film 31. The mask 4 has a mask 41 provided on the upper side of the silicon substrate and including openings 45 and a mask 42 covering at least part of the mask 41 located in the openings 35 and the side surfaces of the openings 35 and including openings 46. The width W1 of the opening 45, the thickness T1 (?m) of the mask 41, and the thickness D (?m) of the film 31 at a position corresponding to the opening 45 satisfy the following relationships: T1<tan(54.6°)×W1, and D?tan(54.6°)×W1.

Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

Abstract: A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Abstract: An isolation NLDMOS device including: an N well and a P well adjacent to each other on an upper part of a P substrate; on the upper part of the P well are sequentially arranged a first P type heavily doped region, a first field oxide, and a second P type heavily doped region; on the upper part of the N well are arranged a second field oxide and an N type heavily doped region; a gate oxide is between the second P type heavily doped region and the second field oxide; a gate polysilicon sits above the gate oxide and part of the second field oxide; from the first P type heavily doped region, the second P type heavily doped region and the N type heavily doped region are led out each a connecting wire via a respective contact hole.

Abstract: A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.

Abstract: An embodiment of a method of fabricating a diode having a plurality of regions of a first conductivity type and a buried region of a second conductivity type includes performing a first dopant implantation procedure to form the buried region, performing a second dopant implantation procedure to form an intermediate region of the plurality of regions, and performing a third dopant implantation procedure to form a contact region of the plurality of regions. The second and third dopant implantation procedures are configured such that the intermediate region is electrically connected with the contact region. The first, second, and third dopant implantation procedures are configured such that the buried region extends laterally across the contact region and the intermediate region to establish first and second junctions of the diode, respectively, and such that the first junction has a lower breakdown voltage than the second junction.

Abstract: A semiconductor device according to the invention includes an epitaxial layer of a first conductivity type, a first well of a second conductivity type to which a first potential is applied, a second well of the second conductivity type to which a second potential that differs from the first potential is applied, a third well of the first conductivity type provided in the epitaxial layer between the first well and the second well, a first impurity region of the first conductivity type provided in the epitaxial layer under the first well, a first MOS transistor provided in the first well, a second MOS transistor provided in the second well, and a third MOS transistor provided in the third well, the first impurity region having a higher impurity concentration than the epitaxial layer.

Abstract: An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed.