Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

Abstract: A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.

Abstract: A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

Abstract: Method and apparatus for providing a lateral double-diffused MOSFET (LDMOS) transistor having a dual gate. The dual gate includes a first gate and a second gate. The first gate includes a first oxide layer formed over a substrate, and the second gate includes a second oxide layer formed over the substrate. The first gate is located a pre-determined distance from the second gate. A digitally implemented voltage regulator is also provided that includes a switching circuit having a dual gate LDMOS transistor.

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80?, 80?), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44?, 84, 84?) and drift (50, 50?, 90, 90?) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50?, 90, 90?) at least into the underlying body region (44, 44? 84, 84?), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50?, 90, 90?).

Abstract: A bidirectional power transistor formed horizontally in a semiconductor layer disposed on a heavily-doped semiconductor wafer with an interposed insulating layer, the wafer being capable of being biased to a reference voltage, the product of the average dopant concentration and of the thickness of the semiconductor layer ranging between 5·1011 cm?2 and 5·1012 cm?2.

Abstract: Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer.

Abstract: The present invention is related to microelectronic device technologies. A method for making an asymmetric source-drain field-effect transistor is disclosed. A unique asymmetric source-drain field-effect transistor structure is formed by changing ion implantation tilt angles to control the locations of doped regions formed by two ion implantation processes. The asymmetric source-drain field-effect transistor has structurally asymmetric source/drain regions, one of which is formed of a P-N junction while the other one being formed of a mixed junction, the mixed junction being a mixture of a Schottky junction and a P-N junction.

Abstract: A method for manufacturing a semiconductor device, which includes the steps of: forming a mask layer (20) on a gate insulating film (18), the mask layer (20) having openings over the portions of first and second semiconductor layers that are destined to become low-concentration impurity regions and source and drain regions; forming first conductivity type implantation regions (24b, 24c) in the first and second semiconductor layers respectively by implanting a first conductivity type impurity (22) to the first and second semiconductor layers through the openings in the mask layer (20); forming first and second gate electrodes (26b, 26c) to cover a portion of the first conductivity type implantation regions and portions of the first and second semiconductor layers that are destined to become channel regions; forming another mask layer (28) which has openings over portions of the first conductivity type implantation region (24b) of the first semiconductor layer, said portions being located at both ends of the fi

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions.

Abstract: According to the embodiments, a semiconductor device using SiC and having a high breakdown voltage, a low on-resistance, and excellent reliability is provided.

Abstract: A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.

Abstract: A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity.

Abstract: An integrated device includes a semiconductor body, in which an STI insulation structure is formed, which delimits laterally first active areas and at least one second active area, respectively, in a low-voltage region and in a power region of the semiconductor body. The integrated device moreover includes low-voltage CMOS components, accommodated in the first active areas, and a power component in the second active area. The power component has a source region, a body region, a drain-contact region, and at least one field-insulating region, set between the body region and the drain-contact region. The field-insulating region is provided entirely on the semiconductor body.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate having a device region; a gate, which is located on a surface of the substrate; a second conductive type source and a second conductive type drain in the device region at different sides of the gate respectively; and a second conductive type drift region, which is located in the device region, between the source and the drain. The gate includes: a conductive layer for receiving a gate voltage; and multiple dielectric layers with different thicknesses, located at different horizontal positions. From cross-section view, each dielectric layer is between the conductive layer and the substrate, and the multiple dielectric layers are arranged in an order from thinner to thicker from a side closer to the source to a side closer to the drain.

Abstract: A P type semiconductor substrate includes a P type body region, an N type drift region formed away from the P type body region in a direction parallel to a substrate surface, an N type drain region formed in a region separated by a field oxide film in the N type drift region so as to have a concentration higher than the N type drift region, an N type source region formed in the P type body region so as to have a concentration higher than the N type drift region. A P type buried diffusion region having a concentration higher than the N type drift region is formed of a plurality of parts each of which is connected to a part of the bottom surface of the P type body region and extends parallel to the substrate surface and its tip end reaches the inside of the drift region.

Abstract: A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.

Abstract: A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.

Abstract: A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

Abstract: The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) formed therewithin; a first ohmic electrode disposed on a central region of the semiconductor layer; a second ohmic electrode which is formed on the edge regions of the semiconductor layer in such a manner to be disposed to be spaced apart from the first ohmic electrodes, and have a ring shape surrounding the first ohmic electrode; and a Schottky electrode part which is formed on the central region to cover the first ohmic electrode and is formed to be spaced apart from the second ohmic electrode.

Abstract: A semiconductor device includes a source region within a semiconductor substrate, a drain region within the semiconductor substrate, a control gate over the semiconductor substrate and between the source region and the drain region, a first gate between the control gate and the drain region, and a first doped region within the semiconductor region and between the control gate and the first gate. The method of forming the semiconductor device may include depositing an electrode material over the semiconductor substrate, patterning the electrode material to form a control gate and a first gate, implanting a first doped region within the semiconductor substrate between the control gate and the first gate while using the control gate and the first gate as a mask, and implanting a source region within the semiconductor substrate.

Abstract: In an ultra high voltage lateral DMOS-type device (UHV LDMOS device), a central pad that defines the drain region is surrounded by a racetrack-shaped source region with striations of alternating n-type and p-type material radiating outwardly from the pad to the source to provide for an adjustable snapback voltage.

Abstract: A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length.

Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.

Abstract: A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.

Abstract: A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110, and a device isolation insulating film 132 and device isolation insulating film 134. Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134; and in the n-doped source region 114, the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.

Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.

Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating layer connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.

Abstract: In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.

Abstract: An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions.

Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

Abstract: A method for manufacturing a lateral double diffused metal oxide semiconductor (LDMOS) device includes forming an oxide layer on a semiconductor substrate, forming first and second trenches by partially etching the oxide layer and the semiconductor substrate, forming a small trench overlapping with the second trench so that the second trench has a stepped structure, and depositing one or more dielectric layers so that the first trench forms a device isolation layer defining a semiconductor device region and the second trench having a stepped structure forms a drain extension device isolation layer. The breakdown voltage of the LDMOS device may be improved while reducing the on-resistance, thereby improving the operational reliability of the device.

Abstract: A transistor arrangement including a triple well structure, the triple well structure including a substrate of a first conductivity type, a first well region of a second conductivity type formed within the substrate and a second well region of the first conductivity type being separated from the substrate by the first well region. The transistor arrangement further includes a first transistor formed on or in the second well region, the first transistor including a body terminal being connected to the second well region and a second well region switch being connected to the body terminal of the first transistor.

Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.

Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).

Abstract: A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

Abstract: A cellular transistor includes an N-type heavily doped (N+) buried layer (NBL), an N-well connected to the NBL, an N+ layer connected to the N-well and multiple drains. The N-well is formed after formation of the NBL. The N+ layer is formed after formation of the N-well. The multiple drains are connected to the NBL via the N-well and the N+ layer.

Abstract: A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.

Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.

Abstract: A power transistor includes a semiconductor layer an electrode layer. The semiconductor layer having a source zone, a drain zone spaced apart from the source zone in a lateral direction, a drift zone adjacent to the drain zone, and a body zone. The body zone is interposed between the drift zone and the source zone. The electrode layer is dielectrically insulated from the semiconductor layer, and includes a gate electrode divided into at least two sections and a field plate. The field plate is arranged at a first height level relative to the semiconductor layer. A first gate electrode section is arranged at least partially at a second height level, which is lower than the first height level relative to the semiconductor layer. A second gate electrode section, which is laterally displaced from the first gate electrode section, is disposed at a first intermediate level arranged between the first and second height levels.

Abstract: A semiconductor device includes a source region embedded in the surface of the second semiconductor region, a drain region embedded in the surface of the first semiconductor region separated from the second semiconductor region, a gate electrode located on the second semiconductor region, an insulation film located on the first semiconductor region between the second semiconductor region and the drain region, a voltage dividing element dividing the voltage between the gate electrode and the drain region, and a charge transfer limiting element limiting transfer of charge from the voltage dividing element to the drain region.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.

Abstract: A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure.

Abstract: A field drain insulating part has a first insulating film and a high dielectric constant insulating film. The first insulating film is positioned at least in the center of the field drain insulating part in a plan view. The high dielectric constant insulating film is positioned at a part close to a drain region in the edge of the bottom surface of the field drain insulating part, and has a higher dielectric constant than the first insulating film. The high dielectric constant insulating film is not positioned in the center of the field drain insulating part in a plan view.

Abstract: A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween.

Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion.