Abstract: A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source and drain and a channel below the gate, having an asymmetric shape with respect to a center line along which the gate extends.

Abstract: Reducing the manufacturing cost of an EL display device and an electronic device furnished with the EL display device is taken as an objective. A textured structure in which projecting portions are formed on the surface of a cathode is used. External stray light is diffusely (irregularly) reflected by the action of the projecting portions when reflected by the surface of the cathode, and therefore a defect in which the face of an observer or the surrounding scenery is reflected in the surface of the cathode can be prevented. This can be completed without using a conventionally necessary high price circular polarizing film, and therefore it is possible to reduce the cost of manufacturing the EL display device.

Abstract: A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.

Abstract: A semiconductor device according to the present invention includes a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each of the nonvolatile memory devices includes a word gate formed over a semiconductor layer with a gate insulating layer interposed in between, impurity layers formed in the semiconductor layer, and sidewall-shaped control gates formed along both side surfaces of the word gate. The control gate includes a first control gate and a second control gate which are adjacent to each other. The first control gate is formed on a first insulating layer formed of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The second control gate is formed on a second insulating layer formed of a silicon oxide film.

Abstract: The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.

Abstract: MOS transistor comprising: a channel region (120) made of a semiconducting material above which there is a grid structure, the grid structure comprising a grid (110) and insulating spacers (122) coating the sides of the grid, regions called source and drain extension regions (116a, 118a) located on each side of the channel, in direct contact with the semiconducting material of the channel, and arranged essentially under the grid structure, the extension regions being made of a non-insulating material, source and drain regions (146, 148) made of metal, in contact with source and drain extension regions respectively and extending partly under the grid structure. Application to manufacturing of integrated circuits.

Abstract: A semiconductor device comprises at least a semiconductor layer including source and drain areas of a first conductive type and of a high impurity concentration and a channel area positioned between the source and drain areas, an insulation layer covering at least the channel area, and a gate electrode positioned close to the insulation layer. The channel area at least comprises a first channel area of a low resistance, positioned close to the insulation layer and having a second conductive type opposite to the first conductive type, and a second channel area of a high resistance, having the first conductive type and positioned adjacent to the first channel area.

Abstract: An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.

Abstract: A semiconductor device in accordance with the present invention includes: an insulating layer; a semiconductor region formed on the insulating layer; a trench that surrounds side parts of the semiconductor region and reaches the insulating layer; an isolation insulating film formed in the trench; a semiconductor element in which the semiconductor region serves as an active region; a side oxide film formed by oxidizing the side parts of the semiconductor region and located between the rest of the semiconductor region and the isolation insulating film; and a bottom oxide film that is formed by oxidizing a bottom part of the semiconductor region, located over the entire interface between the rest of the semiconductor region and the insulating layer, and having side surfaces that reach the side oxide film.

Abstract: A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.

Abstract: Memory elements, switching elements, and peripheral circuits to constitute a nonvolatile memory are integrally formed on a substrate by using TFTs. Since semiconductor active layers of memory element TFTs are thinner than those of other TFTs, impact ionization easily occurs in channel regions of the memory element TFTs. This enables low-voltage write/erase operations to be performed on the memory elements, and hence the memory elements are less prone to deteriorate. Therefore, a nonvolatile memory capable of miniaturization can be provided.

Abstract: By suppressing a short-channel effect of a MIS field-effect transistor and reducing a fringing capacitance of a gate, a signal delay in the transistor can be shortened. The MIS field-effect transistor is formed d by forming a side-wall spacer from a dielectric having a large dielectric constant and then forming an impurity diffusion layer area with the side-wall spacer used as an introduction end in an ion implantation process to introduce impurities. In this case, the side wall of the side-wall spacer having the large dielectric constant has an optimum film thickness in the range from 5 nm to 15 nm, which is required for achieving a large driving current. On the other hand, a side-wall spacer on an outer side is made of a silicon-dioxide film, which is a dielectric having a small dielectric constant.

Abstract: In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A Dicing line is interposed between four basic chips F configuring the memory chip. Four basic chips F can change a word organization by a control signal individually.

Abstract: The present invention discloses an improved transistor with a &pgr;-gate structure usable at microwave and millimeter wave and comprises a GaAs wafer, GND formed on the bottom surface of the wafer and grounded to source layers formed on the top surface of the wafer by the process of back-side via-hole. A drain is formed on the top surface of the wafer between the source layers and has an air layer on top. A gate, shaped as a result of using an air bridge technique, contacts the top surface of the wafer between the source layers and the drain so as to support the wafer at laterally opposite ends over the air layer of the drain. The gate having &pgr;-structure improves noise characteristics of the transistor because of low electrical resistance, which is a result of the gate structure straddling above the drain stage.

Abstract: A method for forming a self-aligned contact in a semiconductor device which can reduce process failures and a method for manufacturing a semiconductor device that includes the self-aligned contact are provided. A self-aligned contact hole is formed in an interlayer dielectric film to expose a portion of the substrate between conductive structures formed thereon. A buffer layer is formed on a sidewall of the self-aligned contact hole, on the bottom of the self-aligned contact hole, and on the interlayer dielectric film such that the thickness of the buffer layer at an upper portion of the self-aligned contact hole is greater than the thickness of the buffer layer at the bottom of the self-aligned contact hole. After removing the portion of the buffer layer on the bottom of the self-aligned contact hole, a contact is formed in the self-aligned contact hole to make contact with the substrate.

Abstract: A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.

Abstract: A semiconductor thin film having extremely superior crystallinity and a semiconductor device using the semiconductor thin film having high performance are provided. The semiconductor thin film is manufactured in such a manner that after an amorphous semiconductor thin film is crystallized by using a catalytic element, a heat treatment is carried out in an atmosphere containing a halogen element to remove the catalytic element. The thus obtained crystalline semiconductor thin film has substantially {110} orientation. The concentration of C, N, and S remaining in the final semiconductor thin film is less than 5×1018 atoms/cm3, and the concentration of O is less than 1.5×1019 atoms/cm3.

Abstract: A semiconductor device includes a gate electrode 16 on a P type well through a gate oxide film 9, a heavily-doped N+ type source layer 12 formed to be adjacent to the one end of the gate electrode 16, an N+ type drain layer 12 formed apart from the other end of the gate electrode 16, a P type body layer 14 below the gate electrode 16, and a lightly-doped drain layer 10 formed in an area extending from below the gate electrode 16 to the heavily-doped N+ type drain layer 12 so that it is shallow at least below the gate electrode 16 and deep in the vicinity of the heavily-doped N-type drain layer 12.

Abstract: A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (111) is deposited outwardly from the trench isolation structure (112). A first insulator layer (116) and a second insulator layer (118) are grown proximate to the epitaxial layer (111). A gate stack (123) that includes portions of the first insulator layer (116 and the second insulator layer (118) is formed outwardly from the epitaxial layer (111). The gate stack (123) also includes a gate (122) with a narrow region (130) and a wide region (132) formed proximate the second insulator layer (118. The epitaxial layer (111) is heated to a temperature sufficient to allow for the epitaxial layer (111) to form a source/drain implant region (126) in the active region (110).

Abstract: An insulated gate field effect transistor comprises a non-single-crystalline semiconductor layer formed on a substrate, a gate electrode, is formed on a portion of the surface of said semiconductor layer, and a gate insulated film is disposed between said gate electrode and said semiconductor layer. A non-single-crystalline channel region is defined within said semiconductor layer just below said gate, electrode. A source region and a drain region are transformed from and defined within said semiconductor layer immediately adjacent to said channel region in an opposed relation, said source and drain regions being crystallized to a higher degree than that of said channel region by selectively irradiating portions of said semiconductor layer using said gate electrode as a mask.

Abstract: A semiconductor device having a self-aligned contact structure. To determine the position of a contact plug in a self-aligned manner, silicon nitride films are provided around a gate electrode and a bitline, respectively. Between the gate electrode and bitline, and the silicon nitride films are provided low dielectric constant insulation films having a dielectric constant lower than that of the silicon nitride films. Further, the low dielectric constant insulation films are provided in contact with the gate electrode and bitline. The presence of the low dielectric constant insulation films suppresses the increase in parasitic capacitance resulting from the presence of the silicon nitride films between the gate electrode and bitline, and the contact plug.

Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

Abstract: A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.

Abstract: A semiconductor device comprising a gate having an approximately 0.05 &mgr;m channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the oxide layer; and gate and drain regions on opposite sides of the halo implant and below the oxide layer.

Abstract: A semiconductor component includes a first connection zone of a first conductivity type for providing a contact at a first side of a semiconductor body and a second connection zone of the first conductivity type for providing a contact at the second side of the semiconductor body. A drift zone adjoins the first connection zone and extends in a vertical direction of the semiconductor body as far as the second side of the semiconductor body. A body zone of a second conductivity type is disposed between the second connection zone and the first connection zone or the drift zone. A control electrode is insulated from the semiconductor body and disposed above the body zone such that the control electrode substantially does not overlap with the drift zone and the second connection zone in a lateral direction. A method for manufacturing a semiconductor component is also provided.

Abstract: At one of main surfaces of a silicon substrate serving as an N+type drain region is arranged an N type first high resistance drift layer. On the first high resistance drift layer is arranged an N−type second high resistance drift layer. A P− type high resistance buried layer is arranged on the surface layer of the first high resistance drift layer and the bottom layer of the second high resistance drift layer at a position right under each of a plurality of P type base regions arranged on the surface layer of the second high resistance drift layer. The thickness T1 of the first high resistance drift layer is set in such a manner that a depletion layer extending over the first high resistance drift layer reaches through the drain region at a voltage lower than a sharing voltage V1 shared by the first high resistance drift layer.

Abstract: A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Abstract: A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of silicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

Abstract: A silicon carbide lateral metal-oxide-semiconductor field-effect transistor (SiC LMOSFET) having a self-aligned drift region and method for forming the same is provided. Specifically, the SiC LMOSFET includes a source region, a drift region and a drain region. The source and drain regions are implanted using non self-aligned technology (i.e., prior to formation of the gate electrode and the gate oxide layer), while the drift region is implanted using self-aligned technology (i.e., after formation of the gate electrode and the gate oxide layer). By self-aligning the drift region to the gate electrode, the overlap between the two is minimized, which reduces the capacitance of the device. When capacitance is reduced, performance is improved.

Abstract: A semiconductor device comprises a gate insulating film formed on a semiconductor substrate, a layer insulting film formed over the gate insulating film and provided with an opening, and a gate electrode formed on the gate insulating film in the opening of the interlayer insulating film. The gate electrode has a metal film, and a poly-Si film formed on the side surfaces of the metal film. The poly-Si film coating the side surfaces of the metal film reduces stresses that may be induced in the interlayer insulating film and the metal film.

Abstract: A semiconductor layer 30 of a graded SiGe-HDTMOS is constructed of an upper Si film 12, an Si buffer layer 13, an Si1−xGex film 14 and an Si cap layer 15. The region between a source region 20a and drain region 20b of the semiconductor layer 30 includes a high concentration n-type Si body region 22 and an n Si region 23, an Si cap region 25 and an SiGe channel region 24. A Ge composition ratio x of the Si1−xGex film 14 is made to increase from the Si buffer layer 13 to the Si cap layer 15. For the p-type HDTMOS, the electron current component of the substrate current decreases.

Abstract: A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

Abstract: A cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells chains. Each cells chain at least includes: numerous gates that located on a substrate, numerous doped regions, numerous polysilicon layers, numerous cover dielectric layers, a conductor layer and numerous isolation dielectric layers.

Abstract: Ion implantation is conducted using contact holes of a MOS transistor as.a mask to form high concentration diffusion regions, whereby a MOS transistor having a medium withstand voltage structure is provided, in which a high drain withstand voltage, a small capacitance between a source/drain region and a gate electrode, and a high junction withstand voltage between a source/drain region and a channel stop region under a field oxide film are obtained, and the drain withstand voltage can be controlled. Low impurity concentration source and drain regions of a second conductivity type are formed in a semiconductor substrate surrounded by a field oxide film and a gate electrode. An interlayer insulating film is formed thereover for electrically insulating a gate electrode and the source and drain regions. A wiring layer is formed on the interlayer insulating film.

Abstract: An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse.

Abstract: A semiconductor device and a fabrication method thereof which can, for example, prevent a punch-through from occurring by forming oxide spacers around source/drain regions in a semiconductor substrate instead of forming a conventional halo ion implanting layer. Such structure improves, for example, an operational speed by reducing junction capacitance, prevents a hot carrier effect from occurring by weakening an electric field around the drain region, and improves reliability by preventing a latch up from occurring. The semiconductor device includes a gate electrode formed on the semiconductor substrate, sidewall spacers formed at the sidewalls of the gate electrode, an impurity layer formed in the semiconductor substrate below each sidewall spacer, a trench formed in the semiconductor substrate at both sides of the gate electrode, oxide spacers formed at the bottom inside corner of each trench, and a conductive material filling up each trench.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: A laser doping process comprising: irradiating a laser beam operated in a pulsed mode to a single crystal semiconductor substrate of a first conductive type in an atmosphere of an impurity gas which imparts the semiconductor substrate a conductive type opposite to said first conductive type and incorporating the impurity contained in said impurity gas into the surface of said semiconductor substrate, thereby modifying the type and/or the intensity of the conductive type thereof. Provides devices having a channel length of 0.5 &mgr;m or less and impurity regions 0.1 &mgr;m or less in depth.

Abstract: Divot fill methods of incorporating thin SiO2 spacer and/or annealing caps into a complementary metal oxide semiconductor (CMOS) processing flow are provided. In accordance with the present invention, the divot fill processes provide a means for protecting the exposed surfaces of the thin SiO2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning step. CMOS devices including thin SiO2 spacer and/or annealing caps whose surfaces are protected such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps are also provided.

Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with first the insulating film serving as a dielectric. The effective aperture ratio can be increased by forming the auxiliary capacitor in a selected region where the influences of alignment disorder of liquid crystal molecules, i.e., disclination, are large.

Abstract: A split gate EEPROM memory device formed on a doped silicon semi-conductor substrate starting with an initial oxide layer with an undoped first polysilicon layer formed thereon. A polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide layer and the undoped first polysilicon layer which are then etched to form a floating gate electrode stack from the undoped first polysilicon layer and the initial oxide layer on the substrate. Then form a tunnel oxide layer and a doped polysilicon and pattern them into control gate electrode stack, with the control gate electrode stack being located in a split-gate configuration with respect to the floating gate electrode stack.

Abstract: A semiconductor device comprises a semiconductor substrate; a semiconductor layer having a higher resistance than that of said semiconductor substrate and provided on a top surface of said semiconductor substrate; a gate electrode provided on a gate insulating film on the top surface of said semiconductor layer; a drain layer of a first conductivity type selectively provided in a location in said semiconductor layer in one side of said gate electrode; a drain electrode connected to said drain layer; a source layer of the first conductivity type selectively provided in a location in said semiconductor layer in the other side of said gate electrode; an element-side connecting portion selectively provided on said semiconductor layer, which does not reach a channel portion between said source layer and said drain layer of said semiconductor layer and also does not reach to said semiconductor substrate, and which is in contact with said source layer and has lower resistance than that of said semiconductor layer; a

Abstract: A nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate having a main surface, and a plurality of memory cell transistors which are formed above the main surface via a tunnel oxide film and which have sources and drains. And at least one of the sources and drains include nitrogen so that the oncentration peak is located in the vicinity of the surface.

Abstract: There is provided a semiconductor device including a transistor formed by means of a common contact hole that connects a gate electrode, and a diffused layer forming a source/drain terminal; and a semiconductor device comprising the gate electrode of the transistor, and a connecting terminal to which capacitance between substrates and capacitance between the gate electrode and the source/drain terminal are added, thereby improving the soft error resistance caused by alpha rays and neutron beams.

Abstract: A semiconductor device with a SOI structure comprises; a SOI substrate having a buried insulating film and a first conductivity type surface semiconductor layer on the buried insulating film; second conductivity type source and drain regions formed in the surface semiconductor layer; and a gate electrode formed over a first conductivity type channel region between the source and drain regions via a gate insulating film, wherein the source and drain regions are thinner than the surface semiconductor layer, and the channel region in the surface semiconductor layer has a first conductivity type high-concentration impurity diffusion region whose first conductivity type impurity concentration is higher than that in a surface of the channel region and which is adjacent to the buried insulating film.

Abstract: A charge transfer device having a charge transfer portion in which a plurality of electrode pairs are formed above a transfer channel, with the plurality of electrode pairs commonly wired forming N (where N=2, 3, 4, . . . natural numbers) bits of the charge transfer portion bits so that electrode pairs of each half bit can be independently driven at every N bits, inputting the electrode pairs of each half bit with the same drive pulse to operate it by a two-phase complementary drive in a normal operation, and in an N-time speed operation, inputting the electrode pairs of N bits with N pairs of complementary drive pulses to operate them by a 2N-phase complementary drive.

Abstract: A method of forming conductive contacts to drain and source regions of a semiconductor device such as a field effect transistor (FET). A gate structure is formed over a portion of a semiconductor substrate, wherein the gate structure includes: a gate dielectric on a surface of the semiconductor substrate, a conductive gate aligned on the gate dielectric, a silicide layer aligned on the conductive gate, and a silicon nitride cap aligned on the silicide layer. Insulative spacers are formed on sidewalls of the gate structure, and the insulative spacers contact the semiconductor substrate. A drain region and a source region are formed within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate structure is over the channel region.

Abstract: A semiconductor substrate has at least one PN junction with dopant atoms at the junction. A non-dopant at the junction provides interstitial traps to prevent diffusion during annealing. In a process for making this, a non-dopant diffusion barrier, e.g., C, N, Si, F, etc., is implanted into the “halo” region of a semiconductor device, e.g. diode, bipolar transistor, or CMOSFET. This combined with a lower annealing budget (“Spike Annealing”) allows a steeper halo dopant profile to be generated. The invention is especially useful in CMOSFETs with gate lengths less than about 50 nm.

Abstract: A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.