Abstract: An integrated circuit includes a diffusion layer, a first poly-silicon layer, and a second poly-silicon layer. The first poly-silicon layer is located on the diffusion layer to form a transistor. The second poly-silicon includes a first section and a second section. The first section of the second poly-silicon layer is located on the first poly-silicon layer to form a capacitor. The second section of the second poly-silicon layer is located on the diffusion layer to form a resistor.

Abstract: A semiconductor device has a silicon substrate, an external connection terminal disposed on the silicon substrate, an internal circuit region disposed on the silicon substrate, an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region, and a wiring connecting together the external connection terminal and the NMOS transistor and connecting together the NMOS transistor and the internal circuit region. The NMOS transistor has a drain region and a gate electrode whose potential is fixed to a ground potential. The external connection terminal is smaller than the drain region and is formed above the drain region.

Abstract: Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element.

Abstract: An electrostatic discharge circuit between a first pad and a second pad including an electrostatic discharge circuit element, including a bipolar transistor path and a resistor path, the electrostatic discharge circuit element alternately discharging an electrostatic current through the bipolar transistor path and the resistor path.

Abstract: A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.

Abstract: A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device.

Abstract: An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I/O device have a better ESD protection capability.

Abstract: Disclosed is an electrostatic discharge protection device that has a low trigger voltage and protects an internal circuit from electrostatic discharge. The ESD protection device includes an NMOS transistor in which a first pad and a drain are connected to each other and a second pad and a source are connected to each other. A capacitor in which an end is connected to the first pad and the other end is connected to a gate of the NMOS transistor and a substrate contact of the NMOS transistor. The ESD protection devices also includes a resistor in which an end is connected to the second pad and the other end is connected to the capacitor. The first pad may be a power pad and the second pad may be a ground pad. Alternately, the first pad may be an input/output pad and the second pad may be a ground pad.

Abstract: A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse.

Abstract: A single semiconductor power module includes a power semiconductor chip including an embedded IGBT (the power semiconductor switching-device) and a control semiconductor chip. The power semiconductor chip also includes a gate series resistor integrated therein as a resistor through which the control semiconductor chip drives the power semiconductor chip. In such a configuration, a gate wire between the gate series resistor and a gate has a small lead inductance and a small parasitic capacitance with respect to the ground.

Abstract: An electrostatic discharge (ESD) protection network for power MOSFETs includes parallel branches, containing polysilicon zener diodes and resistors, used for protecting the gate from rupture caused by high voltages caused by ESD. The branches may have the same or independent paths for voltage to travel across from the gate region into the semiconductor substrate. Specifically, the secondary branch has a higher breakdown voltage than the primary branch so that the voltage is shared across the two branches of the protection network. The ESD protection network of the device provides a more effective design without increasing the space used on the die. The ESD protection network can also be used with other active and passive devices such as thyristors, insulated-gate bipolar transistors, and bipolar junction transistors.

Abstract: An electrical resistance is produced in a semiconductor device by first providing a semiconductor resistor structure that includes a semiconductor resistor having formed thereon a native oxide layer. A portion of the native oxide layer that overlies a corresponding top surface portion of the semiconductor resistor is removed, in order to expose the top surface portion of the semiconductor resistor. Metal is deposited on the exposed top surface portion of the semiconductor resistor. A chemical reaction is effectuated in order to reduce the likelihood of metal reacting with the underlying silicon on any portion of the semiconductor resistor other than the top surface portion thereof. The chemical reaction can be an oxidation reaction that produces on the semiconductor resistor structure an oxide layer other than the native oxide layer and substantially thicker than the native oxide layer.

Abstract: An ESD protection device includes: a semiconductor substrate of a first conductivity type having a first major surface and a second major surface; a signal input electrode formed on the first major surface of the semiconductor substrate; a base region of a second conductivity type formed on a surface region of the second major surface of the semiconductor substrate; a diffusion region of the first conductivity type; a resistor layer formed on the second major surface of the semiconductor substrate of the first conductivity type; a signal output electrode electrically connected to the diffusion region of the first conductivity type; and a ground electrode electrically connected to the resistor layer. The diffusion region is selectively formed on a surface region of the base region of the second conductivity type in the semiconductor substrate of the first conductivity type. The resistor layer is electrically connected to the diffusion region of the first conductivity type.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract: A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage, a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage, an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage, and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a cond

Abstract: An electrostatic discharge (ESD) protection clamp (61) for I/O terminals (22, 23) of integrated circuits (ICs) (24) comprises an NPN bipolar transistor (25) coupled to an integrated Zener diode (30). Variations in the break-down current-voltage characteristics (311, 312, 313, 314) of multiple prior art ESD clamps (31) in different parts of the same IC chip is avoided by forming the anode (301) of the Zener (30) in the shape of a base-coupled P+ annular ring (75) surrounded by a spaced-apart N+ annular collector ring (70) for the cathode (302) of the Zener (30).

Abstract: A method is provided of fabricating a thin film resistor semiconductor structure. In one aspect of the invention, the method includes forming a dielectric layer over a semiconductor substrate, forming a thin film resistor on the dielectric layer, and annealing the thin film resistor at a substantially high temperature for a predetermined time period to set the thermal coefficient of resistance of the thin film resistor. A passivation layer is formed over the semiconductor structure.

Abstract: An electric discharge device includes a bipolar transistor configuration comprising a base, an emitter, and a collector. At least one pinched resistor is formed in a region comprising both the base and emitter so as to produce a pinched resistive area that develops a voltage once the bipolar transistor experiences junction breakdown.

Abstract: A semiconductor device capable of preventing an electrostatic surge without increasing a leak current. In the semiconductor device, a protection circuit for protecting an internal circuit is provided between a source line and a ground line. The protection circuit has a protection transistor of which the drain is connected to the source line and the source and gate are connected to the ground line. The protection transistor is configured by integrally forming two types of transistor structural portions. The latter of the transistor structural portions is longer than the former thereof in gate length. In addition, the sum of gate widths of the latter transistor structural portions is larger than the sum of gate widths of the former transistor structural portions.

Abstract: An ESD protection structure includes, in part, a NMOS transistor having a source and drain in a well in a substrate and a gate on the substrate with the source and drain being connected between ground and a series diode, and the gate being connected to ground. The structure further includes a diode having a cathode connected to the input pad and an anode connected to the well so that the diode is reverse-biased in the event of a positive voltage ESD event on the input pad. As a result, in a positive voltage ESD event, the avalanche effect rapidly injects current into the substrate and therefore into the base of the parasitic bipolar transistor so as to trigger the transistor into conduction and discharge the ESD pulse. Alternatively, the diode is a Zener diode and the current is generated by the Zener effect. A complementary structure provides protection against a negative ESD pulse.

Abstract: A resettable short circuit protection configuration includes a power input terminal, a power output terminal, a first electrically controlled switch, which has a control end and two conducting ends, the two conducting ends being respectively electrically connected to the power input terminal and the power output terminal, a second electrically controlled switch, which has a control end and two conducting ends, the two conducting ends being respectively electrically connected to the power input terminal and the control end of the first electrically controlled switch, a first resistor, which has two opposite ends respectively electrically connected to the control end of the first electrically controlled switch and a grounding terminal, and a second resistor, which has two opposite ends respectively electrically connected to the control end of the second electrically controlled switch and the power output terminal.

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

Abstract: A wide bandgap device in parallel with a device having a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device.

Abstract: This invention discloses a ballasting resistor for an electrostatic discharge (ESD) device that comprises at least one first active region forming a source/drain of an ESD discharge transistor, at least one resistive element with a serpentine shape formed in a single layer of a semiconductor structure, wherein the resistive element has a first terminal coupled to the first active region and a second terminal coupled to a bonding pad including power supply (Vdd or Vss) pads.

Abstract: A layout structure for a CMOS circuit comprises a transistor layer forming P-type transistors 11 and 21 and N-type transistors 12 and 22, and a resistor layer which includes a resistor 13 formed to have a predetermined length and to make plural appropriate portions or the entire of the resistor along a direction of the length satisfy a mask rule necessary for providing VIAs, the resistor being connected to appropriate connecting portions of the P-type transistors and the N-type transistors through the VIAs by metal wires 31 formed of a metal layer, and the resistor having a predetermined circuit resistance which can be set based on the positions of the appropriate connecting portions.

Abstract: The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract: According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness.

Abstract: A semiconductor integrated circuit has complementary field-effect transistors, one formed in a semiconductor substrate, the other formed in a well in the substrate, and has four power-supply potentials: two supplied to the sources of the field-effect transistors, one supplied to the substrate, and one supplied to the well. An unwanted pair of parasitic bipolar transistors are formed in association with the field-effect transistors. An intentionally formed bipolar transistor operates in series with one of the unwanted parasitic transistors and as a current mirror for the other unwanted parasitic transistor, limiting the flow of unwanted current through the parasitic bipolar transistors.

Abstract: A semiconductor device includes an ESD protection device on a substrate, and a resistor having a gate structure overlying a resistor well separating a first doped region coupled to the ESD protection device and a second doped region coupled to a supply voltage for passing an ESD current from the second doped region to the first doped region to turn on the ESD protection device for dissipating the ESD current during an ESD event. The resistor well has an impurity density lower than that of the first and second doped regions for increasing resistance therebetween.

Abstract: Provided is a semiconductor device in which a resistor and a capacitor are inserted in an input/output signal line that connects an input/output pad and an internal circuit at an input/output terminal in order to prevent damage of the internal circuit due to static electricity. The semiconductor device includes the input/output signal line that connects the input/output pad and the internal circuit. A first electrostatic discharge (ESD) protection circuit is branched from the input/output pad and connected to a power supply line, and a second ESD protection circuit is branched from the input/output pad and connected to a ground line. The resistor is located in the input/output signal line, and the capacitor is branched from the power supply line between the power supply line and the resistor.

Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.

Abstract: Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an associated microelectronic circuit for which ESD protection is desired. The SCR used in the ESD cell of the invention is provided with a full guardring for shielding the SCR from triggering by fast transients. A resistor is provided at the guardring for use in triggering the SCR at the onset of an ESD event. Exemplary preferred embodiments of the invention are disclosed with silicide-block resistors within the range of about 2-1000 Ohms or less.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.

Abstract: A semiconductor device comprises a semiconductor portion including first semiconductor layers of a first conduction type and second semiconductor layers of a second conduction type alternately arranged on the surface of a semiconductor substrate to form a striped shape. A main region is formed to arrange a main cell in a well. A current sense cell is arranged in a sense well. A sense region is formed having the direction of the length in a direction that intersects the direction of alternate arrangement of the first semiconductor layers and the second semiconductor layers.

Abstract: The present invention relates to a device for electrostatic discharge protection (ESD).

Abstract: A semiconductor integrated circuit device having a metal thin-film resistance includes a lower insulation film formed over a semiconductor substrate via another lawyer, a metal interconnection pattern formed on the lower insulation film, an underlying insulation film formed on the lower insulation film and the metal interconnection pattern, and a contact hole formed in said underlying insulation film on the metal interconnection pattern, wherein the metal thin-film resistance is formed so as to extend from a top surface of the underlying insulation film to the contact hole in electrical contact with the metal interconnection pattern in the contact hole, at least a part of constituting elements of the semiconductor integrated circuit other than the metal thin-film resistance is disposed in a region underneath the metal thin-film resistance.

Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.

Abstract: A semiconductor apparatus comprises a cell section including at least two transistors. A layer interval insulation coat is formed at least overlying the gate electrode use polysilicon and the gate contact use polysilicon. A source electrode metal coat is formed overlying the semiconductor substrate and insulated from the gate electrode use polysilicon and the gate contact use polysilicon, and is electrically connected to the body diffusion layer and the source diffusion layer. A gate use connection hole is formed on the layer interval insulation coat overlying the gate contact use polysilicon. The gate use connection hole has a width larger than that of the trench. A gate electrode metal coat is formed on the gate use connection hole and the layer interval insulation coat. The polysilicon coat is formed at the same level or lower than the surface of the semiconductor substrate.

Abstract: Current protection in integrated circuit having multiple pads. Different types of current protection structures may be associated with different pads. A common current discharge or charge path may be used to provide current to or draw current from various of these heterogenic current protection structures. Since a common current discharge or charge path is used, the metallization used to formulate a discharge solution is significant simplified. Additionally, the protection structures may be provided with selectively conductive regions that are approximately radially symmetrical around the circumference of the pad. Accordingly, if the protection structures are slightly off center with respect to the bond pad (due to, for example, mask alignment error), the error in the amount of active region around the circumference of the pad is at least partially averaged out.

Abstract: An integrated circuit structure including multiple thin film resistors having different sheet resistances and TCRs includes a first oxide layer (2) formed on a semiconductor substrate (1), a first thin film resistor (3) disposed on the first oxide layer (2), and a second oxide layer (14) disposed over the first oxide layer (2) and first thin film resistor (3). A second thin film resistor (15) is formed on the second oxide layer (14) and a third oxide layer (16) is formed over the second thin film resistor (15) and the second oxide layer (14). Interconnect metallization elements (12A,B & 22A,B) disposed on at least one of the second (14) and third (16) oxide layers electrically contact the circuit element (4), terminals of the first thin film resistor (3), and terminals of the second thin film resistor (15), respectively, through corresponding contact openings through at least one of the second (14) and third (16) oxide layers.

Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

Abstract: A method of fabricating a semiconductor device is disclosed. First, a substrate is provided. The substrate includes at least a transistor area having a gate structure thereon, a capacitor area having a first electrode thereon and a resistor area having a second electrode thereon. The capacitor area and the resistor area both have an isolation structure therein. Then, first spacers and source/drain regions on both sides of the gate are sequentially formed. After that, a dielectric layer and a first conductive material layer are sequentially formed on the substrate. Next, the first conductive material layer is patterned to form a third electrode in the capacitor area and a conductive layer in the resistor area. Then, second spacers are formed. Afterwards, the exposed dielectric layer is removed. Finally, a self-aligned silicide process is performed to form a metal salicide layer to cover the surface of the device.

Abstract: A device for electrostatic discharge (ESD) protection is disclosed. The device for electrostatic discharge protection includes a lateral bipolar transistor and a diode. The semiconductor transistor has an emitter, a base and a collector electrically connected to a first power line (such as Vdd), a second power line (such as Vss) and a bond pad of an integrated circuit respectively. The diode has an n electrode and a p electrode electrically connected to the first power line and the bond pad respectively.

Abstract: To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is connected to the output of the NMOS, to shift the output of the NMOS for boosting. Then, a back gate of the NMOS is connected, via a PMOS in an on state, to the power source. With this structure, the PMOS provides a resistor component when the output terminal short-circuits.

Abstract: A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A storage node layer is formed on the mold layer as well as in the first and second molding holes. The storage node layer is patterned to form storage nodes in the first molding holes and a portion of a resistor in the second hole.

Abstract: An electrostatic discharge (ESD) protection circuit for dissipating an ESD current from a first pad to a second pad during an ESD event. The ESD protection circuit includes a first bipolar transistor having an emitter coupled to the first pad. A second bipolar transistor having a base and a collector coupled to the second pad is used. Zero or more bipolar transistors are sequentially coupled between the first and second bipolar transistors in a base-to-emitter manner. A collector of the first bipolar transistor and the sequentially coupled transistors is connected to a base of a subsequently coupled bipolar transistor for helping to turn on the first, second and sequentially coupled bipolar transistors to provide a current path from the first pad to the second pad during an ESD event.

Abstract: A protection circuit protects an integrated circuit (“IC”) from peak voltages and includes a voltage divider coupled to a silicon controlled rectifier. The voltage divider allows for adjustment of the trigger voltage, trigger current, and holding voltage of the protection circuit so that the protection circuit can conduct current after a particular voltage level has been applied to the protection circuit without accidental triggering on by, for example, noise.

Abstract: With a microwave FET, the internalized Schottky junction capacitance or pn junction capacitance is small and these junctions are weak against static electricity. However, with a microwave device, a protecting diode could not be connected since the increase of parasitic capacitance resulting from this method causes degradation of the high frequency characteristics. Therefore, to eliminate this problem, a semiconductor device is provided, wherein two paths, extending from a gate electrode pad to a gate electrode on an operating region, are arranged, with one path running near a source electrode pad, the other path running near a drain electrode pad, and at the respective parts where a path becomes close to a pad, the abovementioned protecting elements are connected between the gate electrode and source electrode and between the gate electrode and drain electrode to improve the electrostatic breakdown voltage of the FET from approximately 100V to 700V.

Abstract: A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60?) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion.