Abstract: An insulated gate field effect transistor or a CMOS pair of transistors of a family of logic circuits includable in any type of integrated circuit, including microprocessors, memories and logic macros, and any or all functional portions thereof preferably forms an asymmetrical conduction device junction integrally with the gate structure to provide hysteresis that yields increased noise immunity and reduced power consumption and dissipation by asymmetric alteration of switching thresholds for positive and negative input signal transitions such that the turn-ON transition time or speed is slowed relative to the turn-OFF transition time or speed. The asymmetric conduction function is preferably provided by a polysilicon diode junction which is exposed and allowed to function as such by masking prior to application of a conductive material to the gate structure.

Abstract: A semiconductor (preferably a CMOS) device having one or more latch-up inhibitor diffusion regions. The latch-up inhibitor regions are adjacent to complementary P-channel and N-channel transistors, and typically function to inhibit or prevent latch-up, without increasing the die size of the device.

Abstract: The present invention provides a circuitry comprising: a first switching transistor connected in series between an output node and a first voltage supply line which supplies a fist voltage level, the first switching transistor having a first control gate receiving a first control signal; and a second switching transistor connected in series between the output node and a second voltage supply line which supplies a second voltage level which is lower than the first voltage level, the second switching transistor having a second control gate receiving a second control signal, so that the first and second switching transistors are connected in series between the first and second voltage supply lines, wherein the first switching transistor has a first sub-gate which is connected to the output node, and the second switching transistor has a second sub-gate which is connected to the second voltage supply line.

Abstract: A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, &agr;-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

Abstract: Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.

Abstract: A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.

Abstract: In important applications of circuits comprising transistors of the lateral DMOST type, such as (half) bridges, the voltage on the output may become higher or lower than the supply voltage or earth in the case of an inductive load. The injection of charge carriers into the substrate can be prevented by screening the drain (18) of the Low-Side transistor from the substrate by means of a p-type buried layer (13) and an n-type buried layer (14) below said p-type buried layer. In order to avoid parasitic npn-action between the n-type buried layer (14) and the n-type drain (18), not only the back-gate regions (16a, 16c) at the edge of the transistor, but also the back-gate regions (16b) in the center of the transistor, are connected to the p-type buried layer, for example by means of a p-type well. As a result, throughout the relatively high-ohmic buried layer, the potential is well defined, so that said npn-action is prevented.

Abstract: A bipolar transistor compatible with CMOS processes utilizes only a single layer of polysilicon while maintaining the low base resistance associated with conventional double-polysilicon bipolar designs. Dopant is implanted to form the intrinsic base through the same dielectric window in which the polysilicon emitter contact component is later created. Following poly deposition within the window and etch to create the polysilicon emitter contact component, large-angle tilt ion implantation is employed to form a link base between the intrinsic base and a subsequently-formed base contact region. Tilted implantation enables the link base region to extend underneath the edges of the polysilicon emitter contact component, creating a low resistance path between the intrinsic base and the extrinsic base. Fabrication of the device is much simplified over a conventional double-poly transistor, particularly if tilted implantation is already employed in the process flow to form an associated structure such as an LDMOS.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: Additional degrees of freedom are provided for optimizing the component properties by combining two doping profiles. The threshold voltage of NMOS or DMOS transistors can be set through the process parameters involved in the introduction and outward diffusion of the further dopant of the second conductivity type, independently of the deep concentration, since the dopant concentration at the surface can be chosen independently of the dopant concentration at depth. A low film resistance results from the great penetration depth of the semiconductor region through the combination of the two dopant profiles. The low film resistance leads to reduced pinching of the substrate current in an NMOS transistor, and to greater stability against “latch-up”, without substantially increasing the concentration of the dopants in the region of source/drain diffusions, and therefore without unfavorably affecting drain/bulk capacitance.

Abstract: A CMOS integrated circuit is formed on a P-type semiconductor layer and an N-type semiconductor layer in contact with the P-type semiconductor layer to establish a junction therebetween. A PMOS transistor is formed on the N-type semiconductor layer and configured with its source terminal connected to a first voltage source. An N-type contract region is formed in the N-type semiconductor layer and connected to the first voltage source. An NMOS transistor is formed on the P-type semiconductor layer and configured with its source terminal connected to a second voltage source. A P-type contact region is formed in the P-type semiconductor layer and connected to the second voltage source. Moreover, a P-type carrier-releasing region is provided with one portion formed in the N-type semiconductor layer and another portion formed in the P-type semiconductor layer to span the junction.

Abstract: A source region 3 and a back-gate region 4 are alternately arranged along one side of a gate electrode 2 in a power MOSFET. The back-gate region 4 is formed so as not to substantially include the region immediately below the gate electrode 2. Thereby, it is possible to prevent a parasitic bipolar transistor from operating while controlling the increase of a channel resistance and thus, the breakdown resistance is improved.

Abstract: A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (1) in a P-type semiconductor substrate (5), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (1B) of the well region (1). Then, the N-type well region (1) is formed which is shaped such that a portion (6) having P-type properties remains partially in the bottom portion (1B). The P-type portion (6) establishes electrical connection between a P-type well region (2) and the semiconductor substrate (5) to permit the potential applied to a contact region (4) to be supplied to the well region (2) therethrough. The portion (6) may include a plurality of portions (6) which allow uniform potential supply.

Abstract: In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.

Abstract: A silicon-on-insulator metallic oxide semiconductor structure having a double implanted source region. By etching a trench contact window in the double implanted source region and then depositing a metal into the trench to form a metal plug, contact between the source terminal and the substrate is established. Consequently, floating body effect of a silicon-on-insulator device is prevented without having to provide additional surface area to accommodate the contact window.

Abstract: A semiconductor device (10) having a stacked-gate buffer (30) wherein the stacked-gate buffer (30) has a substrate (65) and a top substrate region (70) both with the same first conductivity type. The buffer (30) also has two transistors (95.105), each with a current carrying electrode and a control electrode (90, 100). A deep doped region (120) lies between the first (90) and second (100) control electrodes where the deep doped region (120) is another current carrying electrode for the first transistor (95) and another current carrying electrode for the second transistor (105) and the deep doped region (120) has a second conductivity that is opposite the first conductivity type. A deeper doped region (80) is also part of the stacked-gate buffer which has a second conductivity type and lies between the first (90) and second (100) control electrodes and is deeper than the deep doped region (120). A method of forming the device is also provided herein.

Abstract: A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second a-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron

Abstract: A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.

Abstract: A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.

Abstract: A circuit configuration for reducing an injection of minority carriers into a substrate protects against malfunction due to injected minority carriers by providing a series circuit connected to an external terminal. The series circuit has a transistor and a diode disposed between a supply potential and the external terminal and fed back through a control loop from the external terminal to a control terminal of the transistor.

Abstract: A semiconductor device includes an N-well arranged in the principal surface of a P-type semiconductor substrate, an N.sup.+ well contact arranged in the principal surface of the N-well, and an N.sup.+ buried region arranged to the bottom of the N-well.

Abstract: An arrangement that prevents triggering of latchup in internal circuits by input/output buffers on an integrated circuit chip provides a space surrounding each active device connected to a bond pad. A ring well surrounds the space and separates the active device from the internal circuits of the chip. The ring well serves as a collector to prevent triggering latchup by the active device of the internal circuits located outside the ring well.

Abstract: A semiconductor integrated circuit has a semiconductor substrate on which macrocells are formed. At least one of the macrocells is surrounded by a first diffused region, which may be surrounded by a second diffused region. The first and second diffused regions are connected to power source terminals, respectively. Semiconductor elements included in each macrocell are connected to power source terminals that are independent of the terminals connected to the diffused regions. Alternatively, a voltage is supplied to the diffused regions through power lines that are different from power lines for the semiconductor elements. This arrangement absorbs short-circuit current in CMOS circuitry and/or substrate current produced by the semiconductor elements.

Abstract: Level shift devices are formed in the high voltage termination region of an integrated circuit. The level shift devices provide a connection between the higher voltage, floating circuit and a ground referenced lower voltage circuit. The structure of the level shift devices eliminates the need for a high voltage connector to cross over the low voltage connector.

Abstract: A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in improved isolation of a source/drain contact area and a storage node which may be formed thereat. For fabricate the structure, a source/drain region is formed in a substrate having a space charge in the bulk or major part thereof, the source/drain region including: a first region having a space charge with a polarity opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a polarity opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a polarity opposite that of the space charge of the second region.

Abstract: In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.

Abstract: An integrated power semiconductor component includes a substrate of a first conduction type. At least one first region of a second conduction type is embedded in the substrate and at least one second region of the second conduction type is embedded in the substrate. A substrate contact supplies a supply voltage. Contact-making semiconductor components are embedded in the first region and in the second region. At least a portion of the semiconductor components in the first region control at least a portion of the semiconductor components in the second region. A third region of the second conduction type is disposed between the first region and the second region, and the first region and the third region are at different potentials.

Abstract: An output driver is implemented by a complementary inverter circuit responsive to an output data signal for selectively charging and discharging an external capacitive load, and the complementary inverter circuit has a p-channel enhancement type field effect transistor formed in an n-type well defined in a p-type silicon substrate reversely biased and an n-channel enhancement type field effect transistor formed in a p-type well nested with a reversely biased n-type well defined in the p-type silicon substrate in spacing relation to the n-type well assigned to the p-channel enhancement type field effect transistor, thereby perfectly isolating the p-channel enhancement type field effect transistor from a noise propagated from a ground voltage line to the p-type well assigned to the n-channel enhancement type field effect transistor.

Abstract: A horizontal MOSFET prevents itself from breakdown caused by an avalanche current which flows to a base of a parasitic bipolar transistor when avalanche breakdown of a diode formed between a drain and a substrate occurs. A current path, comprised of a back electrode or a layer with high impurity concentration, is disposed on the side of a back surface of a semiconductor substrate. This current path reduces the base current of the parasitic transistor. Due to this, heat generation caused by an operation of the parasitic transistor is suppressed, and the avalanche withstand capability of the MOSFET is improved corresponding to reduction of the internal resistance component of the MOSFET.

Abstract: A low dropout linear regulator utilizing a vertical PNP transistor as its pass element, integrated with CMOS circuitry. The vertical PNP transistor includes a P-well formed in a lightly doped N type substrate for its collector. An N-type region formed in the P-well is its base and a P-type region formed in the N-type region is its emitter. The emitter receives a variable input supply and the collector provides a regulated output signal to the load being driven. As the input voltage diminishes to less than a diode drop above the output voltage, the vertical PNP transistor tries to saturate and its associated parasitic NPN transistor turns on. To limit the effects of the parasitic NPN transistor and maintain a regulated output, a current limiter is connected between the input and the collector of the NPN parasitic transistor.

Abstract: A data output buffer is disclosed. Generation of a latch-up is prevented by forming a N-well guard ring to interrupt the movement of minority carriers injected from the drain of NMOS transistor to the N.sup.+ pickup region of PMOS transistor. Accordingly, reliability of the device is improved.

Abstract: A bipolar transistor has a first semiconductor region of an n-type epitaxial layer surrounded by a first insulating film, a second insulating film of silicon oxide having an opening, a second semiconductor region as a base link region of a p-type formed in the opening and having a high impurity concentration and a thickness substantially the same as that of the second insulating film, a third semiconductor region as an intrinsic base of a p-type having a thickness thinner than that of the second insulating film, a sidewall insulating film covering the third semiconductor region, and a fourth semiconductor of a p-type formed on the third semiconductor region and surrounded by the side-wall insulating film. The reduction in the thickness of the intrinsic base is achieved without reducing the thickness of the base link region and thus it is possible to realize a bipolar transistor in which a cut-off frequency is high and yet the base resistance is low.

Abstract: A semiconductor device comprises a semiconductor substrate formed with at least one well containing impurity ions of either a first conductivity type or a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; the outer diffusion layer having an impurity concentration sufficient to provide a desired junction withstand voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; the impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power suppl

Abstract: An active pixel image sensor in accordance with the present invention utilizes guard rings, protective diffusions, and/or a combination of these two techniques to prevent electrons generated at the periphery of the active area from impacting upon the image sensor array. For example, an n+ guard ring connected to V.sub.cc can be imposed in the p-epi layer between the active area edge and the array, making it difficult for edge-generated electrons to penetrate the p+ epi in the array; this approach requires the use of annular MOS devices in the array. Alternatively, the gates of the n-channel devices in the array can be built to overlap heavily doped p+ bands, forcing current flow between the source/drain regions. As stated above, combinations of these two techniques are also contemplated. Elimination of the active area edge leakage component from the array can increase the dynamic range of the image sensor by 6 bits.

Abstract: A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

Abstract: A rugged MOS output stage transistor having a third region formed adjacent to the drain region on the side opposite the source. The third region is doped to have a polarity opposite the drain and forms in combination with the drain an output protect diode which renders the transistor relatively free of latch-up. The concept of the third region of opposite polarity adjacent to the drain may be used in both NMOSFET and PMOSFET as well as CMOS output stages.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: An integrated circuit device (10) is provided that comprises an P-FET (12) and an N-FET (14) formed on a semiconductor substrate (32). The P-FET (12) is formed in an n- tank (46). The source (18) and back-gate contact (22) of the P-FET (12) are connected to the V.sub.DD supply voltage. A current sink region (50) is formed in contact with the bulk semiconductor substrate (32). Periodic back-gate contacts (30) and (52) are made to the current sink region (50). The source (26) of N-FET (14) is also connected to the back-gate contacts (30) and (52). The current sink region (50) provides a low resistance path for charge within the substrate (32) to paths to the supply voltage V.sub.SS. This low resistance path prevents voltage from building up in the substrate (32) and thereby prevents latchup from occurring.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: The present invention is directed to a CMOS inverter in which an N-FET (Qn) formed of an N-type source region (2S), a drain region (2D) and a gate electrode (2G) and a P-FET (Qp) formed of a P-type source region (3S), a drain region (3D) and a gate electrode (3G) are formed on an N-type silicon substrate (1n). A first well region (4p) is formed under the N-FET (Qn) and P-FET (Qp). Further, an N-type well region (5n) is formed on the P-FET (Qp) within the first well region (4p). Thus, an influence exerted by a back-gate effect from the substrate can be prevented completely, whereby a phase displacement relative to a pulse response to a CMOS peripheral logic circuit and a malfunction can be avoided.

Abstract: A novel process is taught for forming diodes simulataneouly with the formation of typical prior art Ldd MOS devices. The diodes thus formed have low breakdown voltages, making them suitable for use as voltage reference diodes, or diodes for ESD protection.

Abstract: A back biasing technique is provided for increasing the field inversion voltage between adjacent MOS transistors and for reducing parasitic capacitances in an integrated circuit. The use of a charge pump is avoided by connecting the body portions of the MOS transistors to ground and the sources of the MOS transistors to the anode of a diode, the cathode of which are connected to a reference voltage such as to ground. In this manner, the sources are back biased relative to the material in which they are formed by a diode forward voltage drop. This technique is particularly applicable to CMOS circuits operating from a 3.3 volt supply, with p-well doping densities in excess of 1.times.10.sup.17 atoms/cm.sup.3.

Abstract: A diode implemented in a junction isolated process protected from minority carrier substrate injection is disclosed. In a preferred embodiment, a diode includes an N+ cathode region and a P+ anode region formed in a P epitaxial region, and an N+ isolation region enclosing the epitaxial region. A CMOS inverter connected to the cathode region shorts the isolation region to either the cathode or the grounded substrate, depending on the voltage at the cathode, and thereby prevents minority carrier injection into the substrate in all conditions.

Abstract: A CMOS circuit formed in a semiconductor substrate having improved immunity to radiation induced latch-up and improved immunity to a single event upset. The circuit architecture of the present invention can be utilized with N-Well, P-Well and dual Well processes. For example, the circuit is described relative to an N-Well process. An N-Well is formed in a p-type substrate. A network of p-channel transistors are formed in the N-Well and a network of n-channel transistors are formed in the p-type substrate. A continuous P+guard ring is formed surrounding the n-channel transistors and between the n-channel transistors and the N-Well. Similarly, a continuous N+guard ring is formed surrounding the p-channel transistors and between the p-channel transistors and the p-type substrate. In the event of a radiation hit, the guard rings operate to reduce the parasitic impedance in the collector circuits of the parasitic bipolars forming a parasitic SCR and also act as additional collectors of radiation induced current.

Abstract: A semiconductor memory device in accordance with the present invention includes a plurality of n well regions and p well regions in a p type silicon substrate. One of the p well regions is connected to an external power supply. Peripheries of the p well region having a memory cell array formed therein are surrounded by an n well region having a potential held at a positive potential. The n well region held at the positive potential prevents electrons introduced into the substrate due to undershoot from entering into a p well region through the p well region connected to the external power supply.

Abstract: In a semiconductor device, a FET and an isolation are provided on a semiconductor substrate and a channel stop region is provided under the isolation. At least a region to which a high voltage is applied of a source region and a drain region of the FET is separated from the channel stop region, and a first buffer region doped with an impurity for adjusting the threshold level is provided therebetween. A region under a gate electrode and adjacent to the isolation serves as a second buffer region to which an impurity for adjusting the threshold level is doped. With the first buffer region, a depletion region at a boundary of the drain region and the channel stop region is ensured, obtaining a superior durability to high voltage of the source/drain region. With the second buffer region, leakage current between the source region and the drain region is prevented.

Abstract: A method of fabrication of an semiconductor device comprises applying an impurity of a predetermined polarity to a silicon substrate; forming a well by applying an impurity of an opposite polarity to a region in the silicon substrate; forming a first masking layer on the surface of the substrate; providing openings in the masking layer and implanting dopant ions of a first polarity into the surface of the substrate in a set of first regions selected in the substrate and the well forming a second masking layer on the surface of the substrate; implanting dopant ions of a second polarity through a second mask in other regions selected in the well and the substrate; removal of the second masking layer; formation of field oxide structures over the first and second regions; forming gate oxide layers above the exposed portions of the first and second central regions; and formation of conductive gate structures over the gate oxide layers.

Abstract: A semiconductor device having a source follower circuit is configurated in such a way that a first and a second p-type wells are formed by diffusing a p-type impurity into an n-type semiconductor substrate doped with an n-type impurity of a low density. Next, on the first well, a driver transistor of the source follower circuit and then, on the second well, a load transistor of the source follower circuit are formed. The first well and a source of the driver transistor are then connected to each other.

Abstract: Disclosed herein is a Bi-CMOS IC which includes a semiconductor substrate of one conductivity type, a semiconductor layer of an opposite conductivity type formed on the substrate, a buried region of the opposite conductivity type formed between a first part of the semiconductor layer and the substrate and elongated under a second part of the semiconductor layer to form an elongated buried portion, a bipolar transistor formed in the first part by using the first part as a collector region thereof, a semiconductor region of the one conductivity type formed in the second part in contact with the elongated buried portion separately from the substrate, and an insulated gate transistor formed in the semiconductor region.

Abstract: A semiconductor memory device, e.g., a DRAM, which includes a P-type semiconductor substrate, a memory array each memory cell of which includes at least one N-channel MOS transistor, a CMOS peripheral circuit at least partially surrounding the memory array, the peripheral circuit including at least one P-channel MOS transistor formed in an N-type well region formed in the substrate, and at least one N-channel MOS transistor formed in the substrate outside of the N-type well region, and, a P-type minority carrier absorption semiconductor region formed in the substrate between the N-type well region and the memory array. The minority carrier absorption semiconductor region is preferably connected to a source of negative voltage, e.g., the substrate bias voltage, and a separate N-type region formed in the N-type well region is preferably connected to a source of positive voltage, e.g., the power supply voltage, Vdd, of the memory device.