Abstract: The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer.

Abstract: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract: A MOSFET transistor comprising a substrate of semiconductor material having a source junction connected to a source electrode, a drain junction connected to a drain electrode, and a gate layer connected to a gate electrode, the source junction or the drain junction being a metal-semiconductor junction.

Abstract: A semiconductor device, which can improve the effect of a hydrogenation treatment in case of using a GOLD structure, and a method of manufacturing thereof is provided. A gate insulating film is formed on a semiconductor layer, and a source region, a drain region, and LDD regions are formed in the semiconductor layer. A main gate is formed on the gate insulating film. A sub-gate is formed on the main gate and the gate insulating film so as to cover a part of the main gate and either the LDD regions adjacent to the source region or the drain region. An interlayer insulating film containing hydrogen is formed on the sub-gate, main gate, and gate insulating film. Subsequently, a heat treatment for hydrogenation is performed to terminate a crystal defect of the semiconductor layer with hydrogen.

Abstract: A fabrication method of a self-aligned power semiconductor structure is provided. Firstly, a trenched polysilicon gate is formed in a silicon substrate. Then, a self-aligned polysilicon extending structure is formed on the trenched polysilicon gate. A width of the self-aligned polysilicon extending structure is smaller than that of the trenched polysilicon gate. Thereafter, the self-aligned polysilicon extending structure is oxidized to form a silicon oxide protruding structure on the trenched polysilicon gate. Then, a first spacer is formed on a sidewall of the silicon oxide protruding structure to define a source contact window.

Abstract: The invention provides a method for forming a contact plug, comprising: forming a gate, a sidewall spacer, a sacrificial sidewall spacer, a source region and a drain region on a substrate, wherein the sidewall spacer is formed around the gate, the sacrificial sidewall spacer is formed over the sidewall spacer, and the source region and the drain region are formed within the substrate and on respective sides of the gate; forming an interlayer dielectric layer, with the gate, the sidewall spacer and the sacrificial sidewall spacer being exposed; removing the sacrificial sidewall spacer to form a contact space, the sacrificial sidewall spacer material being different from that of the gate, the sidewall spacer and the interlayer dielectric layer; forming a conducting layer to fill the contact space; and cutting off the conducting layer, to form at least two conductors connected to the source region and the drain region respectively.

Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.

Abstract: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.

Abstract: An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate comprises: a substrate; a first oxide layer formed above the substrate; a second oxide layer formed above the first oxide layer with a channel part interposed therebetween; a gate insulating film formed above the substrate, the first oxide layer and the second oxide layer; a gate electrode and a gate wire formed above the gate insulating film.

Abstract: A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided.

Abstract: It is provided a method for forming a semiconductor device comprising: forming a material layer which exposes dummy gates and sidewall spacers and fills spaces between two adjacent gate stacks, and the material of the material layer is the same as the material of the dummy gate; removing the dummy gates and the material layer to form recesses; filling the recesses with a conductive material, and planarizing the conductive material to expose the sidewall spacers; breaking the conductive material outside the sidewall spacers to form at least two conductors, each of the conductors being only in contact with the active region at one side outside one of the sidewall spacers, so as to form gate stack structures and first contacts. Besides, a semiconductor device is provided. The method and the semiconductor device are favorable for extending process windows in forming contacts.

Abstract: A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.

Abstract: An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer. An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

Abstract: Silicide films with high quality are formed with treatment of laser light irradiation, so that miniaturization and higher performance is achieved in a field-effect transistor that is formed over an insulating substrate and has little variation in electric characteristics. An island-shaped semiconductor film including a pair of impurity regions and a channel formation region is formed over an insulating substrate, a first metal film is formed on the pair of impurity regions, and a second metal film that functions as a reflective film is formed over a gate electrode located over the channel formation region with a gate insulating film interposed therebetween. The first metal film is irradiated with laser light and a region where the second metal film is formed reflects the laser light, so that the island-shaped semiconductor film and the first metal film selectively react with each other in the pair of impurity regions.

Abstract: A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a lower end in electrical contact with first and second transistor elements, respectively; one or more intermediate metal pillars disposed between and in electrical contact with an upper end of the metal pillars; and one or more separation regions of dielectric disposed below the intermediate metal pillar and between the lower ends of the first and second metal pillars.

Abstract: Metal contacts are self-positioned on a wafer of semiconductor product. Respective placement areas for a metal contact are determined by a selective deposition of a growth material over a region of the substrate surface (for example, through epitaxial growth). The growth material is surrounded by an insulating material. The grown material is then removed to form a void in the insulating material which coincides with the desired location of the metal contact. This removal of the grown material exposes the region on the substrate surface. Conductive material is then deposited to fill the void and thus form the metal contact directly with the region of the substrate surface.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode, a source region and a drain region, forming a first metal layer, forming silicide layers by first annealing, removing a remainder of the first metal layer after the first annealing, performing a second annealing, forming a second metal layer, performing a third annealing, and removing a remainder of the second metal layer.

Abstract: A semiconductor device 100 includes: a silicon substrate 102; a first gate 114a including a gate electrode 108 formed on the silicon substrate 102 and sidewalls 112 formed on the sidewalls of the gate electrode 108; a silicide layer 132 formed lateral to the sidewalls 112 of the first gate 114a on a surface of the silicon substrate 102; and a contact 164 which overlaps at least partially in plan view with the first gate 114a and reaches to the silicide layer 132 of the surface of the silicon substrate 102; wherein an insulator film is located between the contact 164 and the gate electrode 108 of the first gate 114a.

Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.

Abstract: A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device may further include a protrusion type isolation layer filling the concave portion and extending upward so that an uppermost surface of the isolation layer is a at level higher that an uppermost surface of the convex portion.

Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.

Abstract: A method of fabricating a self-aligned contact in a semiconductor device, in accordance with one embodiment of the present invention, includes etching a trench in a core area and partially extending into a termination area of a substrate. A first oxide is grown on the substrate proximate the trench. A polysilicon layer is deposited in the core area and the termination area. The polysilicon layer is selectively etched to form a gate region in the core area portion of the trench. The etching of the polysilicon layer also forms a first portion of a gate interconnect region in the termination area portion of the trench and a second portion in the termination area outside of the trench.

Abstract: A semiconductor device 1 according to one embodiment of the invention includes: a semiconductor substrate 10; a convex region 12 provided on the semiconductor substrate 10; a gate insulating film 100 provided on the convex region 12; a channel region 101 located in the convex region 12 under the gate insulating film 100; source/drain regions 115 provided on both sides of the convex region 12 and having extensions 115a on both sides of the channel region 101; and a halo layer 110 provided between the convex region 12 and the source/drain region 115 so as to contact with the convex region 12.

Abstract: Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer (10) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI (2) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer (11) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.

Abstract: An excessive metallic film on a device isolation region is prevented from contributing to silicidation in an end of a source-drain diffusion layer region to thereby form a silicide film with uniform film thickness. There are sequentially conducted a step of forming a device isolation region 3 in a substrate 1 including a silicon layer at least in a surface thereof and filling a first insulator in the device isolation region 3, a step of making height of an upper surface of the first insulator less than height of an upper surface of the substrate 1 and forming a sidewall film 10 on a sidewall of the device isolation region 3, and a step of depositing a metallic film 11 on the substrate 1 and then conducting silicidation through a thermal process.

Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.

Abstract: A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; Si:C layers formed on the semiconductor substrate in sides of the gate electrode; p-type source/drain regions formed in sides of the gate electrode in the semiconductor substrate, and a part of the p-type source/drain regions being formed in the Si:C layers; and silicide layers formed on the Si:C layers.

Abstract: Semiconductor devices include a substrate having first and second active regions; a P-channel transistor associated with the first active region and including at least one of source and drain regions; an N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; first and second contact pad layers each including silicon (Si) and SiGe epitaxial layers on the source and drain regions the SiGe epitaxial layers being sequentially stacked on the Si epitaxial layers; an interlayer insulating film; a first metal silicide film on the SiGe epitaxial layer of the P-channel transistor and a second metal silicide film on the Si epitaxial layer of the N-channel transistor; and contact plugs on the first and second metal silicide films.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

Abstract: An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure.

Abstract: A thin-film semiconductor device including a transparent insulating substrate, an island semiconductor layer formed on the transparent insulating substrate and including a source region containing a first-conductivity-type impurity and a drain region containing a first-conductivity-type impurity and spaced apart from the source region, a gate insulating film and a gate electrode which are formed on a portion of the island semiconductor layer, which is located between the source region and the drain region, a sidewall spacer having a 3-ply structure including a first oxide film, a nitride film and a second oxide film, which are respectively formed on a sidewall of the gate electrode, and an interlayer insulating film covering the island semiconductor layer and the gate electrode.

Abstract: Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the structure; forming a contact hole in the dielectric layer to the first liner; forming a second liner in the contact hole including over the first liner covering the sidewall; removing the first and second liners at a bottom of the contact hole; and filling the contact hole with a conductive material to form the contact. The thicker liner(s) over the sidewall of the structure prevents shorting, and allows for at least maintaining any intrinsic stress in one or more of the liner(s).

Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.

Abstract: A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

Abstract: By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.

Abstract: An integrated circuit includes a first thin film resistor on a first dielectric layer. A first layer of interconnect conductors on the first dielectric layer includes a first and second interconnect conductors electrically contacting the first thin film resistor. A second dielectric layer is formed on the first dielectric layer. A second thin film resistor is formed on the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. A second layer of interconnect conductors on the third dielectric layer includes a third interconnect conductor extending through an opening in the second and third dielectric layers to contact the first interconnect conductor, a fourth interconnect conductor extending through an opening in the second and third dielectric layers to contact the second interconnect conductor, and two interconnect conductors extending through openings in the third dielectric layer of the second thin film resistor.

Abstract: The semiconductor structure is provided that has entirely self-aligned metallic contacts. The semiconductor structure includes at least one field effect transistor located on a surface of a semiconductor substrate. The at least one field effect transistor includes a gate conductor stack comprising a lower layer of polysilicon and an upper layer of a first metal semiconductor alloy, the gate conductor stack having sidewalls that include at least one spacer. The structure further includes a second metal semiconductor alloy layer located within the semiconductor substrate at a footprint of the at least one spacer.

Abstract: A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one or both of misalignment during fabrication of the contacts and contact resistance between sections of the contacts. The contacts of one row communicate with every other active-device region and are staggered relative to the contacts of another row, which communicate with the remaining active-device regions. Each contact may include a relatively large contact plug with a relatively large upper surface to provide a relatively large amount of tolerance as a contact hole for an upper portion of the contact that is formed. The contact holes may be formed substantially simultaneously with trenches for conductive traces, such as bit lines, in a dual damascene process. Intermediate structures are also disclosed, as are methods for designing semiconductor device structures.

Abstract: A method of directly depositing a polysilicon film at a low temperature is disclosed. The method comprises providing a substrate and performing a sequential deposition process. The sequential deposition process comprises first and second deposition steps. In the first deposition step, a first bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a first polysilicon sub-layer on the substrate. In the second deposition step, a second bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a second polysilicon sub-layer on the first sub-layer. The first and second sub-layers constitute the polysilicon film, and the first bias voltage differs from the second bias voltage.

Abstract: A semiconductor device includes a dielectric film and gate electrode that are stacked on a substrate, sidewalls formed to cover the side surfaces of the electrode and dielectric film, and SiGe films formed to sandwich the sidewalls, electrode and dielectric film, filled in portions separated from the sidewalls, having upper portions higher than the surface of the substrate and having silicide layers formed on regions of exposed from the substrate. The lower portion of the SiGe film that faces the electrode is formed to extend in a direction perpendicular to the surface of the substrate and the upper portion is inclined and separated farther apart from the gate electrode as the upper portion is separated away from the surface of the substrate. The surface of the silicide layer of the SiGe film that faces the gate electrode is higher than the channel region.

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract: In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.

Abstract: An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory array region and the periphery region respectively, a silicon oxide spacer disposed on the gates, where the polysilicon contact plugs are formed by polysilicon deposition and chemical mechanical polish. After polysilicon contact plugs are formed, a silicon oxide layer is deposited to isolate the contacts and gate. The silicon oxide layer on top of contact plug is removed by chemical mechanical polish achieve planarization.

Abstract: A semiconductor device that suppresses variation and a drop in the breakdown voltage of transistors. In the semiconductor device in which a logic transistor and a high-breakdown-voltage transistor are formed on one Si substrate, an insulating film which has an opening region and which is thick around the opening region is formed on a low concentration drain region formed in the Si substrate on one side of a gate electrode of the high-breakdown-voltage transistor. The insulating film around the opening region has a two-layer structure including a gate insulating film and a sidewall insulating film. When ion implantation is performed on the low concentration drain region beneath the opening region to form a high concentration drain region, the insulating film around the opening region prevents impurities from passing through.

Abstract: A phase change memory device is provided in which the area of contact between phase change material and heater electrode is reduced to suppress current required for heating and a phase change region is formed directly on a contact to raise the degree of integration. The device comprises a heater electrode in which the lower part thereof is surrounded by a side wall of a first insulating material and the upper part thereof protruding from the side wall has a sharp configuration covered by a second insulating material except for a part of the tip end thereof, and the exposed tip end is coupled to the phase change material layer.

Abstract: A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes which extend in a first direction and are provided on the semiconductor region via gate insulation films, an insulation film provided on the group of transistors, and a first contact layer and a second contact layer extending in the first direction and provided on the semiconductor region at opposite sides of the group of transistors.

Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.