Abstract: A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

Abstract: A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

Abstract: Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misleading a reverse engineer. A method for fabricating such devices.

Abstract: The present invention provides a thin film resistor and method of manufacture therefor. The thin film resistor comprises a resistive layer located on a first dielectric layer, first and second contact pads located on the resistive layer, and a second dielectric layer located over the resistive layer and the first and second contact pads. In an illustrative embodiment, the thin film resistor further includes a first interconnect that contacts the first contact pad and a second interconnect that contacts the second contact pad.

Abstract: An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

Abstract: A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the first interlayer insulating film interposed therebetween. The second interlayer insulating film has a lower relative permeability than the first interlayer insulating film.

Abstract: A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of the first conductive type. The second source/drain region of the second conductive type is formed in a second well region of the first conductive type for a pair of second MIS-type transistors of the second conductive type. The first semiconductor region of the second conductive type is formed in the first source/drain region. The second semiconductor region of the first conductive type is formed in the second source/drain region.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over the semiconductor substrate and the gate electrode. An insulating layer may have a via hole connected to the semiconductor substrate or the gate electrode and a trench connected to the via hole. A first barrier layer and a second barrier layer may be formed. The first barrier layer and the second barrier layer may be annealed to form a silicide and combine the first barrier layer and the second barrier layer to form a metal compound.

Abstract: A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.

Abstract: An electric contact member which is excellent in voltage-proof performance and melt-resistant performance and excellent in mass productivity, and a method of manufacturing thereof, and a vacuum interrupter, a vacuum circuit breaker and a load-break switch for a road side transformer using thereof. The contact member is composed of a base member made of high conductive metal, and a contact layer made of refractory metal and high conductive metal, and the contact layer is formed of a plurality of thermal sprayed layers.

Abstract: A semiconductor device includes a semiconductor substrate, a T-shaped gate electrode, a moisture-proof insulating film, and an interlayer dielectric film. The T-shaped gate electrode has a leg portion joined to the semiconductor substrate and an overhanging head portion spaced from the semiconductor substrate. The T-shaped gate electrode includes a gate metal containing a material reactive with water. The moisture-proof insulating film is located only in the vicinity of the leg portion and covers a side surface of the leg portion of the T-shaped gate electrode. The interlayer dielectric film is located between the overhanging head portion of the T-shaped gate electrode and the semiconductor substrate and has a dielectric constant that is lower than that of the moisture-proof insulating film.

Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

Abstract: A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

Abstract: The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and thereby effectively eliminate the bondpad capacitance. Values of the components of the circuitry may be selectively and independently chosen to synthesize a variable range of negative capacitance and thus produce a negative capacitance approximately equal in magnitude to a unique capacitance associated with the bondpad of a variety of integrated circuits.

Abstract: A doping method includes the step of attaching molecules or clusters to the surface of a semiconductor substrate to enable charge transfer from the molecules or clusters to the substrate surface, thereby inducing carriers underneath the substrate surface. A semiconductor device is fabricated through attachment of molecules or clusters to the surface of a semiconductor substrate. The attachment enables charge transfer from the molecules or clusters to the substrate surface to induce carriers underneath the substrate surface.

Abstract: According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns and the gate pattern are covered with word line spacers and gate spacers having the same width as that of the word line spacers, respectively. The semiconductor substrate having the word line spacers and the gate spacers is covered with an interlayer insulating layer. A self-aligned contact hole formed in the interlayer insulating layer penetrates a predetermined region between the word line patterns. The self-aligned contact hole is formed by etching the interlayer insulating layer and the word line spacers. The side walls of the self-aligned contact hole are covered with a self-aligned contact spacer having a width different from that of the gate spacers.

Abstract: A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N+type source layer 11 and the height gap h2 between the gate electrode 10 and the N+type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.

Abstract: A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle.

Abstract: Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).

Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

Abstract: A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET.

Abstract: To effectively prevent intrusion of moisture into a space above an organic EL element, a moisture blocking layer made of a silicon-based nitride film such as SiNx or a TEOS film formed to cover a drain electrode and source electrode of a TFT is formed on the entire surface of the element. A sealing glass is attached to the moisture blocking layer by a sealing material on the peripheral region of the substrate. The intrusion of moisture from the outside is effectively prevented by the moisture blocking layer.

Abstract: A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.

Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.

Abstract: An annular segment MOSFET structure has reduced drain electric fields for a given applied voltage and dimensional sizing for improved reliability from damage by reducing high energy hot carriers laterally traversing the channel by reducing the intensity of electric fields in the MOSFET structure by creating diverging electric field lines with decreased electric field strength at the drain, while enabling compact integrated layouts of multiple MOSFETs within a square area of surface silicon.

Abstract: In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi2, use of the material having higher barrier height relation to n-Si for the barrier film increasing the contact resistance to n-Si and backwardly biasing the emitter and base of a parasitic bipolar transistor making it less tending to turn-on, thereby decreasing the leak current of power MISFET.

Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Abstract: A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of the thickness. The contact layer has a first member extending over at least a portion of the first surface and a second member spanning at least a portion of the sidewall.

Abstract: Disclosed is a method of forming an integrated circuit structure having first-type transistors, such as P-type field effect transistors (PFETs) and complementary second-type transistors, such as N-type field effect transistors (NFETs) on the same substrate. More specifically, the invention forms gate conductors above channel regions in the substrate, sidewall spacers adjacent the gate conductors, and source and drain extensions in the substrate. The sidewall spacers are larger (extend further from the gate conductor) in the PFETs than in the NFETs. The sidewall spacers align the source and drain extensions during the implanting process. Therefore, the larger sidewall spacers position (align) the source and drain implants further from the channel region for the PFETs when compared to the NFETs. Then, during the subsequent annealing processes, the faster moving PFET impurities will be restrained from diffusing too far into the channel region under the gate conductor.

Abstract: Methods of forming a contact to a gate electrode or substrate despite misalignment of the contact opening due to lithographic techniques, and a semiconductor having such a contact. Silicide can be created on the gate and/or diffusion using the invention.

Abstract: There is a method of manufacturing a semiconductor device. In an example embodiment, the method comprises applying a semiconductor substrate that is provided with a conductor at a surface. The conductor has a top surface portion and sidewall portions, of which at least the top surface portion is provided with an etch stop layer comprising silicon carbide. A dielectric layer is applied. A via is etched in the dielectric layer over the conductor and, and stopping on the etch stop layer to create an exposed part of the etch stop layer. Inside the via from at least the top surface portion of the conductor, the exposed part of the etch stop layer is removed. The via is filled with a conductive material.

Abstract: Field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs have a device channel and a gate above the device channel with a doped source/drain extension at said each end of the thin channel. A portion of a low resistance material layer (e.g., a silicide layer) is disposed on source/drain extensions. The portions on the doped extensions laterally form a direct contact with the doped source/drain extension. Any low resistance material layer on the gate is separated from the low resistance material portions on the source/drain extensions.

Abstract: Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.

Abstract: A processing sequence for definition of gate contacts can be implemented using either a deep ultra-violet (DUV) or mid ultra-violet (MUV) positive resist processing and supports the use of a reticle that integrates contacts to various regions including gates, sources and drains of various devices. In a one example, the wafer is coated with a planarizing anti-reflective coating (ARC), which then supports imaging of gate contacts using a positive DUV or MUV resist. This processing allows the nitride cap of certain transistor gates to be replaced with an oxide. In this example, the ARC can serve as an etch guide for selective removal of a film.

Abstract: A semiconductor device comprises: a semiconductor substrate; a gate insulating film formed on the top surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; diffusion layers formed in the semiconductor substrate to be used a source layer and a drain layer; and a silicide layer formed to overlie the diffusion layers; wherein an oxygen concentration peak, where oxygen concentration is maximized, is at a level lower than said top surface in a cross-section taken along a plane perpendicular to said top surface.

Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.

Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The conductive gate structure forms gates in device trenches in an active device region and forms a gate bus in a gate bus trench. The gate bus trench that connects to the device trenches can be wide to facilitate forming a gate contact to the gate bus, while the device trenches can be narrow to maximize device density. CMP process can be used to planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Abstract: The semiconductor device comprises a gate electrode 26 formed on a semiconductor substrate 10, a source region 45a having a lightly doped source region 42a and a heavily doped source region 44a, a drain region 45b having a lightly doped drain region 42b and a heavily doped drain region 44b, a first silicide layer 40c formed on the source region, a second silicide layer 40d formed on the drain region, a first conductor plug 54 connected to the first silcide layer and a second conductor plug 54 connected to the second silicide layer. The heavily doped drain region is formed in the region of the lightly doped region except the peripheral region, and the second silicide layer is formed in the region of the heavily doped drain region except the peripheral region. Thus, the concentration of the electric fields on the drain region can be mitigated when voltages are applied to the drain region.

Abstract: A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.

Abstract: Apparatus and methods forming electrostatic discharge and electrical overstress protection devices for integrated circuits wherein such devices include shared electrical contact between source regions and between drain regions for more efficient dissipation of an electrostatic discharge. The devices further include contact plugs and contact lands which render the fabrication of the devices less sensitive to alignment constraint in the formation of contacts for the device.

Abstract: A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate, forming a refractory metal layer on the Ti layer, forming a Si layer on the refractory metal layer, removing a portion of the Si layer, and heating to form a local interconnect structure. During this process, a source structure for the local interconnect is formed. This source structure comprises a Ti layer having a nitrogen-rich upper portion overlying a portion of a substrate, a refractory metal layer overlying the Ti layer, and a silicon layer overlying the refractory metal layer. The resulting local interconnect comprises a titanium silicide layer disposed on a portion of a substrate, a nitrogen-rich Ti layer disposed on the titanium silicide layer, and a refractory metal silicide layer disposed on the nitrogen-rich Ti layer.

Abstract: A semiconductor device has a SALICIDE structure with low leakage currents, while maintaining shallow source and drain regions. A method of manufacturing the semiconductor device includes forming source and drain regions in a first semiconductor layer, the source region and the drain region being separated from each other, forming a gate insulating film between the source region and the drain region on the first semiconductor layer; and forming a gate electrode on the gate insulating film. The method also includes forming a metal silicide layer showing a first compound phase on the source region, the drain region and the gate electrode, and forming a second semiconductor layer on the metal silicide layer showing the first compound phase where the second semiconductor layer is adapted to react with the metal silicide layer.

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The contacts are useful for providing electrical connection to active components beneath an insulation layer in integrated circuits such as memory devices. The conductive contacts comprise boron-doped TiCl4-based titanium nitride, and possess a sufficient level adhesion to the insulative layer to eliminate peeling from the sidewalls of the contact opening and cracking of the insulative layer when formed to a thickness of greater than about 200 angstroms.

Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 &mgr;m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.

Abstract: A field effect transistor (FET) has a channel formed in a pore extending up from a conductive portion of a substrate through a stack of planar layers including a first insulating layer, a gate layer, and a second insulating layer. The pore can be upright or inclined relative to the layers. A nanoparticle used for a mask of a directional etching process ultimately defines the size of the pore and therefore the channel width. The substrate or a doped region of the substrate formed immediately beneath the channel can be a source/drain of the FET with the other drain/source being a doped region adjacent the top of the channel. The gate layer can form the gate or can contact a separate gate inside the pore.

Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.

Abstract: A semiconductor device capable of easily setting the sheet resistance of a resistive element or the like to an arbitrary value is obtained. This semiconductor device comprises a first silicide film formed on a first silicon region and a second silicide film, formed on a second silicon region, consisting of the same silicide material as the first silicide film and differing from the first silicide film in film quality to have a sheet resistance value different from that of the first silicide film. When an impurity is introduced into the second silicide film itself so that the second silicide film differs from the first silicide film in film quality in this case, for example, a second silicide film having an arbitrary high sheet resistance value can be obtained by controlling the type of and an introduction condition for the impurity.

Abstract: A method of fabricating a salicided MOS and a one-sided salicided MOS device on a semiconductor substrate. A conformal oxide layer and an organic layer are sequentially formed on first and second MOS devices and the substrate. The first MOS has a first gate structure, a first spacer and first and second doped regions. The second MOS has a second gate structure, a second spacer and third and fourth doped regions. Anisotropic etching is performed to remove part of the organic layer until the oxide layer on the first and the second gate structures is exposed, wherein a remaining organic layer is left above the substrate. The oxide layer on the first and the second gate structures is removed. The remaining organic layer is removed. The oxide layer on the first, second, and third doped regions is removed. Thus, a silicide layer cannot form on the fourth doped region.