Three Or More Electrode Device Patents (Class 257/38)
-
Patent number: 5962864Abstract: A semiconductor device comprises mutually separated first and third barrier layers interposed between the first and second patterned terminals. The device operates by the resonant tunneling of carriers from the second terminal to the first terminal. The first terminal is patterned into a section and a plurality of layers comprising the mutually separated first and second barrier layers are formed on top of the first terminal. A second terminal is then formed on top of the plurality of semiconductor layers. The second terminal is then patterned so that it only overlies the first terminal in confined region. A front-gate is then formed on top of the patterned second terminal.Type: GrantFiled: August 15, 1997Date of Patent: October 5, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Mark L. Leadbeater, Nalin K. Patel
-
Patent number: 5717222Abstract: A superconducting device includes a substrate, a projecting insulating region formed in a principal surface of the substrate, and a first thin film portion of an oxide superconductor formed on the projecting insulating region. Second and third thin film portions of an oxide superconductor are positioned at opposite sides of the projecting insulating region to be continuous to the first thin film portion, respectively, so that a superconducting current can flow through the first thin film portion between the second thin film portion and the third thin film portion. The second thin film portion and the third thin film portion has a thickness larger than that of the first thin film portion. The projecting insulating region is formed of an oxide which is composed of the same constituent elements of the oxide superconductor but which has the oxygen content smaller than that of said oxide superconductor.Type: GrantFiled: May 23, 1996Date of Patent: February 10, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
-
Patent number: 5682041Abstract: An electronic part is disclosed which is furnished with an artificial super lattice obtained by alternately superposing a substance of good conductivity formed of a compound between one element selected from among the elements belonging to the transition elements of Groups 3A to 6A and the rare earth elements and an element selected from among boron, carbon, nitrogen, phosphorus, selenium, and tellurium or a compound between oxygen and a transition metal element selected from among the elements of Group 7A and Group 8 and an insulating substance formed of a compound between a simple metal element selected from among the elements belonging to Group 1A, Group 2A, and Groups 1B to 4B and an element selected from among carbon, nitrogen, oxygen, phosphorus, sulfur, selenium, tellurium, and halogen elements in thicknesses fit for obtaining a quantum size effect.Type: GrantFiled: May 21, 1996Date of Patent: October 28, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Kawakubo, Hideo Hirayama, Kenya Sano, Michihiro Oose, Junsei Tsutsumi
-
Patent number: 5665979Abstract: A Coulomb-blockade element includes a silicon layer formed on a substrate through an insulating film. The silicon layer includes a narrow wire portion and first and second electrode portions. The narrow wire portion serves as a conductive island for confining a charge. The first and second electrode portions are formed to be connected to the two ends of the narrow wire portion and are wider than the narrow wire portion. Each of the first and second electrode portions has constrictions on at least one of the upper and lower surfaces thereof, which make a portion near the narrow wire portion thinner than the narrow wire portion.Type: GrantFiled: November 13, 1996Date of Patent: September 9, 1997Assignee: Nippon Telegraph and Telephone CorporationInventors: Yasuo Takahashi, Masao Nagase, Akira Fujiwara
-
Patent number: 5621223Abstract: A superconducting device includes first and second oxide superconducting regions of a relatively thick thickness, formed directly on a principal surface of a substrate to be separate from each other, and a third oxide superconducting region of an extremely thin thickness which is formed directly on the principal surface of the substrate so as to bridge the first and second oxide superconducting regions. A barrier layer and a diffusion source layer are formed on the third oxide superconducting region, and an isolation region is formed to cover an upper portion or both side surfaces of the diffusion source layer. The first, second and third oxide superconducting regions and the isolation region are formed of the same oxide superconductor material, and the isolation region is diffused with a material of the diffusion source layer, so that the isolation region does not show superconductivity.Type: GrantFiled: August 16, 1995Date of Patent: April 15, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
-
Patent number: 5594257Abstract: A superconducting device comprises a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of an oxide superconductor formed on the principal surface, which can compensates the lattice mismatch between the substrate and the oxide superconductor, a superconducting source region and a superconducting drain region formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer, and an insulating region formed of a doped oxide superconductor on the non-superconducting oxide layer separating the superconducting source region and the superconducting drain region between them. On the insulating region an extremely thin superconducting channel formed of a c-axis oriented oxide superconductor thin film is arranged.Type: GrantFiled: June 24, 1993Date of Patent: January 14, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama
-
Patent number: 5552374Abstract: A superconducting device comprises a thin superconducting channel formed of an oxide superconductor, a superconducting source region and a superconducting drain region formed of an oxide superconductor at the both ends of the superconducting channel which connects the superconducting source region and the superconducting drain region, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region. The superconducting device further includes a gate electrode through a gate insulator on the superconducting channel for controlling the superconducting current flowing through the superconducting channel. The length of the gate electrode ranges from one third of the length of the superconducting channel to one and a half length of the superconducting channel.Type: GrantFiled: April 4, 1994Date of Patent: September 3, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: So Tanaka, Michitomo IIyama
-
Patent number: 5550389Abstract: A superconducting device low in power dissipation and high in operating speed is fabricated by use of a combination of a superconductor material and a semiconductor material. The superconducting device having a low power dissipation and high operating speed characteristic according to the present invention is suitable for configuring a large-scale integrated circuit.Type: GrantFiled: December 22, 1993Date of Patent: August 27, 1996Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Mutsuko Hatano, Haruhiro Hasegawa, Hideaki Nakane, Ushio Kawabe, Kazuo Saitoh, Mitsuo Suga, Kazumasa Takagi
-
Patent number: 5528052Abstract: Proposed is a method for operating a field-effect device comprised of a superconducting current channel having source and drain electrodes connected thereto, said superconducting current channel being separated from a gate electrode by an insulating layer, where the resistance of said current channel is controlled by varying the critical current of the superconducting material through the application of an electrical field across the superconducting current channel, which in turn changes the density of the mobile charge carriers in the superconducting material. Taught is also an inverted MISFET device for performing that method, the device being characterized in that on an electrically conductive substrate an insulating layer is provided which in turn carries a layer consisting of a superconducting material, and that a gate electrode is attached to said substrate, and source and drain electrodes are electrically connected to said superconductor layer.Type: GrantFiled: December 22, 1993Date of Patent: June 18, 1996Assignee: International Business Machines CorporationInventors: Johannes G. Bednorz, Jochen D. Mannhart, Carl A. Mueller, Darrell G. Schlom
-
Patent number: 5521862Abstract: A magnetic memory cell 10 is provided, which includes a layer 12 of superconducting material. A current path 22 is formed insulatively adjacent layer 12 of superconducting material, such that a current passed through current path 22 induces a magnetic field of a selected magnitude and selected orientation in layer 12 of superconducting material.Type: GrantFiled: November 10, 1993Date of Patent: May 28, 1996Assignee: Texas Instruments IncorporatedInventor: Gary A. Frazier
-
Patent number: 5506197Abstract: A superconducting device comprising a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, a first and a second superconducting regions formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer separated from each other and gently inclining to each other, a third superconducting region formed of an extremely thin c-axis oriented oxide superconductor thin film between the first and the second superconducting regions, which is continuous to the first and the second superconducting regions.Type: GrantFiled: September 16, 1994Date of Patent: April 9, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
-
Patent number: 5485017Abstract: A semiconductor device has an n.sup.+ source region, a first n.sup.- channel region, a barrier layer, a second n.sup.- channel region, a pair of n.sup.+ drain regions, an insulating film, and a pair of metal electrodes over the respective n.sup.+ drain regions, all successively disposed on an upper surface of an n.sup.+ crystal substrate. The drain regions and the metal electrodes jointly provide a storage electric capacitance. A source electrode is disposed on the lower surface of the n.sup.+ crystal substrate. Bit information can be written and read at a high speed by tunneling through the barrier layer. According to a method of manufacturing the above semiconductor device, the n.sup.+ source region, the first n.sup.- channel region, the barrier layer, the second n.sup.- channel region, the n.sup.+ drain regions, the insulating film, and the metal electrodes are successively deposited on the n.sup.+ crystal substrate in a growing apparatus.Type: GrantFiled: May 11, 1994Date of Patent: January 16, 1996Assignee: Zaidan Hojin Handotai Kenkyu ShinkokaiInventor: Jun-ichi Nishizawa
-
Patent number: 5471069Abstract: A superconducting device includes a superconducting channel constituted in an oxide superconductor the film deposited on a deposition surface of a substrate. A source electrode and a drain electrode are formed on the oxide superconductor thin film at opposite ends of the superconducting channel, so that a superconducting current can flow through be superconducting channel between the superconductor source electrode and the superconductor drain electrode. A gate electrode is formed through a gate insulator layer on the superconducting channel so as to control the superconducting current flowing through the superconducting channel. The gate electrode is in the form of a thin film and stands upright with respect to the gate insulator layer.Type: GrantFiled: May 13, 1994Date of Patent: November 28, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
-
Patent number: 5462918Abstract: A superconducting device has a stacked structure including a first superconducting layer, a first insulating layer, a second superconducting layer, a second insulating layer and a third superconducting layer stacked on a substrate in this given order. The stacked structure has an end surface portion extending from the first insulating layer to the second insulating layer. A fourth superconducting layer is formed to cover the end surface of the stacked structure. A third insulating layer separates the stacked structure end surface and the fourth superconducting layer. The fourth superconducting layer is electrically connected to the first and third superconducting layers but is isolated from the second superconducting layer by the third insulating layer. The first through fourth superconducting layers are formed of an oxide superconductor thin film.Type: GrantFiled: May 26, 1994Date of Patent: October 31, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
-
Patent number: 5446015Abstract: For manufacturing a superconducting device, a first oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. A second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film, using the gate electrode as a mask, so that first and second superconducting regions having a relatively thick thickness are formed at opposite sides of the gate electrode, electrically isolated from the gate electrode. A source electrode and a drain electrode are formed on the first and second oxide superconducting regions. The superconducting device thus formed can function as a super-FET.Type: GrantFiled: February 10, 1994Date of Patent: August 29, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
-
Patent number: 5442196Abstract: A pair of superconducting electrodes are so formed as to interpose a semiconductor therebetween, and a control electrode is formed on the semiconductor through an insulator film so as to control the superconductive weak coupling state in the semiconductor between the superconducting electrodes. The distance between the superconducting electrodes is determined by the thickness of the superconductor interposed between the two electrodes, whereby the interelectrode distance is settled with a high precision to improve the uniformity of the device characteristic.And in an arrangement where two superconducting electrodes are formed on a semiconductor layer and the superconductive weak coupling state between such two electrodes is controlled by a third electrode, the gain is increadable by furnishing a varied impurity distribution in the semiconductor layer.Type: GrantFiled: February 24, 1994Date of Patent: August 15, 1995Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Mutsuko Miyake, Ushio Kawabe, Yutaka Harada, Masaaki Aoki, Mikio Hirano
-
Patent number: 5430013Abstract: A superconducting thin film formed on a substrate, comprising an a-axis orientated oxide superconductor layer, a c-axis orientated oxide superconductor layer and an oxide semiconductor layer inserted between the a-axis orientated oxide superconductor layer and the c-axis orientated oxide superconductor layer, in contact with them in which superconducting current can flow between the a-axis orientated oxide superconductor layer and the c-axis orientated oxide superconductor layer through the oxide semiconductor layer by a long-range proximity effect.Type: GrantFiled: October 24, 1994Date of Patent: July 4, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiroshi Inada, Michitomo Iiyama
-
Patent number: 5413982Abstract: A superconducting device comprising a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, an extremely thin superconducting channel formed of a c-axis oriented oxide superconductor thin film on the non-superconducting oxide layer, a superconducting source region and a superconducting drain region formed of an a-axis oriented oxide superconductor thin film at the both sides of the superconducting channel separated from each other, which are electrically connected each other by the superconducting channel, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region, and a gate electrode of a material which includes silicon through a gate insulator on the superconducting channel for controlling the superconducting current flowing through the superconducting channel, in which the gate electrode is embedded between the superconduType: GrantFiled: December 14, 1992Date of Patent: May 9, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiroshi Inada, So Tanaka, Michitomo Iiyama
-
Patent number: 5401714Abstract: A field-effect structure formed on a substrate and comprising a channel with source and drain as well as a gate that is separated from the channel by an insulating layer. The channel is made of a high T.sub.c metal-oxide superconductor, e.g., YBaCuO, having a carrier density of about 10.sup.21 /cm.sup.3 and a correlation length of about 0.2 nm. The channel thickness is preferrable in the order of 1 nm. The superconductor is preferably a single crystalline and oriented such that the superconducting behavior is strongest in the plane parallel to the substrate. With a signal of a few volts applied to the gate, the entire channel cross-section is depleted of charge carriers whereby the channel resistance can be switched between a "zero resistance" (undepleted, superconducting) state and "very high resistance" (depleted state).Type: GrantFiled: May 4, 1994Date of Patent: March 28, 1995Assignee: International Business Machines CorporationInventors: Preveen Chaudhari, Carl A. Mueller, Hans P. Wolf
-
Patent number: 5357120Abstract: A compound semiconductor device is provided which includes a thyristor region constructed by four continuous layers of p-n-p-n and an MOSFET region which is formed in the intermediate n layer of the thyristor region so as to be away from the intermediate p layer. The MOSFET is constructed by a p well layer, a source layer, and a drain layer. One main electrode of the device is in ohmic contact with the outside p layer of the thyristor region. While the other main electrode is in ohmic contact with the source layer and well layer of the MOSFET region. An arrangement is provided for electrically connecting the outside n layer of the thyristor region and the drain layer of the MOSFET region. Also, a first insulating gate is formed on the well layer between the source layer and the drain layer of the MOSFET region and a second insulating gate is formed on the intermediate p layer of the thyristor region; with the first and second insulating gates being electrically connected.Type: GrantFiled: July 14, 1992Date of Patent: October 18, 1994Assignee: Hitachi Ltd.Inventor: Mutsuhiro Mori
-
Patent number: 5357125Abstract: A semiconductor device including a normally-on SI thyristor, and a MOSFET connected in cascade with the SI thyristor. The gate of the SI thyristor is connected to the source of the MOSFET. This arrangement makes it possible to turn the device on and off by controlling only the voltage gate of the MOSFET, obviating a current to maintain the on state of the device. The device needs little driving energy and has a low on state voltage and a high switching speed. It can readily be integrated into one chip.Type: GrantFiled: September 11, 1992Date of Patent: October 18, 1994Assignee: Fuji Electric Co., Ltd.Inventor: Naoki Kumagi
-
Patent number: 5352905Abstract: A thyristor type surge suppressor includes a P-type semiconductor substrate, an N-type first semiconductor layer provided in one surface of the semiconductor substrate, an N-type second semiconductor layer provided in the other surface of the semiconductor substrate, a P-type third semiconductor layer formed in the N-type first semiconductor layer so as to provide a plurality of first exposed regions of the N-type first semiconductor layer, a P-type fourth first semiconductor layer formed in the N-type second semiconductor layer so as to provide a plurality of second exposed regions of the N-type second semiconductor layer, a first electrode provided over the P-type third semiconductor layer and the of N-type first exposed regions, and a second electrode provided over the P-type fourth semiconductor layer and the N-type second exposed regions.Type: GrantFiled: September 17, 1992Date of Patent: October 4, 1994Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventor: Koichi Ohta
-
Patent number: 5345099Abstract: In a CCD device, on a semiconductor substrate, and in the insulation films, plural first semiconductor regions and plural second semiconductor regions are formed buried in the insulation films, intermediating a tunneling insulation film therebetween in a manner to spatially isolate them from each other.Type: GrantFiled: May 4, 1993Date of Patent: September 6, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takahiro Yamada
-
Patent number: 5323021Abstract: A bipolar transistor and a diode are incorporated in a semiconductor integrated circuit device, and an emitter electrode is constituted by lower and upper doped polysilicon films sandwiching an oxygen-leakage film which tunnels minority carriers of the base therethrough at higher probability than the majority carriers so as to enhance the emitter injection efficiency, thereby allowing a designer to increase the base width and the distance from the p-n junction between the anode and the cathode for improving the breakdown voltage of the diode without sacrifice of the current amplification factor.Type: GrantFiled: May 17, 1993Date of Patent: June 21, 1994Assignee: NEC CorporationInventor: Hidekazu Hasegawa
-
Patent number: 5318952Abstract: A superconducting transistor is provided with a base layer made of a normal conductor metal, an emitter layer made of a superconductor for injecting hot electrons to the base layer, a collector layer made of a superconductor for trapping electrons from the base layer, a first tunnel barrier layer made of an insulator and provided between the base layer and the emitter layer, and a second tunnel barrier layer made of an insulator and provided between the base layer and the collector layer.Type: GrantFiled: August 27, 1993Date of Patent: June 7, 1994Assignee: Fujitsu LimitedInventor: Tsunehiro Hato
-
Patent number: 5317168Abstract: A superconducting field effect transistor which is very small in size and high in dimensional accuracy, has a first layer of material forming a control electrode and a second layer of another material is disposed on said first layer. A width of said first layer in a direction toward a superconducting source electrode and a superconducting drain electrode is narrower than a width of the second layer in the same direction. Polycrystalline silicon may be used as the control electrode while the second layer can be made of silicon nitride. Furthermore, a side surface of the control electrode may be coated with an insulator film. Accordingly, the above transistor has a fine structure gate electrode part that can be fabricated easily and accurately.Type: GrantFiled: November 19, 1992Date of Patent: May 31, 1994Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Ushio Kawabe, Fumio Murai, Tokuo Kure, Mutsuko Hatano, Haruhiro Hasegawa
-
Patent number: 5311037Abstract: Superconducting electrodes are formed on a semiconductor which serves as a channel. A control electrode is disposed through an insulator film or a p-n junction on the side of the semiconductor which is opposite to the semiconductor side on which the superconducting electrode is formed. A superconducting current flows between the superconducting electrode across the semiconductor is controlled by an electric signal which is applied to the control electrode, thereby enhancing the current gain.Type: GrantFiled: August 6, 1992Date of Patent: May 10, 1994Assignee: Hitachi, Ltd.Inventors: Yutaka Harada, Shinichiro Yano, Mutsuko Miyake, Ushio Kawabe, Toshikazu Nishino
-
Patent number: 5306927Abstract: A high current amplifier, three terminal device, comprising a Josephson tunnel junction and a Schottky diode is configured so that the Josephson junction and Schottky diode share a common base electrode which is made very thin. Electrons which cross the Schottky barrier are supplied to the Josephson junction to obtain the amplified output current.Type: GrantFiled: August 15, 1991Date of Patent: April 26, 1994Assignee: The United States of America as represented by the Secretary of the NavyInventors: Bruce J. Dalrymple, Arnold H. Silver, Randy W. Simon
-
Patent number: 5272358Abstract: In a superconducting device wherein the value of a superconducting current to flow between two superconducting electrodes provided in contact with a semiconductor is controlled by a control electrode provided between the superconducting electrodes, high impurity concentration regions are formed within the semiconductor so as to lie in contact with the superconducting electrodes and to extend to under ends of the control electrode.Type: GrantFiled: November 25, 1991Date of Patent: December 21, 1993Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Ushio Kawabe, Mutsuko Hatano
-
Patent number: 5258625Abstract: An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.Type: GrantFiled: October 15, 1992Date of Patent: November 2, 1993Assignee: Hitachi, Ltd.Inventors: Shiroo Kamohara, Toru Toyabe, Kozo Katayama, Shuichi Yamamoto, Sigeo Ihara
-
Patent number: 5239187Abstract: Disclosed is a transistor or diode type Josephson effect device, at least two electrodes of which are made of superconductive material. If the Josephson effect is to be exerted in a semiconductor layer between the access electrodes, the distance between them should be smaller than the length of coherence, namely 10 to 1000 angstroms. According to the disclosure, the control channel between access electrodes is replaced by two channels perpendicular to the semiconductor layer, located between the two access electrodes and a layer of superconductive material placed between the substrate and the semiconductor layer. The disclosure can be applied to transistors, phototransistors and diodes with high switching speed.Type: GrantFiled: March 2, 1992Date of Patent: August 24, 1993Assignee: Thomson-CSFInventors: Alain Schuhl, Stephane Tyc, Alain Friederich
-
Patent number: 5232905Abstract: A superconducting device has a structure of superconductor - normal-conductor (semiconductor) - superconductor. The superconductors constituting the superconducting device are made of a super-conducting oxide material of K.sub.2 NiF.sub.4 type crystalline structure or perovskite type crystalline structure which contains at least one element selected from the group consisting of Ba, Sr, Ca, Mg and Ra; at least one element selected from the group consisting of La, Y, Ce, Sc, Sm, Eu, Er, Gd, Ho, Yb, Nd, Pr, Lu and Tb; Cu; and O.Type: GrantFiled: August 7, 1991Date of Patent: August 3, 1993Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Haruhiro Hasegawa, Ushio Kawabe
-
Patent number: 5231295Abstract: A field-effect transistor comprises, on a substrate, a layer of semiconductor material incorporating natural or artificial inclusions of superconducting material. The source, drain and gate electrodes are made on this layer. Applications: field-effect transistors with low gate control voltage. FIG. 3.Type: GrantFiled: August 16, 1991Date of Patent: July 27, 1993Assignee: Thomson-CSFInventors: Stephane Tyc, Alain Schuhl
-
Patent number: 5160983Abstract: Superconducting electrodes are formed on a semiconductor which serves as a channel. A control electrode is disposed through an insulator film or a p-n junction on the side of the semiconductor which is opposite to the semiconductor side on which the superconducting electrode is formed. A superconducting current which flows between the superconducting electrodes across the semiconductor is controlled by an electric signal which is applied to the control electrode, thereby enhancing the current gain.Type: GrantFiled: November 21, 1989Date of Patent: November 3, 1992Assignee: Hitachi, Ltd.Inventors: Yutaka Harada, Shinichiro Yano, Mutsuko Miyake, Ushio Kawabe, Toshikazu Nishino