Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region, and a method of formation. In some embodiments, the integrated circuit comprises a first gate boundary dielectric layer disposed over a substrate in the low voltage region. A second gate boundary dielectric layer is disposed over the substrate in the high voltage region having a thickness greater than that of the first boundary dielectric layer. The first boundary dielectric layer meets the second boundary dielectric layer at the boundary region. A first polysilicon component is disposed within the boundary region over the first boundary dielectric layer and the second gate boundary layer. A second polysilicon component is disposed within the boundary region over the first polysilicon component. A hard mask component is disposed over the first polysilicon component and laterally neighbored to the second polysilicon component.

Abstract: Examples of a method of forming an integrated circuit device with an interfacial layer disposed between a channel region and a gate dielectric are provided herein. In some examples, the method includes receiving a workpiece having a substrate and a fin having a channel region disposed on the substrate. An interfacial layer is formed on the channel region of the fin, and a gate dielectric layer is formed on the interfacial layer. A first capping layer is formed on the gate dielectric layer, and a second capping layer is formed on the first capping layer. An annealing process is performed on the workpiece configured to cause a first material to diffuse from the first capping layer into the gate dielectric layer. The forming of the first and second capping layers and the annealing process may be performed in the same chamber of a fabrication tool.

Abstract: A new composition of matter, and more specifically a new compound, includes two or more highly resistive materials integrated into the chemistry of the grain boundary of an internal barrier layer capacitor material. This new compound includes a high permittivity and high resistivity dielectric compound. This new compound has high permittivity, high resistivity, and low leakage current. In certain examples the new compound can be used to create a dielectric energy storage device that is a battery with very high energy density, high operating voltage per cell, and an extended battery life cycle.

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate that includes a surface exposing a first film containing silicon, oxygen, carbon and nitrogen and having an oxygen atom concentration higher than a silicon atom concentration, which is higher than a carbon atom concentration, which is equal to or higher than a nitrogen atom concentration; and changing a composition of a surface of the first film so that the nitrogen atom concentration becomes higher than the carbon atom concentration on the surface of the first film, by supplying a plasma-excited nitrogen-containing gas to the surface of the first film.

Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

Abstract: A manufacturing method of a semiconductor device includes the following steps. At least one mesa structure is provided. The mesa structure includes a III-V compound semiconductor layer. A passivation layer is formed on the mesa structure. A gate dielectric layer is formed on the passivation layer, and a gate electrode is formed on the gate dielectric layer. An etching process is performed to the gate dielectric layer for thinning the gate dielectric layer before the step of forming the gate electrode. The thickness of the gate dielectric layer may be modified by the etching process, and the electrical performance of the semiconductor device may be enhanced accordingly.

Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Abstract: A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.

Abstract: A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.

Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a ?-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistors comprising germanium (Ge) in the channel, and to methods of manufacturing thereof. In one aspect, a field-effect transistor (FET) comprises an active region comprising germanium (Ge) and a gate stack formed on the active region. The gate stack comprises a Si-comprising passivation layer formed on the active region, an interfacial dielectric layer comprising SiOx (x>0) formed on the passivation layer, a dielectric capping layer comprising an interface dipole-forming material formed on the interfacial dielectric layer, a high-k dielectric layer formed on the dielectric capping layer and a gate electrode layer formed on the high-k dielectric layer.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.

Abstract: A MOSCAP phase adjuster includes two conductive regions with a thin insulating region therebetween, where charge is accumulated or depleted. In conventional MOSCAP modulators, the conductive and insulating regions are superposed layers, extending horizontally parallel to the substrate, which limits waveguide design and mode confinement, resulting in reduced phase shift performance. An improved MOSCAP phase adjuster and method of fabricating a MOSCAP phase adjuster includes depositing the material for the second conductive region beside and over top of the first conductive region after oxidation, and selectively etching the material to form the second conductive region.

Abstract: Fin-based well straps are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin structure doped with a first dopant concentration of the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin structure doped with a second dopant concentration of the first type dopant and second source/drain features of the first type dopant. The second dopant concentration is greater than (for example, at least three times greater than) the first dopant concentration.

Abstract: Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; an oxide semiconductor layer that is used as a channel layer; and a gate insulator film that is arranged between the gate electrode and the channel layer. The oxide semiconductor layer is configured of at least one metal element that is selected from the group consisting of In, Ga, Zn and Sn (excluding the cases where the oxide semiconductor layer is constituted of metal elements Sn, and at least one of In and Zn). The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.

Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.

Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.

Abstract: A semiconductor device includes active regions on a semiconductor substrate, gate structures on separate, respective active regions, and source/drain regions in the semiconductor substrate on opposite sides of separate, respective gate structures. Each separate gate structure includes a sequential stack of a high dielectric layer, a first work function metal layer, a second work function metal layer having a lower work function than the first work function metal layer, and a gate metal layer. First work function metal layers of the gate structures have different thicknesses, such that the gate structures include a largest gate structure where the first work function metal layer of the largest gate structure has a largest thickness of the first work function metal layers. The largest gate structure includes a capping layer on the high dielectric layer of the largest gate structure, where the capping layer includes one or more impurity elements.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.

Abstract: A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first active area of the fin having a first active area top surface coplanar with a first shallow trench isolation (STI) top surface of a first STI portion of STI, and a second active area of the fin having a second active area top surface coplanar with a second STI top surface of a second STI portion of the STI. The method herein negates a need to recess at least one of the fin, the first STI portion or the second STI portion during device formation. Negating a need to recess at least one of the fin, the first STI portion or the second STI portion enhances the semiconductor device formation and is more efficient than a semiconductor device formation that requires the recessing of at least one of a fin, a first STI portion or a second STI portion.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.

Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric layer having a first thickness on the semiconductor substrate, a first opening having a first width in the first dielectric layer, a second dielectric layer having a second thickness disposed in a middle region of the first opening, and a third dielectric layer having a first portion and a second portion disposed on opposite sides of second dielectric layer. The first portion and the second portion have a second width smaller than the first width, and the third dielectric layer has a third thickness smaller than the first thickness and the second thickness.

Abstract: A non-volatile storage element including a control gate, a tunneling layer, a charge storage region, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.

Abstract: A memory cell is provided that includes a control gate, a tunneling layer, a charge storage region, a blocking layer including a ferroelectric material, a semiconductor channel, and a source region and a drain region each disposed adjacent the semiconductor channel. The tunneling layer is disposed between the control gate and the charge storage region, the charge storage region is disposed between the tunneling layer and the blocking layer, and the blocking layer is disposed above the semiconductor channel.

Abstract: The present invention relates to polymers comprising a repeating unit of the formula I, or III and their use as organic semiconductor in organic devices, especially an organic field effect transistor (OFET), or a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers according to the invention are used in organic field effect transistors.

Abstract: The structures and methods disclosed herein include changing composition of a metal alloy layer in an epitaxial electrode material to achieve tunable work functions for the electrode. In one example, the tunable work function is achieved using a layered structure, in which a crystalline rare earth oxide (REO) layer is epitaxially over a substrate or semiconductor, and a metal layer is over the crystalline REO layer. A semiconductor layer is thus in turn epitaxially grown over the metal layer, with a metal alloy layer over the semiconductor layer such that the ratio of constituents in the metal alloy is used to tune the work function of the metal layer.

Abstract: A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining. The catalyst causes the grains to be bigger than would occur in the absence of the catalyst. A conductive layer (202) is formed over the metal oxide.

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: A semiconductor device includes a substrate and a gate structure on the substrate, in which the gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, the middle portion being a nitrogen rich portion, the top portion and the bottom portion being titanium rich portions, and the top portion, the middle portion, and the bottom portion are of same material composition.

Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene

Abstract: The present invention relates to polymers comprising a repeating unit of the formula I, or III and their use as organic semiconductor in organic devices, especially an organic field effect transistor (OFET), or a device containing a diode and/or an organic field effect transistor. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers according to the invention are used in organic field effect transistors.

Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a FET device, a vertical source/drain contact, a source/drain contact capping layer, and a vertical gate contact. The FET device includes a source/drain layer, and a gate structure. The vertical source/drain contact is formed in contact with a source/drain layer of the FET device. The source/drain contact capping layer is formed on an upper surface of the vertical source/drain contact. The vertical gate contact is formed in contact with a gate electrode layer of the gate structure. A portion of the vertical gate contact overlaps a portion of the vertical source/drain contact, wherein the source/drain contact capping layer electrically insulates the overlapping portions of the vertical gate and source/drain contacts.

Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.

Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.

Abstract: A semiconductor device includes a first trench and a second trench, a liner pattern along a portion of side surfaces and along bottom surfaces of the first and the second trenches, respectively, a work function metal in the first and the second trenches and on the liner pattern, respectively, a first barrier metal in the first trench and on the work function metal, and having a first thickness, a second barrier metal in the second trench and on the work function metal, and having a second thickness thicker than the first thickness, and a first fill metal on the first barrier metal.

Abstract: A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET).

Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.

Abstract: Systems and methods are disclosed for fabricating a semiconductor die that includes one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.

Abstract: A photoelectric conversion section contains a semiconductor element having a laminated structure which contains an electroconductor, a semiconductor, and an insulator provided between the electroconductor and the semiconductor, in which the insulator is a silicon oxide film containing nitrogen in a main portion located between the electroconductor and the semiconductor.

Abstract: A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a joint between a bottom surface and a sidewall surface of the first opening is a corner region. The method includes forming a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening, a barrier layer on the high-k dielectric layer, and an N-type work function layer containing aluminum ions on the barrier layer. The method further includes performing a back-flow annealing process such that the portion of N-type work function layer at the corner region is thickened and contains diffused aluminum ions. Finally, the method includes forming a metal layer on the N-type work function layer.

Abstract: A semiconductor device according to an embodiment includes a wide bandgap semiconductor layer, a gate electrode and a gate insulating film provided between the wide bandgap semiconductor layer and the gate electrode. The gate insulating film includes a first insulating film having a thickness of 7 nm or greater, a fixed charge film provided on the first insulating film, the fixed charge film containing fixed charge and a second insulating film provided on the fixed charge film, the second insulating film having a thickness of 7 nm or greater. The gate insulating film has a total thickness of 25 nm or greater.

Abstract: A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.

Abstract: While increasing a threshold voltage of a MOSFET configuring a CMOS, electric power saving of elements is achieved by suppressing excessive increase in the threshold voltage, and occurrence of performance variation among the elements is suppressed. A gate electrode of an NMOS is made of a P-type semiconductor film, a high-permittivity film is provided in a gate insulating film of the NMOS, and an impurity is prevented from being introduced into a channel region of the NMOS. Moreover, a high-permittivity film is provided also in a gate insulating film of a PMOS.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate structure, multiple fins having a germanium layer, a dummy gate structure including sequentially a hardmask, a dummy gate, a dummy gate insulating material on the germanium layer, and spacers on opposite sides of the dummy gate structure and on a portion of the germanium layer. The method also includes forming an interlayer dielectric layer on the substrate structure covering the dummy gate structure, planarizing the interlayer dielectric layer to expose a surface of the dummy gate, removing the dummy gate and the dummy gate insulating material to expose a surface of the germanium layer, performing a silane impregnation process on the exposed surface of the germanium layer to introduce silicon to the germanium layer, and performing an oxidation process on the germanium layer to form an oxide layer comprising silicon and germanium.

Abstract: A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.