Abstract: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions.

Abstract: A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.

Abstract: The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. In the present invention, a layer in a pillar-shaped section of a memory cell is etched laterally, decreasing its cross-section. In this way the cross section of the contact area between the heater layer and the phase change material is reduced. In preferred embodiments, the laterally etched layer is the heater layer or a sacrificial layer. In a preferred embodiment, such a cell can be used in a monolithic three dimensional memory array.

Abstract: A device having a substrate, a pair of ferromagnetic leads on a surface of the substrate, laterally separated by a gap, and one or more ferromagnetic microparticles comprising a conductive coating at least partially within the gap. The conductive coating forms at least part of an electrical connection between the leads. A molecular junction may connect the leads to the microparticle.

Abstract: A circuit sheet comprising a substrate and wells dispersed on the substrate operable to hold conductive polymers that form circuit devices.

Abstract: Processes for effecting thermal transfer of electroactive organic material are disclosed wherein unwanted portions of a layer of electroactive organic material supported by a donor element are removed or transferred from the layer by thermal transfer, particularly laser-induced thermal transfer, leaving a desired pattern of the electroactive organic material on the donor element. The electroactive organic material may be an organic material exhibiting electroluminescence, charge transport, charge injection, electrical conductivity, semiconductivity and/or exciton blocking. The layer of electroactive organic material may comprise more than one layer of different types of electroactive organic material. The exposure pattern is a negative image of the desired pattern. The electroactive organic material of the desired pattern is not, therefore, exposed to the heat which can cause decomposition.

Abstract: A new compound derivative that can be used to form a unit molecular film as a rectifier in a molecular electronic device, a new rectifying compound (4,5,9,10-tetrahydro-pyren-2-yl)-carbamic acid 4-(2-methylsulfanyl-alkyl)-3,5-dinitro-benzyl ester and its derivative (4,5,9,10-Tetrahydro-pyren-2-yl)-carbamic acid 4-(2-methylsulfanyl-alkyl)-3,5-dinitro-benzyl ester, and methods of synthesizing the compounds are provided.

Abstract: A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of various geometries. The empty-spaced patterns are then connected through vias with surfaces of the monocrystalline substrate. The empty-spaced patterns and their respective vias are subsequently filled with conductive materials.

Abstract: An organic transistor is capable of emitting light at high luminescence efficiency, operating at high speed, handling large electric power, and can be manufactured at low cost. The organic transistor includes an organic semiconductor layer between a source electrode and a drain electrode, and gate electrodes shaped like a comb or a mesh, which are provided at intervals approximately in the central part of the organic semiconductor layer approximately parallel to the source electrode and the drain electrode. The organic semiconductor layer consists of an electric field luminescent organic semiconductor material such as compounds of naphthalene, anthracene, tetracene, pentacene, hexacene, a phthalocyanine system compound, an azo system compound, a perylene system compound, a triphenylmethane compound, a stilbene compound, poly N-vinyl carbazole, and poly vinyl pyrene.

Abstract: A packaging fabrication for an organic electroluminescence panel is disclosed. The panel comprises a printed circuit board, one or a plurality of OEL panels and a plurality of bumps, wherein the OEL is provided with poly solder interconnections in area array. The printed circuit board is provided with a plurality of solder pads arranged with bumps. One or a plurality of OEL is arranged on the printed circuit board and the poly solder interconnections and bumps are used to electrically connect the OEL with the printed circuit board. Further, the excellent heat dissipation property of the low re-flow temperature of the poly solder interconnections and the ceramic printed circuit board provides packaging fabrication for low temperature low stress OEL.

Abstract: High quality epitaxial layers of piezoelectric monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the piezoelectric monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying piezoelectric monocrystalline material layer.

Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same, are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Abstract: The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface).

Abstract: The invention relate to a damascene chalcogenide memory cell structure. The damascene chalcogenide memory cell structure is fabricated under conditions that simplify previous process flows. The damascene chalcogenide memory cell structure also prevents volatilization of the chalcogenide memory material.

Abstract: Variations in the size of a linear pattern resulting from difference in mask pattern layout are prevented by setting the perimeter of the linear pattern per unit area in a specified range irrespective of the type of a semiconductor integrated circuit device or by adjusting a process condition in accordance with type-to-type difference in the perimeter of the linear pattern per unit area.

Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Abstract: An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and the phase change element, wherein a portion of the dielectric material comprises a thermal conductivity less than silicon dioxide. A method including introducing over a contact formed on a substrate, a dielectric material, a portion of which comprises a thermal conductivity less than silicon dioxide, introducing a heater element through the dielectric material to the contact, and introducing a phase change material over the dielectric material and the heater element.

Abstract: Brass articles having leachable lead are contacted with an aqueous caustic solution that contains a chelating agent. A brass article can optionally be post-treated by contacting it with an aqueous solution containing anazole.

Abstract: Molecular scale electronic devices are disclosed. Such devices include at least two conductive contacts, and a conductive path bridging the contacts. The conductive path is able to be written into a perturbed state by a voltage pulse, which can be of high or low conductivity, relative to an initial state. The conductive path comprises organic molecules including at least one electron-withdrawing group. Room temperature negative differential resistance is exhibited by the devices.

Abstract: An apparatus including a contact point on a substrate; a first dielectric layer comprising a material having a dielectric constant less than five formed on the contact point, and a different second dielectric layer formed on the substrate and separated from the contact point by the first dielectric layer. Collectively, the first and second dielectric layers comprise a composite dielectric layer having a composite dielectric constant value. The contribution of the first dielectric layer to the composite dielectric value is up to 20 percent. Also, a method including depositing a composite dielectric layer over a contact point on a substrate, the composite dielectric layer comprising a first material having a dielectric constant less than 5 and a second different second material, and forming a conductive interconnection through the composite dielectric layer to the contact point.

Abstract: An apparatus including a contact on a substrate, a dielectric material overlying the contact, a phase change element overlying the dielectric material on a substrate, and a heater element disposed in the dielectric material and coupled to the contact and the phase change element, wherein a portion of the dielectric material comprises a thermal conductivity less than silicon dioxide. A method including introducing over a contact formed on a substrate, a dielectric material, a portion of which comprises a thermal conductivity less than silicon dioxide, introducing a heater element through the dielectric material to the contact, and introducing a phase change material over the dielectric material and the heater element.

Abstract: An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.

Abstract: A method of fabricating a back surface point contact silicon solar cell having p-doped regions and n-doped regions on the same side by forming a passivating layer on a surface of the cell having opened windows at the p-doped regions and the n-doped regions, by depositing and patterning a first metal layer on the passivating layer in such a way that the first metal layer comes into contact with the p-doped regions and the n-doped regions, by depositing an insulator layer of polyimide on the first metal layer, by etching and patterning the insulator layer of polyimide in such a way that the insulator layer has opened windows at, at least one of the p-doped regions and the n-doped regions, by curing the insulator layer of polyimide by heating at temperature for a period, by additionally curing the insulator layer of polyimide by heating at a second temperature, which is higher than the first temperature, and by depositing a second metal layer made of metal stack on the insulator layer of polyimide in such a way

Abstract: A conductive composition of titanium boronitride (TiBxNy) is disclosed for use as a conductive material. The titanium boronitride is used as conductive material in the testing and fabrication of integrated circuits. For example, the titanium boronitride is used to construct contact pads such as inline pads, backend pads, sensors or probes. Advantages of embodiments of the titanium boronitride include reduced scratching, increased hardness, finer granularity, thermal stability, good adhesion, and low bulk resistivity. Exemplary methods of creating the titanium boronitride include a sputtering process and a plasma anneal process.

Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Abstract: A method of fabricating a back surface point contact silicon solar cell having p-doped regions and n-doped regions on the same side by forming a passivating layer on a surface of the cell having opened windows at the p-doped regions and the n-doped regions, by depositing and patterning a first metal layer on the passivating layer in such a way that the first metal layer comes into contact with the p-doped regions and the n-doped regions, by depositing a first insulator layer of inorganic material on the first metal layer, by etching and patterning the first insulator layer in such a way that the insulator layer has opened windows at, at least one of the p-doped regions and the n-doped regions, by depositing a second insulator layer of organic material on the first insulator layer, by etching and patterning the second insulator layer in such a way that the insulator layer has opened windows at the one of the p-doped regions and the n-doped regions, by curing the second insulator layer by heating at a predeterm

Abstract: An electrode structure for use in a chalcogenide memory is disclosed. The electrode has a substantially frusto-conical shape, and is preferably formed by undercut etching a polysilicon layer beneath an oxide pattern. With this structure, improved current densities through the chalcogenide material can be achieved.

Abstract: A method for manufacturing a memory device having a plurality of memory cells. Each memory cell has a non-volatile resistive memory element with a small active area. A plurality of memory cells are formed at selected locations of at least a portion of a semiconductor wafer. To form the memory cells, a lower electrode layer and a memory material layer are deposited over at least a portion of the wafer. Patterns are formed over desired contact locations of the memory material layer and etching is used to remove portions of the memory material layer. The etching step undercuts the patterns and forms memory elements having a protruding contact portion with an apex contact area. The pattern is removed, and an upper electrode is formed and electrically coupled to the contact area. Corresponding access devices and word/bit line conductor grids are provided and coupled to the memory cells.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate.

Abstract: A method for manufacturing a memory device having a plurality of memory cells. Each memory cell has a non-volatile resistive memory element with a small active area. A plurality of memory cells are formed at selected locations of at least a portion of a semiconductor wafer. To form the memory cells, a lower electrode layer and a memory material layer are deposited over at least a portion of the wafer. Patterns are formed over desired contact locations of the memory material layer and etching is used to remove portions of the memory material layer. The etching step undercuts the patterns and forms memory elements having a protruding contact portion with an apex contact area. The pattern is removed, and an upper electrode is formed and electrically coupled to the contact area. Corresponding access devices and word/bit line conductor grids are provided and coupled to the memory cells.

Abstract: A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite second conductivity type. A buried dielectric region is located in the semiconductor body beneath the upper semiconductor surface and extends into the first and second body regions. A first drain region of the second conductivity type is located in the semiconductor body and adjoins the first body region, the dielectric region and the upper semiconductor surface. A second drain region of the first conductivity type is located in the semiconductor body and adjoins the second body region, the dielectric region and the upper semiconductor surface. The two drain regions are adjacent to one another.

Abstract: An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

Abstract: Dummy transistors (each composed of a dummy gate electrode and n.sup.+ -diffused layers) are disposed adjacent to a transistor for characteristic checking which is composed of a gate electrode, n.sup.+ -diffused layers and aluminum interconnection layers. They are arranged in the same density as that of regular transistors in a product. This decreases a difference in size between the characteristic checking transistor and that in the regular transistors in the product so that the former can be truly representative of the latter.

Abstract: A semiconductor vacuum device including a semiconductor substrate 3, an insulator film 2 formed on the substrate 3, and a single crystal semiconductor film 1 formed on the insulator film 2. The single crystal semiconductor film 1 has a first and a second tapered edge opposite to one another but spaced apart over a gap formed in the insulator film 2. The first tapered edge acts 6 as a cathode and the second tapered edge acts as a gate 7, the substrate 1 acting as an anode into which said electrons emitted from the cathode above.

Abstract: A semiconductor device comprises a semiconductor substrate having first and second major surfaces, semiconductor elements formed on the first surface of the semiconductor substrate, and a blocking layer formed within the substrate at a given distance from the second major surface for blocking the passage of heavy metals through the semiconductor substrate.

Abstract: The present invention provides a large area, high pixel density solid state radiation detector with a real-time and a non-destructive read-out. The solid state detector comprises a plurality of field effect transistors deposited onto a substrate to form an array. A planarization layer is deposited over the array of transistors. An energy sensitive layer is deposited onto the planarization layer. Means is provided for electrically connecting the energy sensitive layer with each transistor of the array. A top electrode layer is deposited onto the energy sensitive layer. The solid state detector also comprises circuitry means for providing electronic read-out from each FET of the array.