Elongated Alloyed Region (e.g., Thermal Gradient Zone Melting, Tgzm) Patents (Class 257/45)
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Patent number: 9997572Abstract: The reflecting layer is formed on a white pixel PW and chromatic color pixels PR, PG, and PB. The semitransparent reflecting layer is formed on the white pixel PW and the chromatic color pixels PR, PG, and PB. The semitransparent reflecting layer and the intermediate layer in the white pixel PW constitute the light scattering structure. According to this display device, it is possible to obtain an advantage of a micro-cavity structure and an advantage of the white pixel while suppressing an increase in manufacturing cost.Type: GrantFiled: January 26, 2017Date of Patent: June 12, 2018Assignee: Japan Display Inc.Inventor: Takahiro Ushikubo
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Patent number: 9343442Abstract: A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.Type: GrantFiled: September 20, 2012Date of Patent: May 17, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hua Chen, Chen-Shien Chen
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Patent number: 8794501Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.Type: GrantFiled: February 13, 2012Date of Patent: August 5, 2014Assignee: LuxVue Technology CorporationInventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
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Patent number: 8692206Abstract: Systems, devices, and methods are described including implantable radiation sensing devices having exposure determination devices that determines cumulative exposure information based on the at least one in vivo measurand.Type: GrantFiled: September 8, 2011Date of Patent: April 8, 2014Inventors: Roderick A. Hyde, Muriel Y. Ishikawa, Eric C. Leuthardt, Michael A. Smith, Elizabeth A. Sweeney, Lowell L. Wood, Jr.
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Patent number: 8679880Abstract: An electron transporting surfactant is added to a raw material solution such that the electron transporting surfactant is coordinated on the surfaces of quantum dots, and after the dispersion solvent is evaporated by vacuum drying, the immersion in a solvent containing a hole transporting surfactant prepares a quantum dot dispersed solution with a portion of the electron transporting surfactant replaced with the hole transporting surfactant. The quantum dot dispersed solution is applied onto a substrate to prepare a hole transport layer and a quantum dot layer at the same time, and thereby to achieve a thin film which has a two-layer structure.Type: GrantFiled: June 15, 2012Date of Patent: March 25, 2014Assignee: Murata Manufaaturing Co., Ltd.Inventor: Koji Murayama
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Patent number: 8664655Abstract: An organic light emitting display apparatus has a hybrid structure in which resonance red, green and blue pixels and a non-resonance white pixel are combined. An optical path control layer and a white color filter which selectively absorbs light having a specific wavelength are included in the white pixel. Thus, the organic light emitting display apparatus has a large viewing angle, low power consumption, and long lifetime.Type: GrantFiled: February 8, 2011Date of Patent: March 4, 2014Assignee: Samsung Display Co., Ltd.Inventors: Sung-Hun Lee, Gun-Shik Kim
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Patent number: 8637873Abstract: According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall.Type: GrantFiled: June 20, 2011Date of Patent: January 28, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Kazutaka Takagi
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Patent number: 8587113Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, includes multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated has an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.Type: GrantFiled: June 7, 2013Date of Patent: November 19, 2013Assignee: Lam Research CorporationInventors: Keith William Gaff, Keith Comendant, Anthony Ricci
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Patent number: 8581367Abstract: A semiconductor device includes a substrate having first main face having rectangular shape, a first electrode provided at the center on first main face of substrate, first electrode is made of conducting material harder than substrate, and a second electrode provided along at least a part of the periphery on first main face so as to surround first electrode, second electrode is integrated with first electrode by the same conducting material as that of the first electrode, and second electrode has a thinner film thickness than that of the first electrode.Type: GrantFiled: September 2, 2008Date of Patent: November 12, 2013Assignee: Rohm Co., Ltd.Inventor: Tadahiro Okazaki
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Patent number: 8461674Abstract: A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated includes an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.Type: GrantFiled: September 21, 2011Date of Patent: June 11, 2013Assignee: Lam Research CorporationInventors: Keith William Gaff, Keith Comendant, Anthony Ricci
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Patent number: 8278659Abstract: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed.Type: GrantFiled: September 25, 2009Date of Patent: October 2, 2012Assignee: The Trustees of Columbia University in the city of New YorkInventors: James S. Im, Robert S. Sposili, Mark A. Crowder
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Patent number: 7321157Abstract: A method of fabricating a CoSb3-based thermoelectric device is disclosed. The method includes providing a high-temperature electrode, providing a buffer layer on the high-temperature electrode, forming composite n-type and p-type layers, attaching the buffer layer to the composite n-type and p-type layers, providing a low-temperature electrode on the composite n-type and p-type layers and separating the composite n-type and p-type layers from each other to define n-type and p-type legs between the high-temperature electrode and the low-temperature electrode.Type: GrantFiled: April 1, 2005Date of Patent: January 22, 2008Assignees: GM Global Technology Operations, Inc., Dalian Institute of Chemical Physics, Chinese Academy of SciencesInventors: Lidong Chen, Junfeng Fan, Shengqiang Bai, Jihui Yang
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Patent number: 7034328Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.Type: GrantFiled: April 3, 2002Date of Patent: April 25, 2006Assignee: Cree, Inc.Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.
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Patent number: 6921925Abstract: In photonic integrated circuits (PICs) having at least one active semiconductor device, such as, a buried heterostructure semiconductor laser, LED, modulator, photodiode, heterojunction bipolar transistor, field effect transistor or other active device, a plurality of semiconductor layers are formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer.Type: GrantFiled: September 17, 2004Date of Patent: July 26, 2005Inventors: Fred A. Kish, Jr., Sheila K. Mathis, Charles H. Joyner, Richard P. Schneider
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Patent number: 6881984Abstract: A resonant-cavity light-emitting diode includes a semiconductor light-emitting layer sandwiched between an under and an upper semiconductor distributed Bragg reflector mirror layer, which are formed on the substrate, a light extracting section formed on the upper semiconductor distributed Bragg reflector mirror layer and having an opening to extract light from the semiconductor light-emitting layer, and a groove formed by removing portions of the semiconductor light-emitting layer, under and upper semiconductor distributed Bragg reflector mirror layers which lie in a peripheral portion of the opening of the light extraction section and reach the under semiconductor distributed Bragg reflector mirror layer, the inner wall of the groove being formed to reflect part of light emitted from the semiconductor light-emitting layer into the groove.Type: GrantFiled: September 12, 2003Date of Patent: April 19, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Keiji Takaoka
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Patent number: 6573531Abstract: System and methods for processing an amorphous silicon thin film sample into a single or polycrystalline silicon thin film are disclosed.Type: GrantFiled: September 3, 1999Date of Patent: June 3, 2003Assignee: The Trustees of Columbia University in the City of New YorkInventors: James S. Im, Robert S. Sposili, Mark A. Crowder
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Patent number: 6521473Abstract: The present invention relates to a method of fabricating a liquid crystal display panel that involves patterning a silicon film crystallized by sequential lateral solidification. The method comprises the steps of preparing a silicon film, crystallizing the silicon film by growing silicon grains on a slant with respect to a horizontal direction of the silicon film, and forming a driver and a pixel part using the crystallized silicon film wherein the driver and pixel part comprise devices having channels arranged in horizontal and perpendicular directions relative to the silicon film. The crystallized silicon film has uniform grain boundaries in the channels of the devices, thereby improving the products by providing uniform electrical characteristics of devices that comprise a driver and a pixel part of an LCD panel.Type: GrantFiled: October 27, 2000Date of Patent: February 18, 2003Assignee: LGPhilips LCD Co., Ltd.Inventor: Yun-Ho Jung
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Patent number: 6437363Abstract: A semiconductor photonic device includes a substrate having a cleavage plane perpendicular to a principal plane thereof; a ZnO film on the substrate; and a compound semiconductor layer expressed by InxGayAlzN (x+y+z=1, 0≦x≦1, 0≦y ≦1, 0≦z≦1).Type: GrantFiled: September 3, 1999Date of Patent: August 20, 2002Assignee: Murata Manufacturing Co. Ltd.Inventors: Michio Kadota, Takashi Fujii
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Patent number: 6172370Abstract: An X-ray imaging array is described together with a method for its manufacture. The array is defined by a set of PN junctions in a silicon wafer that extend all the way through between the two surfaces of the wafer. The PN junctions are formed using neutron transmutation doping that is applied to P-type silicon through a mask, resulting in an array of N-type regions (that act as pixels) in a sea of P-type material. Through suitable placement of the biassing electrodes, a space charge region is formed that is narrower at the top surface, where X-rays enter the device, and wider at the lower surface. This ensures that most of the secondary electrons, generated by the X-ray as it passes through the wafer, get collected at the lower surface where they are passed to a charge readout circuit.Type: GrantFiled: December 28, 1999Date of Patent: January 9, 2001Assignee: Industrial Technology Research InstituteInventors: Chungpin Liao, Jen-Chau Wu
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Patent number: 5434531Abstract: An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.Type: GrantFiled: April 29, 1994Date of Patent: July 18, 1995Assignee: Intel CorporationInventors: Michael J. Allen, Charles H. Lucas
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Patent number: 5285090Abstract: Electrical ohmic contacts are made to a matrix of silicon having conductive rods embedded therein without making contact to any of the rods. Those rods which extend to the surface in the selected area of the matrix to be contacted are etched to form holes. The holes are filled with insulating polycrystalline silicon. The region of the selected area is heavily doped, and an ohmic contact member is made thereto. The underlying rods are spaced from the ohmic contact member and the heavily-doped region by intervening polycrystalline silicon.Type: GrantFiled: February 6, 1992Date of Patent: February 8, 1994Assignee: GTE Laboratories IncorporatedInventors: Brian M. Ditchek, Marvin Tabasky
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Patent number: RE42007Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.Type: GrantFiled: April 24, 2008Date of Patent: December 28, 2010Assignee: Cree, Inc.Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.
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Patent number: RE45517Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.Type: GrantFiled: November 9, 2010Date of Patent: May 19, 2015Assignee: Cree, Inc.Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.