Abstract: An array substrate and a fabrication method thereof, an array substrate motherboard, and a display device are disclosed. The array substrate includes a display region and a bonding region outside the display region. The array substrate further includes: a bonding electrode, located in the bonding region and spaced apart from an outer edge of the bonding region; and an electrostatic barrier line, the electrostatic barrier line has one end electrically connected with the bonding electrode, and the other end extends to the outer edge of the bonding region, and resistivity of the electrostatic barrier line is greater than resistivity of the bonding electrode.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Abstract: A display device includes a substrate including a display area and a test area adjacent to the display area, a lower electrode disposed in the display area on the substrate, a common layer disposed on the lower electrode, an upper electrode disposed on the common layer; and a test element group. The test element group includes a plurality of electrode patterns disposed in a same layer as the lower electrode and in the test area on the substrate, a test common layer disposed in a same layer as the common layer and on the electrode patterns, where a plurality of openings is defined through the test common layer to expose a part of each of the electrode patterns, and an electrode layer disposed in a same layer as the upper electrode, on the test common layer, and in contact with the electrode patterns through the openings.

Abstract: An object is to provide a technique capable of suppressing the rise in the sense voltage during the Miller plateau. A semiconductor device includes a semiconductor substrate of first conductivity type, a first IGBT portion and a second IGBT portion selectively disposed on a first main surface of the semiconductor substrate, and an impurity region of second conductivity type selectively disposed on a second main surface of the semiconductor substrate. The second IGBT portion is used to detect the current passing through the first IGBT portion. An area ratio of the impurity region within a second range to an area of the second range is lower than an area ratio of the impurity region within a first range to an area of the first range, the second range corresponding to the second IGBT portion, the first range corresponding to the first IGBT portion.

Abstract: Present disclosure provides a semiconductor stress monitoring structure, including a substrate, first conductive segments over the substrate, second conductive segments and a sensing structure proximate to the substrate. The first conductive segments are arranged parallel to each other. The second conductive segments are arranged below the first conductive segments and parallel to each other. The first conductive segments and the second conductive segments extend in the same direction. The sensing structure is configured to respond to a stress caused by the first conductive segments and the second conductive segments and generate a monitoring signal.

Abstract: A display device includes a substrate, a display area disposed on the substrate and including a plurality of pixels and data lines, a peripheral area disposed outside the display area of the substrate, a pad portion disposed in the peripheral area, an encapsulation layer disposed in the peripheral area and the display area, and disposed on the plurality of pixels of the display area, a crack detection circuit disposed in the peripheral area, and a first crack detection line connected with the pad portion and the crack detection circuit. The first crack detection line is disposed on the encapsulation layer.

Abstract: A semiconductor device includes a semiconductor layer having a first surface in which a plurality of trenches each extending along a first direction are arranged along a second direction perpendicular to the first direction, a first electrode on a second surface of the semiconductor layer, a second electrode on the first surface of the semiconductor layer, and a control electrode inside at least one of the trenches. The plurality of trenches includes first, second, and third trenches. The first and second trenches are connected to each other via a first connector at an end in the first direction of each of the first and second trenches. The third trench extends beyond the end of each of the first and second trenches along the first direction.

Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a sensor module, a connector, and a stress buffer structure. The sensor module is disposed on the carrier. The connector is connected to the carrier. The stress buffer structure connects the connector to the sensor module.

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop passing through the left-bottom corner region, a second conduction loop passing through the right-bottom corner region, a third conduction loop passing through the left-bottom corner region and the left-upper corner region, a fourth conduction loop passing through the right-bottom corner region and the right-upper corner region, and a shielding loop to shield electrical interference between the first through fourth conduction loops.

Abstract: A display apparatus includes a first pad at one side of a substrate; a first semiconductor layer on the substrate; a first crack detection electrode interposed between the substrate and the first semiconductor layer, and including a first end portion at the one side and a second end portion at another side; a second crack detection electrode disposed on the first semiconductor layer, and including a first end portion located at the one side and a second end portion connected to the second end portion of the first crack detection electrode; and a first auxiliary electrode disposed on the second conductive layer, and including a first end portion connected to the second end portion of the first crack detection electrode and a second end portion electrically connected to the first pad.

Abstract: A semiconductor package includes a processor, a lower memory including a plurality of lower memory chips that are vertically stacked, an interposer mounted on the processor and the lower memory, and an upper memory mounted on the interposer, the upper memory including a plurality of upper memory chips that are vertically stacked. The interposer includes a first physical layer (PHY) transmitting and receiving a signal between the processor and the lower memory and transmitting and receiving a signal between the processor and the upper memory, and the processor includes a second PHY communicating with the first PHY and a first through silicon via (TSV) electrically connecting the first PHY to the second PHY.

Abstract: An integrated circuit (IC) is manufactured and is mounted in an IC package. A processor of a measurement system determines a reference value of a physical layer (PHY) parameter at a second test point on a test fixture based on one or more model values, specified by an Ethernet communication standard, corresponding to a first test point on the test fixture corresponding to a contact on the IC package and one or more measured test fixture parameters characterizing a channel connecting the first test point to the second test point on the test fixture. The processor then determines whether the PHY parameter at the first test point on the IC package complies with the Ethernet communication standard based on i) the reference value of the PHY parameter and ii) a measured value of the PHY parameter obtained from a measurement of the PHY parameter at the second test point.

Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device, as well as a method for forming the IC. In some embodiments, the IC comprises a memory cell structure including a pair of control gates respectively separated from a substrate by a pair of floating gates and a pair of select gate electrodes disposed on opposite sides of the pair of control gates. A memory test structure includes a pair of dummy control gates respectively separated from the substrate by a pair of dummy floating gates and a pair of dummy select gate electrodes disposed on opposite sides of the pair of dummy control gates. The memory test structure further includes a pair of conductive floating gate test contact vias respectively extending through the pair of dummy control gates and reaching on the dummy floating gates.

Abstract: In a transparent display panel, a GIP region acts as a transmissive region, thereby increasing or maximizing a transmissive area in the GIP region. To this end, a line for VSS voltage application is disposed in a display region. Thus, a non-transparent thick line for applying the VSS voltage is not disposed in an upper portion of a GIP circuit region. Thus, a transparent bezel in which the GIP region acts as the transmissive region is implemented. Further, a GIP input signal line region and a GIP output signal line region constitute different layers, thereby to maximize a spacing between GIP input signal lines, resulting in increasing or maximizing a transmissive area in the GIP circuit region.

Abstract: In a step, acceptor ions are implanted from a back surface of a semiconductor substrate. In a step, a wet process of immersing the semiconductor substrate in a chemical solution including hydrofluoric acid is performed, to introduce hydrogen atoms into the semiconductor substrate. In a step, proton radiation is provided to the back surface of the semiconductor substrate, to introduce hydrogen atoms into the semiconductor substrate and form radiation-induced defects. In a step, an annealing process is performed on the semiconductor substrate, to form hydrogen-related donors by reaction of the hydrogen atoms and the radiation-induced defects and reduce the radiation-induced defects.

Abstract: Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The method inluces forming a semiconductor chip, forming an electromagnetic shield that covers the semiconductor chip, and forming a molding that covers the electromagnetic shield. The electromagnetic shield is electrically connected to a conductor on a side of the semiconductor chip.

Abstract: In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.

Abstract: A display device includes a substrate including a display area in which a display element is arranged and a non-display area having a pad area outside the display area, a first thin-film transistor arranged in the display area of the substrate and including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a first voltage line which extends in a first direction on the first gate electrode, a data line apart from the first voltage line and which extends in the first direction, connection lines which connects the data line to a pad in the pad area in the display area, and a conductive layer arranged in a layer between the first voltage line and the data line.

Abstract: A method is provided. A bottom tier package structure is bonded to a support substrate through a first bonding structure, wherein the bottom tier package structure includes a first semiconductor die encapsulated by a first insulating encapsulation, and the first bonding structure includes stacked first dielectric layers and at least one stacked first conductive features penetrating through the stacked first dielectric layers. The support substrate is placed on a grounded stage such that the first semiconductor die is grounded through the at least one first stacked conductive features, the support substrate and the grounded stage. A second semiconductor die is bonded to the bottom tier package structure through a second bonding structure, wherein the second bonding structure includes stacked second dielectric layers and at least one stacked second conductive features penetrating through the stacked second dielectric layers. The second semiconductor die is encapsulated with a second insulating encapsulation.

Abstract: A testing probe system includes probes configured to contact shared probe pads of multi-channel die of a wafer; and a controller configured to generate testing patterns and receive signals from the multi-channel die of the wafer. The controller is configured to contact a probe of the probes with a shared probe pad of the multi-channel die, select a first channel of the multi-channel die to test, select at least one test mode for testing the first channel, stimulate at least the first channel during a single contact period, acquiring a first output of the first channel during the single contact period, select a second channel of the multi-channel die to test, select at least one test mode for testing the second channel, stimulate at least the second channel during the single contact period, and acquire a second output of the first channel during the single contact period.

Abstract: A first metal layer, an inorganic insulating film, and a second metal layer are provided. A first wiring line led to a peripheral edge of a cutout portion is provided in the first metal layer. A second wiring line led to the peripheral edge of the cutout portion is provided in the second metal layer. The first lead wiring line and the second lead wiring line overlap each other through intermediation of the inorganic insulating film.

Abstract: An AI-based rule generation system generates an ontology from user-provided information and further enables generating rules that govern processes via drag-and-drop operations by automatically generating code in the backend. The rule generation system after generating the ontology, provides access to the entities of the ontology via a drag-and-drop GUI which also includes operators required to generate the rules. The user can drag-and-drop the entity elements and the operator elements as needed onto a whitespace in addition to providing the requisite values in order to generate a rule flow. The rule flow is validated and published to an execution server for use by downstream processes. The rule generation system further includes custom functions in addition to enabling distributed knowledge base processes for generating the rules.

Abstract: A display device includes a substrate; and a driving pad disposed on the substrate, wherein the driving pad includes a first pad portion and a second pad portion alternately arranged along a direction, wherein each of the first pad portion and the second pad portion includes first data pads and signal pads, wherein the first data pads of the first and second pad portions include a first side and a second side different from the first side, wherein the signal pads of the first pad portion are disposed on the first side of the first data pads of the first pad portion, and the signal pads of the second pad portion are disposed on the second side of the first data pads of the second pad portion, and wherein the first data pads provide a data signal to pixels, and the signal pads provide a driving voltage to the pixels.

Abstract: A semiconductor device may include function circuits and a test line structure beside the function circuits. The test line structure includes standard cell circuit blocks including a first components and environment circuit regions between the standard cell circuit blocks. The environment circuit regions include second components. The first components are different from the second components in structure, arrangement or a combination thereof.

Abstract: Detecting voltage-based attacks on an integrated circuit (IC) is difficult in the presence of clock jitter. Propagating signals can exhibit a total delay that is due to a delay component resulting from a voltage-based attack and a delay characteristic resulting from clock fluctuation. Voltage-variation detection circuitry includes first and second voltage-dependent circuits and a voltage analysis circuit. The voltage-dependent circuits produce first and second signals that are indicative of a voltage level responsive to a clock signal and based on different first and second voltage sensitivities. The voltage analysis circuit generates a voltage alert signal based on the first and second signals. A combined signal neutralizes the delay characteristic in the first and second signals, but the delay component due to the voltage variation can be at least partially maintained. Thus, a voltage-based attack is detectable in the presence of clock fluctuation by using two voltage-dependent circuits.

Abstract: Provided is a method of producing an electronic device, including a step of preparing a structure which includes an electronic component having a circuit forming surface, and an adhesive laminated film which includes a base material layer, an unevenness-absorptive resin layer, and an adhesive resin layer in this order and in which the adhesive resin layer is attached to the circuit forming surface of the electronic component such that the circuit forming surface is protected; and a step of forming an electromagnetic wave-shielding layer on the electronic component in a state of being attached to the adhesive laminated film.

Abstract: Present disclosure provides a semiconductor stress monitoring structure, including a substrate, first conductive segments, second conductive segments, and a sensing structure. The first conductive segments are over the substrate and arranged parallel to each other. The second conductive segments are arranged below the first conductive segments and parallel to each other. The sensing structure is proximate to the substrate. The sensing structure is configured to respond to a stress caused by the first conductive segments and the second conductive segments and generate a monitoring signal.

Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.

Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by a first through electrode and a second through electrode. The first semiconductor chip may electrically connect the first through electrode to a third test resistor during a second test operation. The first semiconductor chip may detect a voltage level of the first internal node, which is determined by resistance values of the third test resistor and the first and second through electrodes, to test a short failure between the first and second through electrodes during the second test operation.

Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.

Abstract: A novel electric rectifier for use in a rectenna device is provided. The rectenna device can advantageously be used in a variety of applications. The electric rectifier comprises an integrated structure comprising: a diode structure comprising first and second electrodes located in first and second conductive layers respectively and an insulating layer between them, the diode structure being configured and operable for receiving an input signal and generating output signal indicative thereof, and a compensation structure electrically connected in parallel to said diode structure and being configured to compensate the parasitic capacitance of the diode structure when a frequency spectrum of the input signal is beyond the diode's cutoff frequency.

Abstract: A light emitting device package according to an embodiment may include a first package body including first and second openings passing through the upper surface and lower surface thereof; a second package body disposed on the first package body and including a third opening passing through the upper surface and lower surface thereof; a light emitting device disposed in the third opening; a first resin disposed between the upper surface of the first package body and the light emitting device; and a second resin disposed in the third opening.

Abstract: A transistor device includes field plate contacts that electrically connect overlying contact pads to field electrodes in underlying trenches, and mesa contacts that electrically connect the contact pads to semiconductor mesas confined by the trenches. Each field plate contact is divided into field plate contact segments that are separated from one another. Each mesa contact is divided into mesa contact segments that are separated from one another. In a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts. In a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts.

Abstract: A fin height monitoring structure including a substrate, isolation structures, a first word line, and a second word line is provided. The substrate includes a first region and a second region. The isolation structures are located in the substrate of the first region to define at least one active area. The substrate in the active area has a fin that is higher than the isolation structures. The first word line is located on the isolation structures of the first region and on the fin of the first region. The second word line is located on the substrate of the second region.

Abstract: A semiconductor device includes through-package debug features enabling debug of a BGA package while mounted to a printed circuit board or other host device. In one example, the through-package debug features are filled or plated vias extending from a surface of the semiconductor device, through a device housing, down to test pads on the substrate. In another example, the through-package debug features are open channels formed from a surface of the semiconductor device.

Abstract: A probe card in an automated test equipment (ATE) and methods for operating the same for testing electronic devices. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins. The probe card has a pad geometry that compensates for misalignment with corresponding probe pins due to manufacturing error or a mismatch of coefficient of thermal expansion, enabling reliable operation of the ATE over a wide range of test temperatures. The pad array may have a plurality of elongated pads, each of uniquely designed size, tilt angle, and/or center location, with the characteristics of each pad being dependent on a distance between each pad and a centroid of the pad array, such that a probe pin to pad location errors can be mitigated.

Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

Abstract: A substrate is orientated parallel to a plane and includes pads that are located at a bottom surface of the substrate and external to the electrical device. A first integrated circuit die is orientated parallel to the plane and disposed above the substrate in a vertical direction. The first integrated circuit die is electrically coupled to at least some of the pads of the substrate. A packaging material is disposed above the first integrated circuit die around at least a top surface and side surfaces of the first integrated circuit die. Test pads are orientated parallel to the plane and disposed above the first integrated circuit die in the vertical direction. The test pads are electrically coupled to the first integrated circuit die and encased within the packaging material.

Abstract: A semiconductor apparatus includes a semiconductor layer having first and second faces, a semiconductor element portion in which semiconductor elements are provided, and openings each penetrating the semiconductor layer from the second face side, an interconnection structure provided on the first face side, and an insulator portion provided to surround at least one of the openings within a virtual plane along the second face and extend to a depth between T/2 and T from the first face, where T is the thickness of the semiconductor layer. The semiconductor layer includes a semiconductor region of one conductivity type provided on the opposite side to the one opening to the insulator portion within the virtual plane, and a semiconductor region of another conductivity type provided in the semiconductor layer from the insulator portion face on the second face side to the second face in a direction perpendicular to the second face.

Abstract: The present invention provides a method, device, and system for testing devices under testing (DUTs). The method comprises: sending a scan activated signal and a synchronous clock signal via the second signal line, and sending a first preset signal via the serial signal line, wherein each bit of the first preset signal is transmitted to a corresponding scan chain unit in a sequence of serial connection of the plurality of scan chain units with according to the synchronous clock signal, the corresponding scan chain unit is one of the plurality of scan chain units connected serially and coupled to the plurality of DUTs via a third signal line; sending a scan deactivated signal via the second signal line, to deactivate the scan chain units from identifying and receiving the first preset signal; and sending a second preset signal via the second signal line, and sending a test signal via the first signal line.

Abstract: Provided is a package structure including a photonic die, an electronic die, a conductive layer, a circuit substrate, and an underfill. The electronic die is bonded on a front side of the photonic die. The conductive layer is disposed on a back side of the photonic die. The conductive layer includes a plurality of conductive pads and a dam structure between the conductive pads and a first sidewall of the photonic die. The circuit substrate is bonded on the back side of the photonic die through a plurality of connectors and the conductive pads. The underfill laterally encapsulates the connectors, the conductive pads, and the dam structure. The underfill at the first sidewall of the photonic die has a first height, the underfill at a second sidewall of the photonic die has a second height, and the first height is lower than the second height.

Abstract: A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube.

Abstract: A mother substrate and a display panel are disclosed. The mother substrate includes a plurality of display panels, a plurality of first test terminals and a plurality of first one-way conductive circuits. Each of the display panels has a display area, and includes a plurality of first signal lines extending from outside of the display area to the display area in parallel; the plurality of first signal lines of each of the display panels are respectively electrically connected to one of the plurality of first test terminals; the plurality of first one-way conductive circuits are respectively electrically connected to the plurality of first signal lines outside the display area and are configured to allow signals to be able to transmit only from the plurality of first test terminals to the plurality of first signal lines of each of the display panels.

Abstract: A circuit board has an electrical circuit and a connector that is attached to the circuit board. The connector has metal contacts. A housing of the connector has an embedded reference metal layer that is disposed under a single-ended metal contact or differential metal contacts. The reference metal layer sets the impedance of the single-ended metal contact or the differential metal contacts.

Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.

Abstract: An array substrate including a substrate, a plurality of fan-out traces and a plurality of bonding terminals. The substrate includes a display area and a non-display area surrounding the display area. The fan-out traces and the bonding terminals are disposed in the non-display area. The bonding terminals are spaced apart from each other. First ends of the fan-out traces are respectively electrically connected to the bonding terminals. Second ends of the fan-out traces are electrically connected to the display area. The fan-out traces include a plurality of first fan-out traces and a plurality of second fan-out traces. The first fan-out traces are formed by a first metal layer. The second fan-out traces are formed by a second metal layer. An insulating layer is provided between the first metal layer and the second metal layer. The first fan-out traces and the second fan-out traces are partially overlapped.

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

Abstract: A semiconductor device includes: wiring layers laminated in a first direction and including conducting members; and a second wiring layer including a bonding pad electrode. The first wiring layers each include a bonding pad area. The bonding pad area overlaps with the bonding pad electrode viewed in the first direction. The conducting member is absent in an area inside a first imaginary circle with a first point as a midpoint in the bonding pad area. The conducting members are disposed in an area outside a second imaginary circle in the bonding pad area. The second imaginary circle has the first point as a midpoint and has a radius equal to or more than a radius of the first imaginary circle. When the radius of the first imaginary circle is denoted as R1 and the radius of the second imaginary circle is denoted as R2, R2/R1 is smaller than 1/cos(?/4).