Abstract: A high-speed, soft-recovery semiconductor device that reduces leakage current by increasing the Schottky ratio of Schottky contacts to pn junctions. In one embodiment of the present invention, an n− drift layer is formed on an n+ cathode layer 1 by epitaxial growth, and ring-shaped ring trenches having a prescribed width are formed in the n− drift layer. Oxide films are formed on the side walls of each ring trench. The ring trenches are arranged such that the centers of the rings of the ring trenches adjacent to one another form a triangular lattice unit. A p− anode layer is formed at the bottom of each ring trench. Schottky contacts are formed at the interface between an anode electrode and the surface of the n− drift layer. Ohmic contact is established between the surfaces of polysilicon portions and the anode electrode.

Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: A sealed symmetric multilayered package with integral windows for housing one or more microelectronic devices. The devices can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the windows being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic devices can be flip-chip bonded and oriented so that the light-sensitive sides are optically accessible through the windows. The result is a compact, low-profile, sealed symmetric package, having integral windows that can be hermetically-sealed.

Abstract: Disclosed is an inventive diode which can reduce a stray capacity to improve various characteristics thereof, in which a dielectric layer, a conductive layer and a second dielectric layer are respectively formed by deposition in this order on an upper face of a semiconductor substrate excluding a central portion of an exposed surface of a P-type region. Then, an anode side electrode is formed extending from the exposed surface of the P-type region to the upper face of the second dielectric layer, and is electrically connected with the P-type region. Herein, the conductive layer is formed such that it is isolated from the electrode by the second dielectric layer, is connected with the semiconductor substrate upper face in a location where the dielectric layer has not been formed, and partially resides in a location sandwiched between the electrode and the semiconductor substrate.

Abstract: A semiconductor device, such as a pin diode, includes a first drift layer, a second drift layer, an anode layer on the first drift layer, and a buffer layer formed between the first and second drift layers. The shortest distance from the pn-junction between the anode layer and the buffer layer, and the thickness of the buffer layer are set at the respective values at which a high breakdown voltage is obtained, while reducing the tradeoff relation between the soft recovery and the fast and low-loss reverse recovery.

Abstract: A receiver for radio or television signals provided with a high-frequency circuit comprising a discrete semiconductor component which includes a planar variable capacitance diode formed on a semiconductor substrate of a first doping type with a first doping density n1, on which semiconductor substrate an epitaxial layer of the same doping type with a second doping density n2>n1 is provided, on which epitaxial layer an insulation layer having a first window is provided by means of a first laterally bounded semiconductor region of a second doping type with a doping density n3>n2 in the epitaxial layer below the first window, and a first contact pad which contacts the first laterally bounded semiconductor region via the first window,

Abstract: The invention relates to a semiconductor component which is capable of blocking such as an (IGBT), a thyristor, a GTO or diodes, especially schottky diodes. An insulator profile section (10a, 10b, 10c, 10d, 11) provided in the border area of an anode metallic coating (1, 31) is fixed (directly in the edge area) on the substrate (9) of the component. The insulator profile has a curved area (KB) and a base area (SB), said curved area having a surface (OF) which begins flat and curves outward and upward in a steadily increasing manner. A metallic coating MET1; 30a, 30b, 30c, 30d, 31b) is deposited on the surface (OF). Said coating directly follows the surface curvature and laterally extends the inner anode metallic coating. The upper end of the curved metallic coating (MET1; 30a, 30b . . . ) is distanced and insulated from one of these surrounding outer metallic coatings (MET2; 3) by the surrounding base area (SB) of the insulator profile (10a, . . .

Abstract: The invention relates to a solid-state imaging device (1) which is encapsulated in a ceramic package covered by a transparent window (6) comprising a phosphorus-containing glass. The window is provided with a coating (8), for example of chromium, at the circumference of the window to counteract degradation of the joint between the window and the ceramic package, which degradation results from the sensitivity of phosphorus glass to moisture. The use of phosphorus glass has the advantage that it is opaque to infrared radiation, so that the application of a separate coating serving as an IR filter is avoided and hence the dependence of the sensitivity of the imaging device on the angle of incidence of the radiation to be detected.

Abstract: A bond pad structure is provided which has a primary bond pad region electrically connected to a secondary bond pad region. The secondary bond pad region is used to test a circuit for configuration, while the primary bond pad is covered with a protective oxide. After configuration and etching to complete desired disconnections, the oxide is removed from the primary bond pad region, leaving an undamaged surface for subsequent wire bonding. The primary bond pad region and the secondary bond pad region can be a unitary structure or two separate structures.

Abstract: A semiconductor diode structure comprising a Schottky junction, where a metal contact and a silicon carbide semiconducting layer of a first conducting type form said junction and where the edge of the junction exhibits a Junction Termination Extension (JTE) laterally surrounding the junction, said JTE having a charge profile with a stepwise or uniformly decreasing total charge or effective sheet charge density from an initial value to a zero or almost zero total charge at the outermost edge of the termination following a radial direction from the centre part of the JTE towards the outermost edge of the termination. The object of the junction termination extension is to control the electric field at the periphery of the diode.

Abstract: A semiconductor diode has two electrodes that form a cathode and an anode. The semiconductor diode is distinguished by the fact that at least one of the electrodes is curved, and that a surface area of the other electrode amounts to at most 20% of a product of a width of the other electrode and an inner edge length of the curved electrode. An electrical circuit constructed in such a way that it contains the semiconductor diode is also disclosed. The semiconductor diode contains two electrodes which form the cathode and anode, and is distinguished by the fact that at least one of the electrodes is curved, and that the surface area of the other electrode amounts to at most 20% of the product of the width of the other electrode and the inner edge length of the curved electrode.

Abstract: The invention provides a zener zap diode having a high reliability and a method of manufacturing the same that can remove the problems accompanied with the zener zap trimming. In order to attain the object, the zener zap diode according to the invention is constructed such that, in an area adjacent to the surface of a semiconductor substrate, an active base region, an outer base region, and an emitter region are formed. Furthermore, a base lead electrode (one polysilicon layer) is formed to overlay the outer base region, and an emitter lead electrode (another polysilicon layer) is formed above the active base region. A contact between the one polysilicon layer and a metal interconnecting layer is disposed right above the outer base region. Since the insulation film that hinders the filament from being formed is not disposed under the one polysilicon layer, a filament is widely formed into an N-type well region when a PN junction is zapped by the zener zap trimming method.

Abstract: An area-variable varactor diode is disclosed, in which the capacitance can be arbitrarily varied under an applied bias voltage. The area-variable varactor diode is characterized in that, in order to ensure freedom to designing the epi-layer, to obtain the desired capacitance characteristics, and to facilitate the integration with other elements, a steeply varied depletion layer area is provided through a variation of the surface layout area, and thus, varied capacitance characteristics are obtained. In steeply varying the area of the depletion layer, an etching of the active layer, a selective epi-layer growth, and an ion implantation are carried out or a combination of them is carried out. The capacitance characteristics are varied in accordance with the pattern of the mask, and therefore, a restriction is not imposed on the epi-layer, with the result that an integration with other elements becomes easy.

Abstract: A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.

Abstract: A process for fabricating sequential inductors and varactor diodes of a monolithic, high voltage, nonlinear, transmission line in GaAs is disclosed. An epitaxially grown laminate is produced by applying a low doped active n-type GaAs layer to an n-plus type GaAs substrate. A heavily doped p-type GaAs layer is applied to the active n-type layer and a heavily doped n-type GaAs layer is applied to the p-type layer. Ohmic contacts are applied to the heavily doped n-type layer where diodes are desired. Multiple layers are then either etched away or Oxygen ion implanted to isolate individual varactor diodes. An insulator is applied between the diodes and a conductive/inductive layer is thereafter applied on top of the insulator layer to complete the process.

Abstract: A varactor diode having a stepped capacitance-voltage profile, formed in heterostructural integrated circuit technology. Several layers in the diode structure have pulse doping to confine conduction in the diode to a sheet of charge that provides the stepped capacitance-voltage profile. The structural design of the diode may be modified to attain desired capacitance-voltage characteristics.

Abstract: A planar frequency tripler comprised of two semiconductor diode structures connected back-to-back by an n.sup.+ doped layer (N.sup.+) of semiconductor material utilizes an n doped semiconductor material for a drift region (N) over the back contact layer in order to overcome a space charge limitation in the drift region. A barrier layer (B) is grown over the drift region, after a sheet of n-type doping (N.sub.sheet) which forms a positive charge over the drift region, N, to internally bias the diode structure. Two metal contacts are deposited over the barrier layer, B, with a gap between them. To increase the power output of the diodes of a given size, stacked diodes may be provided by alternating barrier layers and drift region layers, starting with a barrier layer and providing a positive charge sheet at the interface of a barrier on both sides of each drift region layer with n-type .delta. doping. The stacked diodes may be isolated by etching or ion implantation to the back contact layer N.sup.

Abstract: An integrated coplanar strip nonlinear transmission line comprising a substrate of gallium arsenide upon which a heavily doped buried layer and a lightly doped surface layer of epitaxially grown gallium arsenide are grown. Two parallel conductors are integThis work was funded by the United States Government's Office of Naval Research under contract No. N99914-85-K-0381. The United States Government has a paid up license in this technology.

Abstract: A variable field effect capacitive device suitable for providing different amounts of capacitance in response to control signals of different magnitudes. The device includes a pair of plate electrodes and a pair of control electrodes. A semiconductor region is located between the control electrodes. The plates each make Schottky contact to the semiconductor region to form a depletion region therein which changes shape in response to changes in the magnitude of the control signals.

Abstract: A resin sealed semiconductor device for use in testing is disclosed, in which a first MOS field effect transistor is formed in a region within 100 .mu.m from an outer perimeter of a main surface of a silicon substrate, and a second MOS field effect transistor is formed in a region 100 .mu.m or more distant from an outer perimeter of the main surface, and the first and second MOS field effect transistors are encapsulated with resin. Dimensions and materials of the first MOS field effect transistor and the second MOS field effect transistor are identical. By comparing the electric characteristics of the first MOS field effect transistor and the electric characteristics of the second MOS field effect transistor, the effect produced on the MOS field effect transistors by the mechanical stresses due to the resin seal applied from a side direction of silicon substrate can be evaluated.