Abstract: A lateral bipolar transistor structure (10) formed in a laterally isolated semiconductor device tub (22) of a first conductivity type is provided. First and second trenches are etched in the device tub and filled with doped polysilicon of a second conductivity type to form an emitter (30) and a collector (32). The portion of the tub (22) between the emitter (30) and collector (32) regions forms a base region. This configuration provides high emitter area and minimal device surface area, as well as emitter (30) and collector (32) regions which are interchangeable, greatly easing layout of integrated circuits using the transistor structure (10).

Abstract: This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is (111) is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral trench is formed at the bottom portion of the side wall of the vertical trench by effecting an anisotropic etching with respect to crystallographical axes so that the etching proceeds in the direction of <110> axis, the lateral and the vertical trenches being filled with polycrystalline or amorphous semiconductor or insulator.

Abstract: A logic circuit comprising an active-pull-down circuit in which electrodes of an active capacitor are formed of a conductive layer in common with one of contact electrodes of neighboring transistors is disclosed. The area for the capacitor is reduced, so that the element-occupied area is minimum even when the absorbing capability of the active-pull-down circuit is designed to be high for reducing a transient duration of an output signal. Besides, capacitor insulation film is used as a mask during a process, so that the process for fabrication of the integrated circuit is simplified.

Abstract: A bipolar transistor is provided in which the emitters do not traverse the base but terminate inside the top surface of the base. Each emitter is L-shaped in some embodiments. The base top surface has a polygonal or circular outer boundary. The transistor has a long emitter perimeter available for base current flow and more than two emitter sides (e.g., five sides) available for base current flow. Further, the transistor has a large ratio of the emitter area to the base area. Consequently, the transistor has low noise, high gain, high frequency range, and a small size.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.

Abstract: Disclosed is an improved bipolar-and-complementary MOS transistor coexisting semiconductor device and a method of making the same. A collector-and-base separator is formed on the site allotted to a bipolar transistor along with a source-and-drain separator on each site allotted to PMOS and NMOS transistors. The superficial collector-and-base separator coating causes no stress to the lattice of the underlying region in the epitaxy of the semiconductor substrate, and therefore there can be no lattice defect which may appear in a conventional composite type semiconductor device structure as a result of selective oxidization of the epitaxial layer to separate the base and collector region of the bipolar transistor. Such a superficial collector-and-base separator according to the present invention assures that the bipolar transistor each of such composite type semiconductor devices is free from the lowering of the breakdown voltage at its collector-and-base junction.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device includes the steps of forming a first conductivity type layer on one surface of a work piece comprising a semiconductor substrate. A gate oxide is formed on the surface of the substrate. A first conductive structure is formed on the gate oxide consisting essentially of polysilicon. An insulating structure is formed in contact with the first conductive structure. Material is removed from the surface of the first conductive structure to expose at least a portion of the surface of the first layer, and to form on the remaining structure on the workpiece a second conductive structure consisting essentially of polysilicon. The polysilicon is in electrical contact with the first conductive structure. Thus, a compound conductive structure is provided on the work piece.

Abstract: A self-aligned process for fabricating high performance bipolar transistors for integrated circuits includes the formation of a collector contact and intrinsic collector region within an opening at the face of a semiconductor substrate. In particular, layers of oxide and polysilicon are formed on the surface of a substrate. An opening is then formed in both layers followed by the implantation of a buried collector region into the substrate at the exposed substrate face through the opening. Polysilicon contacts to the buried layer are then formed on the sidewalls of the opening. These contacts join with the polysilicon layer to form a collector contact. An oxide is then grown on the collector contact. A monocrystalline intrinsic collector is then formed from the exposed substrate face adjacent said collector contact. In this manner, the buried collector, collector contact and intrinsic collector are all formed in a self-aligned manner.

Abstract: A process and structure for resolving the divergent etching requirements of a relatively thick base oxide (62) and a relatively thin gate oxide (64) in a BiCMOS integrated circuit. The necessity of etching base oxide (62) is eliminated by extending nitride mask (58) over the extrinsic base region (86) so that the relatively thick base oxide (62) only covers intrinsic base region (60) and tab region (61). Base oxide (62) at tab region (61) is partially etched in the course of forming sidewall oxide filaments (78), resulting in the residual tab oxide (62'). An extrinsic base implant is performed in extrinsic base region (86) and tab region (61), with the presence of residual tab oxide (62') affecting the profile of the implant so that it is stepped. The resulting structure, after an anneal, is extrinsic base (87'), an intrinsic base (63) (formed prior to the extrinsic base implant), and an overlap region (88') common to both.

Abstract: A silicon film 9 and an N.sup.+ -type impurity region 9a are provided between a base region 11 and an epitaxial growth layer 3. A silicon oxide film 12 is provided on the inner sidewalls of an opening 16, and an N-type polycrystalline silicon film 13 and an emitter region 15 are provided in the region surrounded by the silicon oxide film 12.The silicon film 9 is formed by means of a molecular beam epitaxy and the N-type impurity region 9a is formed prior to the formation of the base region 11 by means of ion implantation that uses a silicon oxide film 7 as the mask. As a result, it is possible to suppress the reduction in the cut-off frequency, and reduce the capacity between the base and the collector, so that a high speed operation of the bipolar transistor becomes possible.

Abstract: A bipolar transistor is disclosed which substantially reduces prior art problems associated with current crowding by maximizing the active periphery of the transistor's emitter [10].

Abstract: A bipolar transistor with a trench. The trench extends down into a buried collector region through an emitter region, the underlying intrinsic base and collector regions at their center portion. Insulating films are formed on the sidewalls of the trench. The trench is filled with a collector-connection conductor which contacts with the buried collector region.

Abstract: A contact hole for guiding an emitter electrode of bipolar transistors continuously arrayed and a contact hole for guiding a base electrode are positioned not to be arranged in the continuous array direction of the bipolar transistors. Also, the emitter electrode and the base electrode are respectively drawn from these contact holes in two directions different from the continuous array direction of the bipolar transistors. At least one of the base electrode and the emitter electrode is formed on a conductive layer of a polycide structure contacting an active region in a substrate to be connected.

Abstract: A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.

Abstract: A vertical bipolar transistor is constructed with reduced step height by codeposition of a polysilicon base contact member and an epitaxial device layer, thereby placing the base contact below the device surface, and by the use of a doped glass layer as a dopant source for the base contact and as a dopant source to provide a continuous conductive path to the base, and as the dielectric separating the base contact from the emitter contact, and as an etch stop when forming the base implantation aperture.

Abstract: In an open-hole section formed in a silicon oxide layer, a polycrystalline silicon layer, which will become a lower layer of an emitter electrode, is deposited and arsenic ions are implanted into it. Next, on top of the polycrystalline silicon layer, another polycrystalline silicon layer, which will become an upper layer of the emitter electrode, is deposited and implanted with a high density of arsenic ions. Through heat treatment, an N-type emitter diffusion layer is formed inside a P-type intrinsic base diffusion layer. By constructing the emitter electrode with 2 layers, the lower layer and upper layer, and by optimizing the impurity density in each of the layers, the characteristic irregularities of a bipolar transistor having minute emitter contact holes are reduced, and it is possible to increase the allowance of the formation conditions of the open-hole section which connects a wiring layer and to reduce the emitter resistance.

Abstract: A first region of a first conductivity type is formed in the surface of a semiconductor body, and second and third regions of a second conductivity type are formed on and under, respectively, of the first region. An electrode region formed on a first insulating film formed on the semiconductor body is connected electrically to the first region. The electrode region is defined as having an elongated first part an upper surface of which is connected to an electrode, and having a second, different part which has a substantially constant width and which width is substantially equal to the thickness of the first portion of the electrode region. A metal silicide film is formed over the upper surface of the first portion of the electrode region. The first, second and third regions can be base, emitter and collector regions, respectively, of a bipolar transistor formed in an island region of an epitaxially grown layer on a semiconductor substrate.

Abstract: A bipolar transistor including a semiconductor layer formed on a semiconductor substrate; a base region formed at an upper portion of the semiconductor layer; a graft base region formed at the upper portion of the semiconductor layer so as to connect with a periphery of the base region; an emitter region formed at an upper portion of the base region; an offset insulating film formed on the base region around the emitter region; a collector buried region formed in the semiconductor layer below the base region; a collector drawn region formed in the semiconductor layer so as to connect with the collector buried region and be arranged on the side of the base region adjacent to an element isolating region; an emitter electrode formed on the offset insulating film so as to connect with the emitter region; an emitter insulating film formed so as to cover the emitter electrode; a base electrode formed so as to connect with the graft base region and contact with the emitter insulating film; and a collector electrode

Abstract: In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.

Abstract: A semiconductor device includes an insulating support layer on which are mounted, in succession, a conductive layer, a buried layer comprising first and second spaced portions and a semiconductor single crystal layer comprising spaced first and second portions respectively supported on the first and second spaced portions of the buried layer, the respective first and second portions having respective, first and second common sidewalls defining respective, first and second peripheries thereof and respectively comprising a transistor region and a collector electrode region. A remaining exposed surface portion of the conductive layer extends between the spaced, opposing portions of the sidewalls of the transistor and collector electrode regions.

Abstract: In order to simplify the structure of a power amplifying transistor and improve its high-frequency characteristics, a base electrode (7b) and a collector electrode (7c) are formed on the surface of such a power amplifying transistor, while an emitter electrode (7e) is formed on its rear surface. Since it is possible to easily ground the emitter electrode (7e) and use the base and collector electrodes (7b, 7c) as an input and an output respectively, the structure is simplified and no wiring pattern is required, whereby high-frequency characteristics can be improved.

Abstract: A bipolar transistor and a diode are incorporated in a semiconductor integrated circuit device, and an emitter electrode is constituted by lower and upper doped polysilicon films sandwiching an oxygen-leakage film which tunnels minority carriers of the base therethrough at higher probability than the majority carriers so as to enhance the emitter injection efficiency, thereby allowing a designer to increase the base width and the distance from the p-n junction between the anode and the cathode for improving the breakdown voltage of the diode without sacrifice of the current amplification factor.

Abstract: A Si-SiGe-Si heterojunction bipolar transistor which has a very thin epitaxial base layer. The device possesses an optimum doping profile across a base layer. The emitter region is higher doping concentration of n.sup.+ -type. The base layer of p-type comprises both a monocrystalline SiGe layer having a lightly doped region on a collector side and a heavily doped region, and a lightly doped monocrystalline Si layer on an emitter side. An emitter side Si-SiGe heterojunction exists in the base layer and a collector side Si-SiGe heterojunction exists in the collector region. Those provides a slope negative gradient of a potential profile from the emitter to collector without a potential barrier for carriers, or electrons or holes. The very thin base layer is connected to an aluminium contact through an external base layer and a base contact layer thereby permitting the very thin base layer to be free from a damage by contacting with a metal such as aluminium.

Abstract: The present invention relates to a semiconductor device which comprises: an n.sup.- type buried collector provided on an n type silicon epitaxial layer disposed in an emitter opening; an n.sup.- type silicon collector disposed on said collector; a p.sup.+ type single crystal silicon intrinsic base layer; and an n.sup.+ type single crystal silicon emitter wherein said p.sup.+ type single crystal silicon intrinsic base layer is connected with a p.sup.+ type base electrode polycrystalline silicon through a p.sup.+ type polycrystalline silicon graft base.

Abstract: A transistor (10 or 11) and method of formation. The transistor (10) has a substrate (12). The substrate (12) has an overlying dielectric layer (14) and an insulated conductive control electrode (16) which overlies the dielectric layer (14). A dielectric region (18) overlies the insulated conductive control electrode (16), and a dielectric region (20) is adjacent to the insulated conductive control electrode (16). A spacer (30) is adjacent to the dielectric region (20). Epitaxial regions (24) are adjacent to the spacer (30) and the spacer (30) is overlying portions of the epitaxial regions (24). A dielectric region (26) overlies the epitaxial regions (24). Highly doped source and drain regions (32) underlie the epitaxial regions (24). LDD regions (28), which are underlying the spacer (30), are adjacent to and electrically connected to the source and drain regions (32).

Abstract: A semiconductor device including a MOS element having a buried contact structure. The buried contact structure includes a first contact diffused region formed by diffusion from a polycrystalline silicon layer and a second contact diffused region formed by diffusion deeper than the first contact diffused region, so that a parasitic resistance of the MOS element can be reduced. In a composite element composed of the MOS element and a bipolar element, partly since the first contact diffused region and an emitter diffused region of the bipolar element can be formed simultaneously, and partly since the depth of connection of the emitter diffused region, with the parasitic resistance of the MOS element being reduced, it is possible to realize a high-speed operation.

Abstract: A semiconductor device including a semiconductor substrate, first and second bipolar transistors formed at the major surface of the semiconductor substrate, a Schottky-barrier diode formed on a predetermined area of each of the first and second bipolar transistors, a capacitor formed on each of the first and second bipolar transistors, each capacitor including an insulating layer covering a surface of a respective one of the first and second bipolar transistors, a polysilicon layer formed on the insulating layer in a pattern that extends around the predetermined area, a dielectric film formed covering the polysilicon layer, and a conductive film covering the dielectric film.

Abstract: A silicon-on-insulator lateral bipolar transistor having an edge-strapped base contact is disclosed. A thin layer of oxide is deposited on a silicon-on-insulator structure and a layer of polysilicon is deposited on the thin oxide layer that is patterned and etched to form an extrinsic base region of the transistor. The polysilicon extrinsic base is very heavily doped and the thin oxide layer acts as both a diffusion stop and an etch stop during the formation of the extrinsic base. A silicon edge contact region is formed of selective epitaxy or polysilicon to connect the extrinsic base to the intrinsic base formed in the silicon-on-insulator layer.

Abstract: A bipolar transistor comprising a semiconductor substrate, of a first conductivity type, a retrograde well serving as the collector and having a second conductivity type opposite to the first, a base active region having a first conductivity type, a region serving as an emitter of the second conductivity type, the regions being bordered on either side by insulating regions. According to the invention, the transistor includes at least one second conductivity type zone serving as the collector contact, located in a region of the retrograde well at a distance from the base zone and extending away from said base zone no further than level with the insulating zone. The invention is applicable to making BI-MOS or BI-CMOS circuits.

Abstract: This invention is an SOI BICMOS process which uses oxygen implanted wafers as the starting substrate. The bipolar transistor is constructed in two stacked epitaxial layers on the surface of the oxygen implanted substrate. A buried collector is formed in the first epitaxial layer that is also used for the CMOS transistors. The buried collector minimizes the collector resistance. Selective epitaxial silicon is then grown over the first epitaxial layer and is used to form the tanks for the bipolar transistors. An oxide layer is formed over the base to serve as an insulator between the emitter poly and the extrinsic base, and also as an etch stop for the emitter etch. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the epitaxial layer and overlaps the oxide layer.

Abstract: A bipolar transistor having a base intrinsic region, collector region, and emitter region. The emitter region, collector region, and base intrinsic region each having at least a portion thereof adjacent to an oxide isolation region. The base intrinsic region having a diffusion compensation region therein abutting the oxide isolation region. The diffusion compensation region compensates for the intrinsic concentrations segregating during oxidation, and also compensates for oxide charge contribution to the base region. The additional dopant in the compensation region results in only a small increase in the desired BJT performance and adds minimal complexity in manufacturing. The invention results in the controlled placement of dopants near the "birds's beak" between the emitter and base providing I.sub.CEO leakage current reduction at the emitter edge without affecting the bulk of the active intrinsic base.

Abstract: A self-aligned process for fabricating high performance bipolar transistors for integrated circuits includes the formation of a collector contact and intrinsic collector region within an opening at the face of a semiconductor substrate. In particular, layers of oxide and polysilicon are formed on the surface of a substrate. An opening is then formed in both layers followed by the implantation of a buried collector region into the substrate at the exposed substrate face through the opening. Polysilicon contacts to the buried layer are then formed on the sidewalls of the opening. These contacts join with the polysilicon layer to form a collector contact. An oxide is then grown on the collector contact. A monocrystalline intrinsic collector is then formed from the exposed substrate face adjacent said collector contact. In this manner, the buried collector, collector contact and intrinsic collector are all formed in a self-aligned manner.

Abstract: A semiconductor device includes a bipolar transistor and an IIL element fabricated on a single wafer. The emitter region of the bipolar transistor is formed by diffusing the impurity of an impurity layer formed in contact with the base region therein. The impurity layer is formed of a polycide layer formed of a polysilicon layer doped with an impurity and a metal silicide layer laminated on the polysilicon layer, a laminated layer of a polysilicon layer and a refractory metal layer, or a metal silicide layer.

Abstract: Semiconductor devices having a reduced parasitic capacitance while having a maximum acceptable current similar to those of prior devices, and a method of manufacturing thereof are disclosed. The inventive device has a hole at the bottom of which an insulating film separated from the hole walls is located, a semiconductor film being present in the hole, which is connected to the semiconductor substrate adjacent to the insulating film and a conductor film constituting a portion of the hole wall, and extends onto the insulating film so as to cover at least part of the film.

Abstract: An improved bipolar transistor is provided which can be formed using a number of process steps which are similar to those used for forming MOSFETs. As such, the bipolar transistor is particularly useful in BiCMOS device arrangements. In accordance with one embodiment, a bipolar transistor is formed so that at least one of the emitter and collector regions has a high impurity region and a low impurity region. The collector and emitter regions of the device are formed in the base region to be spaced apart from one another, and the base electrode is arranged to cover the area of the base region between them. In an alternative embodiment, two collector regions can be provided in a base region on opposite sides of an emitter which is also formed in the base region. Two base electrodes can then be respectively provided in the areas between the two collectors and the emitter region. The bipolar transistors are particularly useful for forming a horizontal bipolar transistor structure.

Abstract: A pre-processed substrate structure for a semiconductor device. A subcollector layer is spaced apart from a substrate by a dielectric. A relatively small, lightly-doped epitaxial feed-through layer extends through the dielectric between the substrate and the subcollector. A transistor constructed over the subcollector has very low collector-to-substrate capacitance. A plurality of devices on a common substrate are electrically isolated from each other by channel stops formed in the substrate around each device.

Abstract: A stress isolating signal path having one end of fixed to a bonding pad of an integrated circuit chip and another end which forms a flexible bonding surface is provided. The flexible bonding surface may be bonded to external package components or external circuitry using conventional wire bond, epoxy bond, tape automated bonding, flip chip bonding, or the like. The signal path is formed using conventional semiconductor thin film deposition, patterning, and etching techniques. The signal path comprises a conductive material compatible with batch semiconductor manufacturing technology.

Abstract: A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base region generally bounding a portion of the first region; forming by ion implantation a linking region of the second conductivity type in the surface of the bounded portion of the first region so as to electrically link generally opposing edges of the extrinsic base region through the linking region; forming an insulating spacer over the junction between the extrinsic base region and the linking region so as to generally bound a portion of the linking region within the portion of the first region; etching the surface of the bounded portion of the linking region a short distance into the linking region; forming by epitaxial growth a first layer of semiconductor material of the second conductivity type on the etched surface of t

Abstract: This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is a (111) plane is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral trench is formed at the bottom portion of the side wall of the vertical trench by effecting an anisotropic etching with respect to crystallographical axes so that the etching proceeds in the direction of <110> axis, the lateral and the vertical trenches being filled with polycrystalline or amorphous semiconductor or insulator.

Abstract: A semiconductor integrated circuit device includes at least two bipolar transistors having a first type structure in which a wiring layer is formed in direct contact with the emitter region thereof and at least one bipolar transistor having a second type structure in which a polysilicon layer is formed on the emitter region thereof. The transistor having the first type structure is used in a circuit which is required to have a high matching degree. The transistor having the second type structure is used in a circuit which is required to have a high performance, low power consumption and high integration density rather than a high matching degree.

Abstract: A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region.

Abstract: A bipolar transistor having an inverse-T emitter electrode is formed in a semiconductor device (10) to reduce hot carrier injection (HCI) damage under reverse-biasing conditions and to increase emitter-base breakdown voltages. The bipolar transistor includes an emitter electrode having a central body portion (26) and shelf portions (38). Beneath the emitter electrode is an emitter region (30) and an active base region (25). Extrinsic base regions (35 and 36) are self-aligned to the shelf edges and are linked to the ative base region by link regions (27 and 28). Having the emitter-base junction beneath the shelf portions, and therefore under direct control of the emitter electrode, decreases the electrical field at the junction, which lessens HCI damage and improves breakdown characteristics. The inverse-T emitter electrode also eliminates the need to etch a polysilicon emitter electrode selective to an underlying silicon substrate.

Abstract: A bipolar transistor with a collector, a base and an emitter disposed in vertical succession includes a semiconductor substrate, insulating oxide zones disposed in the substrate for separating adjacent transistors, and a buried collector terminal layer at least partly disposed on the insulating oxide zones. An insulator structure laterally surrounding a collector. A subcollector is surrounded by the insulating oxide zones, has the same conductivity type with a lower impedance than the collector, is disposed under the collector and under the insulator structure, and is electrically connected to the collector. The insulator structure covers the buried collector terminal layer, laterally insulates the collector from the buried collector terminal layer, and has lateral surfaces extending inside the insulating oxide regions up to the subcollector. The buried collector terminal layer is in direct contact with the subcollector.