Abstract: A sealing resin composition contains an epoxy resin (A), a curing agent (B) having at least one amino group in one molecule, and an inorganic filler (C), wherein the inorganic filler (C) contains a first inorganic filler (C1) having an average particle size from 0.1 ?m to 20 ?m and a second inorganic filler (C2) having an average particle size from 10 nm to 80 nm, and a value obtained by multiplying a specific surface area of the inorganic filler (C), by a proportion of a mass of the inorganic filler (C) in a solid mass of the sealing resin composition, is 4.0 mm2/g or more.

Abstract: A sealing resin composition contains an epoxy resin (A), a curing agent (B) having at least one amino group in one molecule, and an inorganic filler (C), wherein the inorganic filler (C) contains a first inorganic filler (C1) having an average particle size from 0.1 ?m to 20 ?m and a second inorganic filler (C2) having an average particle size from 10 nm to 80 nm, and a value obtained by multiplying a specific surface area of the inorganic filler (C), by a proportion of a mass of the inorganic filler (C) in a solid mass of the sealing resin composition, is 4.0 mm2/g or more.

Abstract: A sealing resin composition contains an epoxy resin (A), a curing agent (B) having at least one amino group in one molecule, and an inorganic filler (C), wherein the inorganic filler (C) contains a first inorganic filler (C1) having an average particle size from 0.1 ?m to 20 ?m and a second inorganic filler (C2) having an average particle size from 10 nm to 80 nm, and a value obtained by multiplying a specific surface area of the inorganic filler (C), by a proportion of a mass of the inorganic filler (C) in a solid mass of the sealing resin composition, is 4.0 mm2/g or more.

Abstract: A Micro-Electro-Mechanical Systems (MEMS) device includes a first substrate with a first surface and a second surface, the first substrate including a base layer, a moveable beam disposed on the base layer, at least one metal layer, and one or more standoffs disposed on the base layer such that one or more metal layers are situated on the top surface of the one or more standoffs. The MEMS device further includes a second substrate including one or more metal layers bonded to the one or more standoffs resulting in an electrical connection between at least a portion of the one or more metal layers of the second substrate and one or more of the at least one electrode on the bottom surface and the at least one electrode on the top surface.

Abstract: According to one embodiment, there is disclosed a MEMS element. The MEMS element includes a lower electrode having a surface on which a plurality of minute convex portions are formed. A plurality of dielectric bumps are provided on the upper surface of the lower electrode and are thicker than heights of the convex portions. A dielectric layer is provided on the dielectric bumps and the lower electrode. An upper electrode is provided above the dielectric layer. The upper electrode is movable so as to vary capacitance between the upper electrode and the lower electrode.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one fixed electrode on a substrate. The method further includes forming a Micro-Electro-Mechanical System (MEMS) beam with a varying width dimension, as viewed from a top of the MEMS beam, over the at least one fixed electrode.

Abstract: According to one embodiment, there is disclosed a MEMS element. The MEMS element includes a lower electrode having a surface on which a plurality of minute convex portions are formed. A plurality of dielectric bumps are provided on the upper surface of the lower electrode and are thicker than heights of the convex portions. A dielectric layer is provided on the dielectric bumps and the lower electrode. An upper electrode is provided above the dielectric layer. The upper electrode is movable so as to vary capacitance between the upper electrode and the lower electrode.

Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.

Abstract: This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.

Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.

Abstract: An energy conversion device, and methods of manufacturing and operating the same. The energy conversion device includes: a monolithic single-crystal silicon layer that includes a plurality of doping regions; a vibrator that is disposed in the single-crystal silicon layer and is connected to a doping region of the plurality of doping regions; a first diode that is a PN junction diode and allows an input signal applied to the vibrator to pass therethrough; and a second diode that is a PN junction diode and allows a signal output from the vibrator to pass therethrough.

Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.

Abstract: The embodiments of the invention provide a structure, method, etc. for a fin differential MOS varactor diode. More specifically, a differential varactor structure is provided comprising a substrate with an upper surface, a first vertical anode plate, and a second vertical anode plate electrically isolated from the first vertical anode plate. Moreover, a semiconductor fin comprising a cathode is between the first vertical anode plate and the second vertical anode plate, wherein the semiconductor fin, the first vertical anode plate, and the second vertical anode plate are each positioned over the substrate and perpendicular to the upper surface of the substrate.

Abstract: A nanowire-based device and method employ removal of residual carriers. The nanowire-based device includes a semiconductor nanowire having a semiconductor junction, and a residual carrier sink. The residual carrier sink is located at or adjacent to the semiconductor nanowire near the semiconductor junction and employs one or both of enhanced recombination and direct extraction of the residual carriers. The method includes providing a semiconductor nanowire, forming a semiconductor junction within the semiconductor nanowire, forming a residual carrier sink, and removing residual carriers from the semiconductor junction region using the residual carrier sink.

Abstract: A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.

Abstract: A MESA-type photonic detection device, including at least one first junction, which itself includes a first receiving layer and sides formed or etched in the receiving layer. These sides at least partially include a layer with a doping opposite the doping of the first receiving layer.

Abstract: An RF MEMS tuneable arrangement, e.g. variable capacitor, having two or more tunable devices, e.g. variable capacitances, a coupling circuit arranged to couple the tunable devices together to provide a combined output, e.g. a combined capacitance, that is variable according to a tuning signal. The coupling circuit is reconfigurable to alter a response of the arrangement to changes in the tuning signal, to enable a broader range of applications, manufacturing cost reductions and more flexibility in design. The device can have a pivoted beam (30), actuable by a control signal, the beam having electrodes (40, 60) at either side of the pivot, and corresponding fixed electrodes (50, 70) facing the electrodes on the beam to provide a two or more variable devices such as switches or variable capacitors, arranged such that a given movement of the beam causes electrode separation in the same direction for the two or more switches or capacitors.

Abstract: A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.

Abstract: A varactor on a substrate is provided. The varactor comprises a bottom electrode, an upper electrode, a first dielectric layer and a conductive layer. The bottom electrode has several doped regions arranged in the substrate as an array with several rows and several columns, wherein the doped regions in adjacent columns are arranged alternatively. The upper electrode is located over the substrate and the upper electrode is composed of several electrode locations and has several openings, wherein each opening exposes the corresponding doped region. Furthermore, each electrode location is surrounded by three doped regions. The first dielectric layer is located between the substrate and the upper electrode. The conductive layer is located over the upper electrode, wherein the conductive layer and the upper electrode are isolated from each other and the conductive layer and the doped regions are electrically connected to each other.

Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.

Abstract: A nanowire capacitor and methods of making the same are disclosed. The nanowire capacitor includes a subrate and a semiconductor nanowire that is supported by the substrate. An insulator is formed on a portion of the surface of the nanowire. Additionally, an outer coaxial conductor is formed on a portion insulator and a contact coupled to the nanowire.

Abstract: Projecting elongate stub walls are provided on the planar surfaces of a substrate at positions where bonding of the substrate to a clamping lid or base is to be carried out. On firing of the substrate, the surfaces thereof are mechanically processed but since the stub walls protrude from the substrate, the grinding and polishing tools make contact with the surfaces of these stub walls, rather than with the entire substrate surface. As a result, the area of the substrate to be processed is minimised and problems with dishing and erosion are alleviated. This allows the clamping lid, or frame to be bonded, using conventional conductive adhesive processes, avoiding the cracking and stress problems associated with non-uniformity of the surface of the ceramic substrates.

Abstract: Disclosed is a semiconductor structure, which includes a non-planar varactor having a geometrically designed depletion zone with a taper, as to provide improved Cmax/Cmin with low series resistance. Because of the taper, the narrowest portion of the depletion zone can be designed to be fully depleted, while the remainder of the depletion zone is only partially depleted. The fabrication of semiconductor structure may follow that of standard FinFET process, with a few additional or different steps. These additional or different steps may include formation of a doped trapezoidal (or triangular) shaped silicon mesa, growing/depositing a gate dielectric, forming a gate electrode over a portion of the mesa, and forming a highly doped contact region in the mesa where it is not covered by the gate electrode.

Abstract: A semiconductor actuator includes a substrate base, a bending structure which is connected to the substrate base and can be deflected at least partially relative to the substrate base. The bending structure has semiconductor compounds on the basis of nitrides of main group III elements and at least two electrical supply contacts which impress an electrical current in or for applying an electrical voltage to the bending structure. At least two of the supply contacts are disposed at a spacing from each other respectively on the bending structure and/or integrated in the latter.

Abstract: A multi-layer structure including a base insulating layer and a thin metal film layer (seed layer) is prepared. A plating resist layer is formed to have a prescribed pattern on the upper surface of the thin metal film layer. A metal plating layer is formed on the thin metal film layer exposed by electroplating. Then, the plating resist layer is removed, and the thin metal film layer in the region having the plating resist layer is removed. In this way, a conductive pattern including the thin metal film layer and the metal plating layer is formed. The upper surface of the base insulating layer in the region without the conductive pattern is subjected to roughening treatment. A cover insulating layer is formed on the upper surfaces of the base insulating layer and the conductive pattern. In this way, a printed circuit board is completed.

Abstract: A semiconductor diode (30) has an anode (32), a cathode (33) and a semiconductor volume (31) provided between the anode (32) and the cathode (33). An electron mobility and/or hole mobility within a zone (34) of the semiconductor volume (31) that is situated in front of the cathode (33) is reduced relative to the rest of the semiconductor volume (31).

Abstract: A Micro-Electro-Mechanical system (MEMS) device includes a doped semiconductor layer that is disposed outwardly from a substrate. The MEMS device further includes an insulation layer that is disposed outwardly from and in contact with the doped semiconductor layer. The MEMS device also includes a conductive membrane that is disposed outwardly from the insulation layer by a distance that defines an air gap between the conductive membrane and the insulation layer. The conductive membrane is operable to come in contact with the insulation layer when an appropriate voltage is applied between the conductive membrane and the doped semiconductor layer. In one particular embodiment, the combination of the doped semiconductor layer and the insulation layer operates to provide a path to dissipate any excess electrical charge received by the insulation layer.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter of the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A high precision microelectromechanical capacitor with programmable voltage source includes a monolithic MEMS device having a capacitance actuator, a trim capacitor, and a high precision, programmable voltage source. The trim capacitor has a variable capacitance value, preferably for making fine adjustments in capacitance. The capacitance actuator is preferably mechanically coupled to and electrically isolated from the trim capacitor and is used to control the capacitance value of the trim capacitor. The capacitance adjustment of the trim capacitor is non-destructive and may be repeated indefinitely. The trim capacitor may be adjusted by mechanically changing the distance between its electrodes. The programmable voltage source provides a highly accurate and stable output voltage potential corresponding to control signals for controlling the capacitance actuator.

Abstract: Disclosed are a vertical-type capacitor and a formation method thereof. The capacitor includes a first electrode wall and a second electrode wall perpendicular to a semiconductor substrate, and at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall. The first electrode wall includes a plurality of first conductive layers and a plurality of first contacts, the plurality of first conductive layers being interconnected with each other by each of the plurality of first contacts. The second electrode wall includes a plurality of second conductive layers and a plurality of second contacts, the plurality of second conductive layers being interconnected with each other by each of the plurality of second contacts.

Abstract: A capacitive dynamic quantity sensor whose size is small and whose reliability and mass productivity are high is provided. In order to realize signal transmission from a lower electrode to an upper electrode, silicon columns which are electrically isolated from one another but not mechanically isolated from one another are formed to connect both electrodes.

Abstract: A voltage-controlled oscillator (VCO) circuit includes first, second, third, and fourth transistors, each with a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor communicates with the first terminal of the second transistor. The control terminals of the third and fourth transistors communicate with the second terminals of the first and second transistors, respectively. The first terminals of the third and fourth transistors communicate with the control terminals of the first and second transistors, respectively. First ends of first and second capacitances communicate with the second terminals of the first and second transistors, respectively. Second ends of the first and second capacitances communicate with the control terminals of the first and second transistors, respectively.

Abstract: A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.

Abstract: Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.

Abstract: A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si1?xGex, where 0.5<x?1, at a temperature substantially below the temperature at which a poly-Si is deposited by thermal chemical vapor deposition (CVD).

Abstract: A nanowire varactor diode and methods of making the same are disclosed. The structure comprises a coaxial capacitor running the length of the semiconductor nanowire. In one embodiment, a semiconductor nanowire of a first conductivity type is deposited on a substrate. An insulator is formed on at least a portion of the nanowire's surface. A region of the nanowire is doped with a second conductivity type material. A first electrical contact is formed on at least part of the insulator and the doped region. A second electrical contact is formed on a non-doped potion of the nanowire. During operation, the conductivity type at the surface of the nanowire inverts and a depletion region is formed upon application of a voltage to the first and second electrical contacts. The varactor diode thereby exhibits variable capacitance as a function of the applied voltage.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70) are formed above the contact isolation structure (32) reducing the parasitic resistance. In addition, contact structures are formed on the gate layer (50) over the well regions (20) is a further embodiment to reduce the parasitic resistance.

Abstract: Electrically tunable electromagnetic bandgap (“TEBG”) structures using a ferroelectric thin film on a semiconductor substrate, tunable devices that include such a TEBG structure, such as a monolithic microwave integrated circuit (“MMIC”), and a method producing such a TEBG structure are disclosed. The present invention provides a semiconductive substrate having an oxide layer, a first conductive layer positioned on the oxide layer, a ferroelectric layer covering the first conductive layer, and a second conductive layer positioned on a surface of the tunable ferroelectric layer. The use of the ferroelectric layer, which have a DC electric field dependent permittivity, enables a small size, tunable EBG structure.

Abstract: A sequential mesa type avalanche photodiode (APD) includes a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.

Abstract: A PN-junction varactor includes a first ion well of first conductivity type formed on a semiconductor substrate of second conductivity type. A first dummy gate is formed over the first ion well. A first gate dielectric layer is formed between the first dummy gate and the first ion well. A second dummy gate is formed over the first ion well at one side of the first dummy gate. A second gate dielectric layer is formed between the second dummy gate and the first ion well. A first heavily doped region of the second conductivity type is located in the first ion well between the first dummy gate and the second dummy gate. The first heavily doped region of the second conductivity type serving as an anode of the PN-junction varactor.

Abstract: A cold electron emitter may include a heavily a p-doped semiconductor, and dielectric layer, and a metallic layer (p-D-M structure). A modification of this structure includes a heavily n+ doped region below the p region (n+-p-D-M structure). These structures make it possible to combine high current emission with stable (durable) operation. The high current density is possible since under certain voltage drop across the dielectric layer, effective negative electron affinity is realized for the quasi-equilibrium “cold” electrons accumulated in the depletion layer in the p-region next to the dielectric layer. These electrons are generated as a result of the avalanche in the p-D-M structure or injection processes in the n+-p-D-M structure. These emitters are stable since they make use of relatively low extracting field in the vacuum region and are not affected by contamination and absorption from accelerated ions. In addition, the structures may be fabricated with current state-of-the-art technology.

Abstract: A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Abstract: The present invention provides an varactor, a method of manufacture thereof. In an exemplary embodiment, the varactor includes a semiconductor substrate and well of a first and second conductivity type, respectively. A conductive region in the well has a same conductivity type as the well but a lower resistivity than the well. At least a portion of the well is between at least two sides of the conductive region and an area delineated by an outer perimeter of a conductive layer over the well. Such varactors have a lower series resistance and therefore have an increased quality factor.

Abstract: A semiconductor device includes a plurality of barrier layers and a plurality of quantum well layers which are alternately interleaved with each other and disposed on a substrate of semiconductor material so as to form a multiple-heterojunction varactor diode. The barrier layers and quantum well layers are doped with impurities. The varactor diode includes an ohmic contact which is electrically connected to a heavily doped embedded region and a Schottky contact which is electrically connected to a depletion region of the diode. The ohmic contact and the Schottky contact enable an external voltage source to be applied to the contacts so as to provide a bias voltage to the varactor diode. A variable capacitance is produced as a result of the depletion region varying with a variation in the bias voltage. The varactor diode also provides a constant series resistance.

Abstract: A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

Abstract: A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.

Abstract: A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

Abstract: A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used.

Abstract: A multilayer circuit board having a high level of reliability in terms of electric connection against temperature changes caused by the actual operation of electronic equipment, a manufacturing process, a substrate for multilayer circuitry, and an electronic apparatus.