Abstract: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect.

Abstract: A zener diode circuit includes a semiconductor substrate having an N-doped region and a P-doped region that form a PN junction. The N-doped region and the P-doped region have areas with widths that decrease as the N-doped region and the P-doped region approach the PN junction. The zener diode circuit also includes a transistor that provides current to the zener diode, and circuitry that detects a state of the zener diode.

Abstract: A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.

Abstract: A semiconductor element includes a semiconductor layer having a first doping density, a metallization, and a contact area located between the semiconductor layer and the metallization. The contact area includes at least one first semiconductor area that has a second doping density higher than the first doping density, and at least one second semiconductor area in the semiconductor layer. The second semiconductor area is in contact with the metallization and provides lower ohmic resistance to the metallization than a direct contact between the semiconductor layer and the metallization provides or would provide.

Abstract: A semiconductor device includes a first layer having a first conductivity type, a second layer having a second conductivity type, a third layer having the second conductivity type, one or more first zones having the first conductivity type and located within the second layer, wherein each one of the one or more first zones is adjacent to the third layer, and one or more second zones having the second conductivity type and located within the second layer, wherein each one of the one or more second zones is adjacent to one or more of the one or more first zones.

Abstract: A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability.

Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Abstract: A semiconductor device has a semiconductor device chip with upper and lower terminal electrodes, and upper and lower frames bonded to the upper and lower terminal electrodes, respectively, with solder material, wherein the semiconductor device chip includes: a semiconductor layer of a first conductivity type; a diffusion layer of a second conductivity type, which is selectively formed in the semiconductor layer; a plurality of guard-ring layers of the second conductivity type, which are formed outside of the diffusion layer in the semiconductor layer; an insulating film formed on the semiconductor layer; and a field plate formed of a poly-crystalline silicon film embedded in the insulating film.

Abstract: A bi-directional transient voltage suppression (“TVS”) device (101) includes a semiconductor die (201) that has a first avalanche diode (103) in series with a first rectifier diode (104) connected cathode to cathode, electrically coupled in an anti-parallel configuration with a second avalanche diode (105) in series with a second rectifier diode (106) also connected cathode to cathode. All the diodes of the TVS device are on a single semiconductor substrate (301). The die has a low resistivity buried diffused layer (303) having a first conductivity type disposed between a semiconductor substrate (301) having the opposite conductivity type and a high resistivity epitaxial layer (305) having the first conductivity type. The buried diffused layer shunts most of a transient current away from a portion of the epitaxial layer between the first avalanche diode and the first rectifier diode, thereby reducing the clamping voltage relative to the breakdown voltage.

Abstract: A protection device for handling energy transients includes a plurality of basic unit Zener diodes connected in series to achieve a desired breakdown voltage. Each of the basic unit Zener diodes is formed in a first-type substrate. Each of the basic unit Zener diodes comprises a second-type well formed in the substrate, a second-type Zener region formed in the second-type well and a first-type+ region formed over the second-type Zener region between a first and second second-type+ region.

Abstract: A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a depletion layer expanded outward from the guard ring portions except the outermost one reaches these relay diffusion layers, and then the outer guard ring portions. The width of the distance between the guard ring portions is shorter where the relay diffusion layers are provided. For the width of the relay diffusion layers, the depletion layer reaches the outer guard ring portions with a lower voltage than the conventional structure.

Abstract: The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).

Abstract: A sequential mesa type avalanche photodiode (APD) includes a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.

Abstract: This invention provides a method or an auxiliary method to implement optimum variation lateral flux on a semiconductor surface. The method is to cover one or more thin films of high permittivity dielectric material on the semiconductor surface. The one or more films are capable of transmitting flux into or extracting flux from the semiconductor surface, or even to extract some flux from a part of the semiconductor surface and then transmit the flux to another part of the semiconductor surface. By using optimum variation lateral flux, not only can high-voltage lateral devices be made, but also an edge-termination technique for high-voltage vertical devices is provided. While the thin films can be used to prevent the occurrence of strong electric fields produced at the edges of some doped regions, these regions are used to compensate other doped regions with opposite doping and different location.

Abstract: A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.

Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.

Abstract: A plurality of connection holes 24 for connecting n+ type semiconductor region 20 of zener diodes (D1, D2) and wires 21 and 22 to each other are not arranged in the center of the n+ type semiconductor region 20, that is, in a region in which a p+ type semiconductor region 6 and the n+ type semiconductor region 20 form a junction but is arranged in the periphery which is deeper than the center in junction depth. In addition, these connection holes 24 are spaced from each other so that a pitch between the adjacent connection holes 24 is greater than a minimum pitch between connection holes of the circuit, and thereby a substrate shaving quantity is reduced when the respective connection holes 24 are formed by means of dry etching.

Abstract: A constant voltage device includes n-type and p-type doped layers. The n-type doped layer is formed by heavily doping with an n-type impurity an upper portion of a p-type silicon semiconductor substrate, in an active region defined by an isolating insulator film. The p-type doped layer is formed by doping the region under the n-type doped layer with a p-type impurity. The n-type and p-type doped layers are provided to form two layers in parallel with the substrate surface of the semiconductor substrate, whereby a pn junction formed between the n-type and p-type doped layers creates a diode structure. Impurity concentration in the p-type doped layer is established so that the impurity concentration of a portion adjacent the isolating insulator film is lower that that of the rest.

Abstract: An integrated circuit having very low parasitic current gain includes a guard ring that is used to completely surround a device, such as a power device, that induces parasitic current. The guard ring is formed in a semiconductor body layer such as an epitaxial layer and has a central guard ring of the same type conductivity as that of the body layer and additional flanking rings of the opposite type conductivity. An unbiased configuration of the guard ring based on the above structure is particularly effective in reducing the parasitic gain. The effectiveness of the guard ring, such as the high current performance, is further improved by reducing the resistance between neighboring rings using various methods.

Abstract: A semiconductor component includes a first layer and at least one adjacent semiconductor layer or metallic layer, which forms a rectifying junction with the first layer. Further semiconductor layers and metallic layers are provided for contacting the component. Insulating or semi-insulating structures are introduced into the first layer in a plane parallel to the rectifying junction. These structures are shaped like dishes with their edges bent up towards the rectifying junction. A method of producing such a semiconductor component is also provided.

Abstract: A diode (20), having first and second conductive layers (24,26), a conductive pad (28), and a distributed reverse surge guard (22), provides increased protection from reverse current surges. The surge guard (22) includes an outer loop (42) of P+-type surge guard material and an inner grid (44) of linear sections (46, 48) which form a plurality of inner loops extending inside the outer loop (42). The surge guard (22) distributes any reverse current over the area of the conductive pad (28) to provide increased protection from transient threats such as electrostatic discharge (ESD) and during electrical testing.

Abstract: A semiconductor device comprises a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type, a base layer of a second conductivity type provided in the first semiconductor layer, for defining a vertical MISFET including source regions and a gate electrode on a gate insulation film, a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer, a guard ring region of the second conductivity type provided around SBD-forming region, a first main electrode disposed above the first semiconductor layer and provided in common as both a source electrode of the MISFET and an anode of the SBD, a surface gate electrode disposed above the first semiconductor layer, and a second main electrode provided in common as a drain electrode of the MISFET and a cathode of the SBD.

Abstract: This invention provides a method or an auxiliary method to implement optimum variation lateral flux on a semiconductor surface. The method is to cover one or more thin films of high permittivity dielectric material on the semiconductor surface. The one or more films are capable of transmitting flux into or extracting flux from the semiconductor surface, or even to extract some flux from a part of the semiconductor surface and then transmit the flux to another part of the semiconductor surface. By using optimum variation lateral flux, not only can high-voltage lateral devices be made, but also an edge-termination technique for high-voltage vertical devices is provided. While the thin films can be used to prevent the occurrence of strong electric fields produced at the edges of some doped regions, these regions are used to compensate other doped regions with opposite doping and different location.

Abstract: A high voltage semiconductor device includes a drain region disposed within a semiconductor substrate. The semiconductor device further includes a field oxide layer disposed outwardly from the drain region of the semiconductor substrate. The semiconductor device also includes a floating ring structure disposed inwardly from at least a portion of the field oxide layer. In one particular embodiment, a device parameter degradation associated with the semiconductor device comprises one (1) percent or less after approximately five hundred (500) seconds of accelerated lifetime operation.

Abstract: A semiconductor device embraces an n-type first semiconductor region, defined by first and second end surfaces and a first outer surface connecting the first and second end surfaces; a p-type second semiconductor region, defined by third and fourth end surfaces and a second outer surface connecting the third and fourth end surfaces, the fourth end surface is in contact with the first end surface; an n-type third semiconductor region connected with the first semiconductor region at the second end surface; a p-type fourth semiconductor region connected with the second semiconductor region at the third end surface; and a fifth semiconductor region having inner surface in contact with the first and second outer surfaces and an impurity concentration lower than the first semiconductor region. The fifth semiconductor region surrounds the first and second semiconductor regions and is disposed between the third and fourth semiconductor regions.

Abstract: A high-voltage diode has a dopant concentration of an anode region and a cathode region optimized in terms of basic functions static blocking and conductivity. Dopant concentrations range from 1×1017 to 3×1018 dopant atoms per cm3 for the anode emitter, especially on its surface 1019 dopant atoms per cm3or more for the cathode emitter and approximately 1016 dopant atoms per cm3 for the blocking function of an anode-side zone.

Abstract: A semiconductor device includes an electronic circuit, a metal guard ring surrounding the electronic circuit, and a passivation layer covering the electronic circuit and guard ring. The passivation layer has a slot extending from the surface of the device down to the guard ring. The slot prevents cracks that may form in the passivation layer at the edges of the device from propagating to the area inside the guard ring. Locating the slot over the guard ring enables the size of the device to be reduced, and enables the guard ring to keep moisture and contaminants that enter the slot from reaching lower layers of the device.

Abstract: Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are formed in a semiconductor substrate such as silicon. Furthermore, a cathode side P layer 103 is also formed facing a cathode electrode 105 in a position on the N layer 101 that a depletion layer extended during application of a reverse bias voltage does not reach. By providing the cathode side P layer 103, a current density of a reverse current obtained during a reverse recovery operation can be increased, the sudden change of a resistance component of a diode can be prevented and the generation of a voltage oscillation can be suppressed. The cathode side P layer 103 has a diameter W of approximately 400 &mgr;m or less and a rate of an area of the cathode side P layer 103 occupying a cathode surface is kept at approximately ⅖ or less.

Abstract: The invention concerns an integrated circuit, including a substrate (SBSTR) with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point (GND), a Vcc power supply terminal, an input point (in) and an output point (out). At least one of the Vcc power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, and the overvoltage protection circuit includes means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point. The means include two or more diode elements of the Zener type connected in series. The substrate of a first conductivity type is provided with a well (WLL) of a second, opposed conductivity type formed in the substrate.

Abstract: It is an object of the present invention to provide a radio frequency module incorporating an MMIC that has a high S/N ratio while ensuring a high output.

Abstract: An MOS integrated circuit, such as an input-output buffer, exhibits improved resistance to damage from electrostatic discharge (ESD) by balancing the ESD current flow through active and inactive sections of drivers. Better balance of the ESD current flow is achieved by increasing the width and length of multi-finger channels of semiconductor material defining the gates of the drivers in the active section. Wider, longer gates of the drivers in the active section increase their ability to carry current, thereby resulting in a more symmetrical distribution of ESD current between the active and inactive sections without degrading the IC's normal performance.

Abstract: A structure of a cross guard ring along the edge of a semiconductor chip is disclosed. A first guard ring, a second guard ring and a third guard ring are formed along the edge of a semiconductor chip. Each guard ring comprises several rectangle shaped vias which are positioned along the edge of the chip structure, wherein each rectangle via is separated from an adjacent rectangle via by a gap. Further, each rectangle via of the second guard ring is positioned opposite the said gap of the first guard ring and are crossed over and have some overlay with rectangle vias of the first guard ring which are separated by the said gap as shown in FIG. 2. Similarly the third guard ring is positioned with respect to the second guard ring.

Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.

Abstract: A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor layer for impressing voltage on the active layer, and a concave portion which is cut from around the first electrode in a direction of the second semiconductor layer and the active layer and which subdivides the second semiconductor layer and the active layer to which the first electrode is connected as a region which functions as a Gunn diode. Since etching for defining a region that is to function as a Gunn diode is performed by self-alignment dry etching utilizing electrode layers formed above this region as masks, variations in characteristics are restricted.

Abstract: A pin diode includes an inner zone, a cathode zone and an anode zone. A boundary surface between the inner zone and the anode zone is at least partly curved and/or at least one floating region having the same conduction type and a higher dopant concentration than in the inner zone is provided in the inner zone. The turnoff performance in such geometrically coupled power diodes, in contrast to the turnoff performance of pin power diodes (in the Read-diode version) with spaced charge coupling, is largely temperature-independent. Hybrid diodes with optimized conducting-state and turnoff performance can be made from such FCI diodes. FCI diodes are preferably used in conjunction with switching power semiconductor elements, as voltage limiters or free running diodes.

Abstract: A field oxide surrounding an active region, an N-type doped layer formed in the active region, and an electrode formed on the field oxide in the vicinity of the active region are provided on a P-type semiconductor substrate. During the operation as a constant voltage device, a desired voltage is applied to the electrode. Then, trapping of carriers in the interface between the field oxide and the semiconductor region can be suppressed, although such trapping is ordinarily caused by a reverse breakdown phenomenon at the pn junction between the doped layer and the P-type semiconductor substrate. Accordingly, the variation in strength of the electric field between the doped layer and the semiconductor substrate can be suppressed. As a result, it is possible to suppress a variation in reverse withstand voltage, which is usually caused by a reverse breakdown voltage at a pn junction, for a semiconductor device functioning as a constant voltage device.

Abstract: An integrated circuit (10) includes a P-epi substrate (12) having therein an n-well isolation layer (13) and a p-well (14) within the n-well. The p-well includes adjacent an upper surface thereof a p+ layer (18) having several elongate parallel openings (21-23) therethrough. Each of the openings has therein a respective n− RESURF layer (26-28). Each n− RESURF layer has therethrough a respective further elongate opening (31-33), and has a uniform horizontal thickness all around that opening. Each of the openings in the RESURF layers has therein an n+ finger (36-38). The p+ layer and the n+ fingers each have a vertical thickness which is greater than the vertical thickness of the n− RESURF layers. The p+ layer serves as the anode of a zener diode, and the n+ fingers are interconnected and serve as the cathode.

Abstract: A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for providing source/drain extensions or halo doping or both.

Abstract: There is provided a semiconductor device having a novel structure in which high reliability and high field effect mobility can be simultaneously achieved. In an insulated gate transistor formed on a single crystal silicon substrate, pinning regions 105 and 106 are formed at the ends of a channel formation region 102. The pinning regions 105 and 106 suppress the expansion of a depletion layer from the drain side to prevent a short channel effect. In addition, they also serve as a path for extracting minority carriers generated as a result of impact ionization to prevent breakdown phenomena induced by carrier implantation.

Abstract: A semiconductor device which has few peripheral element malfunctions and superior performance is obtained. The semiconductor device includes a p-type buried layer on a main surface of a semiconductor substrate, an n-type cathode region provided on the p-type buried layer, and a p-type anode region in contact with the side surface of the n-type cathode region, the p-type buried layer being higher than the p-type anode region in acceptor content, and the p-type buried layer being in contact with the bottom surfaces of the anode and cathode regions.

Abstract: A semiconductor device includes a guard ring in the termination area that is formed using the same processing steps that form the active area of the device and without requiring additional masking steps or a passivation layer. The guard ring is formed in an opening in the field oxide located in the termination area and is electrically connected to a polysilicon field plate that is located atop a portion of the field oxide region. The guard ring increases the rated voltage of the device without the introduction of a passivation layer.

Abstract: The present invention is directed to an improved deep trench structure, for use in junction devices, which addresses junction breakdown voltage instabilities of the prior art. The primary, or metallurgical, junction where avalanche breakdown occurs is moved away from the surface dielectric into the bulk silicon by adding a lightly doped layer adjacent to the deep trench. A preferred embodiment suitable for isolated structures places the doped layer adjacent to the sidewalls of the deep trench. A second preferred embodiment, suitable for non-isolated structures, places the doped layer adjacent to both the floor and the sidewalls of the trench.

Abstract: A multi guard ring structure for a reach-through type semiconductor device has at least first and second guard ring regions. The first guard ring region surrounds a main region with a predetermined first spacing. The second guard ring region surrounds the first guard ring region with a predetermined second spacing. To improve the ability to withstand reverse bias voltage, the second spacing between the first and second guard ring regions is made smaller than the first spacing between the main region and the first guard ring region in order that a maximum value of an electric field strength at a junction between the first guard ring region and the drift region may be equal to or lower than 85% of a maximum value of a field strength at the main junction at the avalanche breakdown condition of the main junction.

Abstract: A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.

Abstract: A semiconductor power device (100) that includes a number of bipolar or FET power devices (116), an over-voltage clamp (118), and an edge termination structure (110) that separates the power devices (116) and the over-voltage clamp (118). The power devices (116) are formed in an interior region (100a) of a semiconductor substrate (128), while the over-voltage clamp (118) is formed in a peripheral region (100b) of the substrate. The over-voltage clamp (118) and the gate/base terminals of the power devices (116) are formed in a polysilicon layer (126) overlying the substrate (128), such that the over-voltage clamp (118) is connected between the anode and gate/base terminals of each power device (116) to provide over-voltage protection.

Abstract: A zapping diode concerned with a P-N junction diode provided in an integrated circuit, whose P-N junction is subjected to breakdown by an overvoltage to perform fine adjustment in the value of capacitance or resistance involved in the circuit. The diode has a first impurity region of a first conductivity type formed in a first conductivity type semiconductor region, a second impurity region, an interlayer insulation film formed over the semiconductor region, and a third conductor film formed on the semiconductor region between the first and second impurity region. The third conductor film, when applied by a reverse-bias voltage, controls the direction of breakdown in the P-N junction to thereby provide a consistent value of residual resistance.

Abstract: A zener diode capable of breakdown at much higher voltages than in the prior art is fabricated by providing a semiconductor substrate of a first conductivity type having an opposite conductivity type first tank disposed therein. The first tank includes relatively lower and relatively higher resistivity portions, the relatively lower doped portion isolating the relatively higher doped portion from the substrate. A first region of first conductivity type is disposed in the higher doped portion and a second region of opposite conductivity type and more highly doped than the first tank is spaced from the first region.

Abstract: A mesa-structure avalanche photodiode in which a buffer region in the surface of the mesa structure effectively eliminates the sharply-angled, heavily doped part of the cap layer that existed adjacent the lightly-doped n-type multiplication layer and p-type guard ring before the buffer region was formed. This reduces electric field strength at the ends of the planar epitaxial P-N junction and prevents edge breakdown in this junction. The lateral extent of the guard ring is defined by a window formed in a masking layer prior to regrowth of the guard ring. This guard ring structure eliminates the need to perform additional processing steps to define the lateral extent of the guard ring and passivate the periphery of the guard ring.

Abstract: In a semiconductor electron emission device for causing an avalanche breakdown by applying a reverse bias voltage to a Schottky barrier junction between a metallic material or metallic compound material and a p-type semiconductor, and externally emitting electrons from a solid-state surface, a p-type semiconductor region (first region) for causing the avalanche breakdown contacts a p-type semiconductor region (second region) for supplying carriers to the first region, and a semi-insulating region is formed around the first region.

Abstract: A large area avalanche photodiode device that has a plurality of contacts formed on a bottom side that are isolated from each other by various kinds of isolation structures. In one embodiment, a cavity is formed in one layer of the avalanche photodiode that extends to a depletion region that exists in the layer as a result of a voltage applied to the device. The plurality of contacts are formed in the cavity so that each of the contacts are positioned substantially adjacent the depletion region. In another embodiment, a plurality of contacts are formed in a cavity and an isolation structure comprised of a grid of semiconductor material is formed so as to be interposed between adjacent contacts. The isolation structure preferably forms a p-n junction with the surrounding semiconductor material and the p-n junction provides isolation between adjacent contacts.