Abstract: A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.

Abstract: A voltage-controlled switch comprises a first electrode, a second electrode, a switching junction situated between the first electrode and the second electrode, a conducting channel extending from adjacent to the origin through the switching junction and having a channel end situated near the second electrode, and a layer of dopants situated adjacent to an interface between the switching junction and the second electrode, wherein the dopants are capable of being activated to form switching centers.

Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. The device further includes at least one of dopant initiators or dopants localized at an interface between i) the first electrode and the active region, or ii) the second electrode and the active region, or iii) the active region and each of the first and second electrodes.

Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.

Abstract: A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state.

Abstract: A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming an indent, having a flange and an indent side, from a peripheral region of the active side; and forming a conformal interconnect, having an elevated segment, a slope segment, and a flange segment, over the indent.

Abstract: A conventional semiconductor device, for example, a lateral PNP transistor has a problem that it is difficult to obtain a desired current-amplification factor while maintaining a breakdown voltage characteristic without increasing the device size. In a semiconductor device, that is a lateral PNP transistor, according to the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The epitaxial layer is used as a base region. Moreover, molybdenum (Mo) is diffused in the substrate and the epitaxial layer. With this structure, the base current is adjusted, and thereby a desired current-amplification factor (hFE) of the lateral PNP transistor is achieved.

Abstract: An electrically actuated device comprises an active region (16) disposed between a first electrode (12) and a second electrode (14), a fixed dopant (24) distributed within the active region, and at least one type of mobile dopant situated near an interface between the active region and the second electrode.

Abstract: In a circuit module for a high frequency, a resistance film is formed on a side of a semiconductor circuit chip, mounted above a dielectric substrate through ground metal layers, opposite to the dielectric substrate. A distance from the ground metal layer to the resistance film is a ¼ wavelength at a predetermined frequency, and the resistance film has a sheet resistance equal to a characteristic impedance of air. A second dielectric substrate with the metal layer formed on a side opposite to the resistance film can be mounted. When being adhered to the second dielectric substrate, the resistance film has a characteristic impedance determined by a permittivity of a material of the semiconductor circuit chip. When being formed in space from the semiconductor circuit chip, the resistance film has a sheet resistance equal to a characteristic impedance of air. The thickness of the second dielectric substrate is a ¼ wavelength in a desired frequency.

Abstract: A control layer for use in a junction of a nanoscale electronic switching device is disclosed. The control layer includes a material that is chemically compatible with a connecting layer and at least one electrode in the nanoscale switching device. The control layer is adapted to control at least one of electrochemical reaction paths, electrophysical reaction paths, and combinations thereof during operation of the device.

Abstract: The invention relates to a semiconductor component comprising a buried temporarily n-doped area (9), which is effective only in the event of turn-off from the conducting to the blocking state of the semiconductor component and prevents chopping of the tail current in order thus to improve the turn-off softness. Said temporarily effective area is created by implantation of K centers (10).

Abstract: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.

Abstract: A silicon controlled rectifier structure with the symmetrical layout is provided. The N-type doped regions and the P-type doped regions are disposed with the N-well and symmetrically arranged relative to the isolation structure in-between, while the P-type buried layer is located under the N-type doped regions and the P-type doped regions and fully isolates the N-type doped regions from the N-well.

Abstract: The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. Moreover, a second copper silicide layer is sandwiched between the semiconductor layer and the source/drain.

Abstract: A semiconductor substrate of the present invention is a DSP wafer or Semi-DSP wafer (FIG. 2) having a flatness of an SFQR value ≦70 (nm) and containing boron at a concentration not lower than 5×1016 (atoms/cm3) nor higher than 2×1017 (atoms/cm3) within 95% or more of rectangular regions of 25×8 (mm2) arranged on a front face of the substrate. Specifically, a silicon crystal layer by an epitaxial growth is formed on a front face of a silicon substrate having the above substrate boron concentration.

Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).

Abstract: A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N− LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

Abstract: In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member is manufactured by interposing the microgaps between two substrates.

Abstract: The photoconductive switch comprises a laser that generates light having a first wavelength and a photoconductive switch element arranged to receive the light generated by the laser as incident light. The photoconductive switch element includes a photoconductive layer and a wavelength conversion element. The photoconductive layer has a low absorptivity at the first wavelength. The wavelength conversion element converts the incident light into activating light having a second wavelength at which the photoconductive layer has a greater absorptivity than at the first wavelength. The wavelength conversion element is integral with the photoconductive layer, or is in contact with the photoconductive layer, or is both integral with and in contact with the photoconductive layer.

Abstract: An integrated circuit includes a substrate and a degenerated transistor. The degenerated transistor includes a control terminal formed on the substrate, a channel formed in the substrate beneath the first control terminal, first and second heavily-doped regions embedded in the substrate on opposing sides of the channel, first and second output contacts positioned on the first and second heavily-doped regions, respectively, and a lightly-doped region extending between the first heavily-doped region and the channel. The lightly-doped region has a length that is selected such that the first output contact is spaced from a respective edge of the control terminal by a distance that is at least twice as great as a minimum distance defined for the technology in which the integrated circuit is fabricated and the lightly-doped region has a desired resistance in series with the first output contact.

Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate (2) in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate (2); step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate (2) by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate (2), the dopant from said solids-based dopant source diffusing directly into said substrate (2) to form a first diffusion region (12) and, at the time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate (2) to form a second diffusion region (15) in at least some areas of said substrate (2) not covered by said pattern; and step 3) forming a metal contact pattern (20) substantially in alignment with said first diffusion region (12) with

Abstract: Useful to inhibit reverse engineering, semiconductor devices and methods therefore include formation of two active regions over a substrate region in the semiconductor device. According to an example embodiment, a dopable link, or region, between two heavily doped regions can be doped to achieve a first polarity type, with the two heavily doped regions of the opposite polarity. If dictated by design requirements, the dopable region is adapted to conductively link the two heavily doped regions. A dielectric is formed over the dopable region and extends over a portion of each of the two heavily doped regions to inhibit silicide formation over edges of the dopable region. In connection with a salicide process, a silicide is then formed adjacent the dielectric and formed over another portion of the two heavily doped regions.

Abstract: A combination of an IGBT and an antiparallel-connected freewheeling diode in which the IGBT die size is greater than about twice the diode die size. Preferably the diode die size is about 10%-25% of that of the IGBT. The respective die sizes of an IGBT and an antiparallel connected freewheeling diode may be adjusted by the steps of: determining respective initial die sizes for the IGBT and the diode; increasing the IGBT die size from the initial value; and reducing said diode die size from the initial value. The IGBT die size is increased sufficiently to reduce current density, conduction losses and switching losses in the IGBT. The diode die size is reduced sufficiently to reduce the reverse recovery charge of the diode so as to further reduce switching losses in the IGBT, to a minimum size which is sufficient to carry the antiparallel current without substantial overheating.

Abstract: Useful to inhibit reverse engineering, semiconductor devices and methods therefor include formation of two active regions over a substrate region in the semiconductor device. According to an example embodiment, a dopable link, or region, between two heavily doped regions can be doped to achieve a first polarity type, with the two heavily doped regions of the opposite polarity. If dictated by design requirements, the dopable region is adapted to conductively link the two heavily doped regions. A dielectric is formed over the dopable region and extends over a portion of each of the two heavily doped regions to inhibit silicide formation over edges of the dopable region. In connection with a salicide process, a silicide is then formed adjacent the dielectric and formed over another portion of the two heavily doped regions.

Abstract: A semiconductor substrate is provided which maintains its gettering capabilities throughout the manufacturing process of a semiconductor device and which prevents previously gettered contaminating impurities from being released again into an operating region of a semiconductor device. The semiconductor substrate includes a silicon substrate, a polysilicon layer, and a high density boron layer. The silicon substrate has a first main surface and a second main surface opposed to the first main surface, and the silicon substrate is used to form a semiconductor device at least indirectly on the first main surface. The polysilicon film is formed at least indirectly on the second main surface, and the high density boron layer is disposed between the silicon substrate and the polysilicon film. Also a ratio of a highest boron density value in the high density boron layer to a lowest boron density value in the silicon substrate is greater than or equal to approximately 100.

Abstract: A photoconductive switch, having at least a part of a first layer doped with dopants providing substantially no free charge carriers for charge transport between the electrodes at the normal operation temperature of the switch, has the nature of the doping, i.e., concentration, type (n or p). The dopants, varied from the first side to an opposite, second side of the first layer for co-operating with the intensity distribution of the light emitted by an illumination source, strikes the first side versus energy so as to obtain a substantially even creation of free charge carriers throughout the depth of the first layer from the first to the second side when illuminated by the illumination source.

Abstract: Channel-hot-carrier reliability can be improved by deuterium sintering. However, the benefits obtained by deuterium sintering can be greatly reduced or destroyed by thermal processing steps which break Si--H and Si--D bonds. A solution is to increase the deuterium concentration near the interface to avoid subsequent depletion of deuterium due to diffusion. By using a rapid quench of a sintered wafer, the deuterium concentration near the interface is increased, because the rapid quench impedes the ability of the deuterium to diffuse away from the gate oxide interface.

Abstract: Method of producing a bromine compound having an aliphatic unsaturated bond which includes reacting a compound having an aliphatic unsaturated bond represented by the following general formula (1) with bromine:R.sup.1 --O--Ar.sup.1 --Y--Ar.sup.2 --O--R.sup.2 (1)to produce a bromine compound represented by the following formula (2):R.sup.3 --O--Ar.sup.1 --Y--Ar.sup.2 --O--R.sup.4 (2)wherein Ar.sup.1, Ar.sup.2 and Y are the same as defined in the above general formula (1) , and R.sup.3 and R.sup.4 are groups obtained by saturating the unsaturated groups of R.sup.1 and R.sup.2 in the above general formula (1) with bromine, respectively.The reaction is carried out in the presence of a solvent which is inactive in the reaction, and a substantial amount of the heat of reaction is removed from a reaction system by the vaporization of the solvent or bromine. A high-purity bromine compound in high yield which is useful as flame retardant, can be obtained.

Abstract: A photoconductive switching device is disclosed that has an enhanced speed of response so that its closed (low) and open (high) resistive states are obtained in response to optical illumination in the less than nanosecond regime. The enhanced speed of response is achieved by neutron irradiation of a material preferably comprising GaAs:Si:Cu. An application of the improved photoconductive switching devices is disclosed which allows the realization of a high-power, frequency-agile RF source topology.

Abstract: A first type of superconductive photoelectric device is provided by a superconductive thin film located between two electrodes. The superconductive thin film is one which has a photo-conductive effect and converts from a normally conducting state to a superconductive state in response to light irradiation. The superconductive thin film is preferably formed of a compound semiconductor of Pb chalcogenide added with Pb and/or In added beyond the stoicheometry of the compound semiconductor, such as Pb.sub.1-x Sn.sub.x Te+In, so as to generate precipitations of Pb. A second type of superconductive photoelectric device is provided by a photo-conductive material formed of Pb.sub.1-x Sb.sub.x Te filled in a gap between two superconductive electrodes, where the gap width is shorter than 500 times of a coherence length.

Abstract: The disclosed improved GaAs majority carrier rectifying barrier diodes comprise a p.sup.+ region between semiconductor regions that comprise n-doped material. Exemplary structures are n.sup.+ -i-p.sup.+ -i-n.sup.+ and n.sup.+ -n-p.sup.+ -n-n.sup.+. The improvement comprises use of carbon as the p-dopant and results in readily manufacturable reliable devices.

Abstract: An EEPROM cell is implemented by a field effect transistor comprising a channel layer of an intentionally undoped gallium arsenide, a carrier supplying layer formed on the channel layer and of a heavily doped n-type aluminum gallium arsenide having deep energy level, and a gate electrode formed on the carrier supplying layer, in which the deep energy level causes a current-voltage collapse phenomenon to take place due to trapping hot electrons injected from the channel layer to the carrier supplying layer in the presence of a stress voltage of about 1.2 volts between the source and drain for minimizing channel conductivity and in which the stress voltage of about 3 volts ionizes the deep energy level so as to allow recovering from the current-voltage collapse phenomenon, thereby providing the low and high channel conductivities to two logic levels.