With Peripheral Feature Due To Separation Of Smaller Semiconductor Chip From Larger Wafer (e.g., Scribe Region, Or Means To Prevent Edge Effects Such As Leakage Current At Peripheral Chip Separation Area) Patents (Class 257/620)
-
Patent number: 9165897Abstract: A semiconductor package includes one or more semiconductor stack structures mounted on a package board. The semiconductor stack structures include sequentially stacked first to fourth semiconductor devices. Each of the first to fourth semiconductor devices includes a first unit semiconductor chip and a second unit semiconductor chip. The first unit semiconductor chip and the second unit semiconductor chip are unitary. A method for fabricating the semiconductor package includes forming pairs of unit semiconductor chips on a wafer, forming a scribe lane between the pairs of unit semiconductor chips, separating the pairs of unit semiconductor chips into semiconductor devices, each of the semiconductor devices having a corresponding one pair of unit semiconductor chips.Type: GrantFiled: September 16, 2013Date of Patent: October 20, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: In Lee
-
Patent number: 9166029Abstract: A method for manufacturing a semiconductor device includes: forming, in element regions of a semiconductor wafer, electrodes and a insulator on peripheral part of the electrodes so that a height of the insulator is higher than that of the electrodes; forming, on the front face of the semiconductor wafer, a groove for surrounding a periphery of the electrodes with the insulator being sandwiched between the electrodes and the groove, the groove being formed so that a height of the groove is lower than that of the insulator and the groove extends to an outer circumferential edge of the semiconductor wafer; bonding adhesives onto the electrodes in the element regions so that a height of the adhesives is higher than that of the insulator, and bonding, onto the adhesives, a base material for covering the front face of the semiconductor wafer; and processing a rear face of the semiconductor wafer.Type: GrantFiled: January 9, 2014Date of Patent: October 20, 2015Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Toru Onishi
-
Patent number: 9142588Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.Type: GrantFiled: October 28, 2014Date of Patent: September 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-I Cheng, Chih-Mu Huang, Pin Chia Su, Chi-Cherng Jeng, Volume Chien, Chih-Kang Chao
-
Patent number: 9123708Abstract: The semiconductor chip package comprises a carrier, a semiconductor chip comprising a first main face and a second main face opposite to the first main face, chip contact elements disposed on one or more of the first or second main faces of the semiconductor chip, an encapsulation layer covering the first main face of the semiconductor chip, the encapsulation layer comprising a first main face facing the carrier and a second main face remote from the carrier, first contact elements disposed on the second main face of the encapsulation layer, each one of the first contact elements being connected to one of the chip contact elements, and second contact elements disposed on the first main face of the encapsulation layer, each one of the second contact elements being connected to one of the chip contact elements.Type: GrantFiled: March 1, 2013Date of Patent: September 1, 2015Assignee: Infineon Technologies Austria AGInventors: Khalil Hosseini, Thomas Wowra, Joachim Mahler, Ralf Wombacher
-
Patent number: 9099549Abstract: A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus.Type: GrantFiled: December 2, 2013Date of Patent: August 4, 2015Assignee: VIA TECHNOLOGIES, INC.Inventor: Darius D. Gaskins
-
Patent number: 9086328Abstract: An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress.Type: GrantFiled: July 9, 2012Date of Patent: July 21, 2015Assignee: INFINEON TECHNOLOGIES AGInventor: Rolf-Peter Vollertsen
-
Patent number: 9087891Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.Type: GrantFiled: September 14, 2012Date of Patent: July 21, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazutaka Yoshizawa, Taiji Ema, Takuya Moriki
-
Patent number: 9076799Abstract: A solution for indexing electronic devices includes corresponding electronic device including a die integrating an electronic circuit, the die having at least one index including a reference defining an ordered alignment of a plurality of locations on the die and a marker for defining a value of the index according to an arrangement of the marker with respect to the reference. In one embodiment, the marker includes a plurality of markers each one arranged at a selected one of the locations, the selected location of the marker defining a value of a digit associated with a corresponding power of a base higher than 2 within a number in a positional notation in the base representing the value of the index.Type: GrantFiled: October 8, 2010Date of Patent: July 7, 2015Assignee: STMicroelectronics S.r.l.Inventors: Emanuele Brenna, Antonio Di Franco
-
Patent number: 9075103Abstract: Provided is a test structure for wafer acceptance test (WAT). The test structure includes a row of a plurality of first pads electrically connecting to each other, a second pad, a third pad, a first peripheral metal line, and a second peripheral metal line. The second pad is disposed in the vicinity of a first end of the row, wherein the second pad is electrically disconnected to the first pads. The third pad is disposed in the vicinity of a second end of the row, wherein the third pad is electrically disconnected to the first pads. The first peripheral metal line is disposed at a first side of the row and electrically connected to the second pad. The second peripheral metal line is disposed at a second side of the row and electrically connected to the third pad.Type: GrantFiled: October 5, 2012Date of Patent: July 7, 2015Assignee: United Microelectronics Corp.Inventors: Qiong Wu, Chien-Ming Lan
-
Patent number: 9059191Abstract: A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the sides of the IC chip. Each corner crackstop includes a plurality of layers, formed on a top surface of a silicon layer of the IC chip, within a perimeter boundary region that comprises a triangular area, in which a right angle is disposed on a bisector of the corner, equilateral sides of the triangle are parallel to sides of the IC chip, and the right angle is proximate to the corner relative to a hypotenuse of the triangle. The plurality of layers of the corner crackstop include crackstop elements, each comprising a metal cap centered over a via bar, in which the plurality of layers of the corner crackstop is chamfered to deflect crack ingress forces by each corner crackstop.Type: GrantFiled: October 19, 2011Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, David B. Stone
-
Patent number: 9059110Abstract: A method of reducing contamination of contact pads in a metallization system of a semiconductor device. Fluorine contamination of contact pads in a semiconductor device can be reduced by appropriately covering the sidewall portions of a metallization system in the scribe lane in order to significantly reduce or suppress the out diffusion of fluorine species, which may react with the exposed surface areas of the contact pads. The quality of the bond contacts is enhanced, possibly without requiring any modifications in terms of design rules and electrical specifications.Type: GrantFiled: September 4, 2009Date of Patent: June 16, 2015Assignee: X-Fab Semiconductor Foundries AGInventors: Hyung Sun Yook, Tsui Ping Chu, Poh Ching Sim
-
Patent number: 9054114Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.Type: GrantFiled: May 29, 2014Date of Patent: June 9, 2015Assignee: XINTEC INC.Inventors: Hung-Jen Lee, Shu-Ming Chang, Chen-Han Chiang, Tsang-Yu Liu, Yen-Shih Ho
-
Patent number: 9041162Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.Type: GrantFiled: February 24, 2014Date of Patent: May 26, 2015Assignee: Infineon Technologies AGInventors: Giuseppe Miccoli, Bhaskaran Jayachandran, Friedrich Steffen, Alfred Vater
-
Patent number: 9041161Abstract: There is provided a semiconductor device including a semiconductor layer, a protective layer including a transparent material, and a transparent resin layer that seals a gap between the semiconductor layer and the protective layer. A chip prevention member with a higher Young's modulus than the transparent resin layer is formed to come into contact with the semiconductor layer in a dicing portion of a layer structure before fragmentation, and dicing is performed in the dicing portion for the fragmentation.Type: GrantFiled: July 18, 2013Date of Patent: May 26, 2015Assignee: Sony CorporationInventors: Taizo Takachi, Satoru Wakiyama
-
Patent number: 9041160Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.Type: GrantFiled: June 18, 2014Date of Patent: May 26, 2015Assignee: Rohm Co., Ltd.Inventors: Mitsuru Okazaki, Youichi Kajiwara, Naoki Takahashi, Akira Shimizu
-
Publication number: 20150137322Abstract: A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets. Each wafer section has at least two semiconductor die. The wafer sections are mounted over a temporary carrier in a grid pattern to reserve an interconnect area between the wafer sections. An encapsulant is deposited over the wafer sections and interconnect area. A conductive pillar can be formed in the encapsulant over the interconnect area. An interconnect structure is formed over the wafer sections and encapsulant in the interconnect area. The wafer sections and interconnect area are singulated to separate the semiconductor die each with a portion of the interconnect area. A heat sink or shielding layer can be formed over the wafer sections.Type: ApplicationFiled: December 10, 2014Publication date: May 21, 2015Applicant: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Yaojian Lin
-
Publication number: 20150130028Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.Type: ApplicationFiled: November 13, 2014Publication date: May 14, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yusaku ASANO, Kazuhito Higuchi, Taizo Tomioka, Tomohiro Iguchi
-
Patent number: 9029987Abstract: While reliably cutting an object to be processed, the strength of the resulting chips is improved. An object to be processed 1 is irradiated with laser light L, so as to form modified regions 17, 27, 37, 47 extending along lines to cut 5 and aligning in the thickness direction in the object 1. Here, modified regions 17 are formed such that modified region formed parts 17a and modified region unformed parts 17b alternate along the lines, and modified regions 47 are formed such that modified region formed parts 47a and modified region unformed parts 47b alternate along the lines. This can inhibit formed modified regions 7 from lowering the strengths on the rear face 21 side and front face 3 side of chips obtained by cutting. On the other hand, modified regions 27, 37 located between the modified regions 17, 47 are formed continuously from one end side of the lines 5 to the other end side thereof, whereby the cuttability of the object 1 can be secured reliably.Type: GrantFiled: June 16, 2014Date of Patent: May 12, 2015Assignee: Hamamatsu Photonics K.K.Inventors: Aiko Nakagawa, Takeshi Sakamoto
-
Publication number: 20150115411Abstract: A method of producing a semiconductor device includes forming an insulating film on a substrate on which a semiconductor layer is formed; removing a part of the insulating film by etching to form an opening in the insulating film; supplying steam with a temperature greater than or equal to 200° C. and less than or equal to 600° C. to the opening formed in the insulating film; after supplying the steam, applying a solution including a silicon compound to a side surface or the insulating film defining the opening; and forming a hydrophobic film on the side surface of the insulating film defining the opening by polymerizing the silicon compound.Type: ApplicationFiled: October 14, 2014Publication date: April 30, 2015Applicant: FUJITSU LIMITEDInventors: Shirou OZAKI, NAOYA OKAMOTO
-
Patent number: 9018737Abstract: In accordance with one embodiment, an apparatus is disclosed that comprises a submount operable to integrate with a laser as a laser submount assembly; a predetermined portion of the submount configured to bond with the laser; a bonding pad positioned on the predetermined portion of the submount for integrating the laser with the submount.Type: GrantFiled: March 6, 2013Date of Patent: April 28, 2015Assignee: Seagate Technology LLCInventors: Lijuan Zhong, Edward Charles Gage
-
Publication number: 20150108612Abstract: There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.Type: ApplicationFiled: December 23, 2014Publication date: April 23, 2015Applicant: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Hiroyuki NUMAGUCHI
-
Publication number: 20150108613Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: ApplicationFiled: December 23, 2014Publication date: April 23, 2015Applicant: Renesas Electronics CorporationInventors: Takeshi FURUSAWA, Noriko MIURA, Kinya GOTO, Masazumi MATSUURA
-
Publication number: 20150108611Abstract: In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer.Type: ApplicationFiled: September 20, 2014Publication date: April 23, 2015Inventors: Yasuhiro KUMAGAI, Masami KOKETSU
-
Publication number: 20150102467Abstract: Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape.Type: ApplicationFiled: December 18, 2014Publication date: April 16, 2015Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Saravjeet Singh, Todd Egan, Ajay Kumar, Seshadri Ramaswami
-
Publication number: 20150097272Abstract: A semiconductor device includes a carrier, several dies disposed on a surface of the carrier and several scribing lines defined on the surface of the carrier. The scribing lines include several continuous lines along a first direction and several discontinuous lines along a second direction. Further, a method of dies singulation includes providing a carrier, disposing several dies on a surface of the carrier according to several scribing lines including several continuous lines along a first direction and several discontinuous lines along a second direction, cutting the carrier according to the continuous lines along the first direction, and cutting the carrier according to the discontinuous lines along the second direction.Type: ApplicationFiled: October 9, 2013Publication date: April 9, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: BOR-PING JANG, CHIEN LING HWANG, HSIN-HUNG LIAO, YEONG-JYH LIN
-
Publication number: 20150097271Abstract: A self-healing crack stop structure and methods of manufacture are disclosed herein. The structure comprises a crack stop structure formed in one or more dielectric layers and surrounding an active region of an integrated circuit chip. The crack stop comprises self healing material which, upon propagation of a crack, is structured to seal the crack and prevent further propagation of the crack.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen P. Ayotte, Alissa R. Cote, Kendra A. Lyons, John C. Malinowski, Benjamin J. Pierce
-
Patent number: 9000454Abstract: An electro-optic device and a method for manufacturing the same. The method includes forming a bottom electrode on a substrate, forming a first insulation film crossing over the bottom electrode, forming an organic film on the substrate, forming a top electrode film on the organic film, and forming a top electrode that crosses the bottom electrode by laser-scribing the top electrode film. Herein, forming the top electrode by laser-scribing may position a bottom edge of the top electrode along an upper side of the first insulation film. Therefore, processing required for separately forming the top electrodes may be reduced, thereby simplifying manufacturing processes and saving manufacturing cost. Furthermore, since the insulation film is formed under the top electrode edge, leakage current and device malfunction caused by deformation of the top electrode can be prevented, even though the top electrode edge is damaged during laser-scribing. Thus, electro-optic device reliability can be improved.Type: GrantFiled: February 8, 2013Date of Patent: April 7, 2015Assignee: Jusung Engineering Co., Ltd.Inventors: Hyung Sup Lee, Chi Wook Yu, Sung Hui Lee
-
Publication number: 20150091138Abstract: A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window.Type: ApplicationFiled: December 10, 2014Publication date: April 2, 2015Applicant: Spansion LLCInventor: Fei WANG
-
Patent number: 8994148Abstract: A semiconductor die includes a semiconductor substrate having an edge region surrounding an active region, the active region containing devices of an integrated circuit. The semiconductor die further includes interconnect wiring over the active region in an interlayer dielectric and electrically connected to the devices in the active region, and ancillary wiring over the edge region in the interlayer dielectric and isolated from the interconnect wiring and the devices in the active device region. The interlayer dielectric is passivated, and bond pads are provided over the interconnect wiring and electrically connected to the interconnect wiring through openings in the passivation over the active region. Additional bond pads are provided over the ancillary wiring and are electrically connected to the interconnect wiring through additional openings in the passivation over the active region.Type: GrantFiled: February 19, 2013Date of Patent: March 31, 2015Assignee: Infineon Technologies AGInventors: Achim Gratz, Scott David Wallace, Tobias Jacobs
-
Publication number: 20150084164Abstract: The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.Type: ApplicationFiled: December 4, 2014Publication date: March 26, 2015Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kazuo TOMITA
-
Patent number: 8987057Abstract: Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.Type: GrantFiled: September 9, 2013Date of Patent: March 24, 2015Assignee: NXP B.V.Inventors: Leonardus Antonius Elisabeth Van Gemert, Tonny Kamphuis, Hartmut Buenning, Christian Zenz
-
Patent number: 8987867Abstract: A wafer includes a first die, a second die, and a scribe lane located between the first die and the second die. The scribe lane includes a first doped silicon region, and does not directly contact the first die and the second die.Type: GrantFiled: November 13, 2013Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hyun Lee, Jong Hyoung Lim
-
Publication number: 20150076665Abstract: A conductive structure includes a wafer having a scribe line defined thereon, at least a first wiring layer formed in the scribe line, and at least a via layer disposed in the scribe line and under the wiring layer. The first wiring layer includes a main pattern and the via layer includes a closed frame pattern corresponding to the main pattern of the first wiring layer.Type: ApplicationFiled: September 18, 2013Publication date: March 19, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jian-Bin Shiu, Min-Ching Chen
-
Publication number: 20150069578Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.Type: ApplicationFiled: March 11, 2014Publication date: March 12, 2015Applicant: NXP B.V.Inventors: Hartmut BUENNING, Sascha MOELLER, Guido ALBERMANN, Martin LAPKE, Thomas ROHLEDER
-
Publication number: 20150069577Abstract: A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Applicant: Xilinx, Inc.Inventors: Michael J. Hart, James Karp
-
Publication number: 20150061079Abstract: Disclosed herein is a method for dicing a wafer, the method comprising forming a molding compound layer over each of one or more dies disposed on a wafer, the one or more dies separated by scribe lines, the molding compound layer having gaps over the respective scribe lines. The wafer is separated into individual dies along the gaps of the molding compound in the scribe lines. Separating the wafer into individual dies comprises cutting at least a portion of the substrate with a laser. Forming the molding compound layer comprises applying a stencil over the one or more dies and using the stencil to form the molding compound layer.Type: ApplicationFiled: August 27, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ju Chen, Hsia-Wei Chen
-
Publication number: 20150061080Abstract: A guard ring structure of a semiconductor apparatus includes a base wiring layer located above a semiconductor substrate, a first guard ring configured as a wiring stacked structure of two or more layers adjacent to the side of the device forming region above the base wiring layer, and a second guard ring configured to be stacked with the same number of layers as the first guard ring and separated from the first guard ring, the second guard ring formed adjacent to the side of a scribe lane above the base wiring layer.Type: ApplicationFiled: December 9, 2013Publication date: March 5, 2015Applicant: SK hynix Inc.Inventor: Sang Bum LEE
-
Publication number: 20150061081Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.Type: ApplicationFiled: November 10, 2014Publication date: March 5, 2015Inventors: Jeffrey Alan WEST, Thomas D. BONIFIELD, Basab CHATTERJEE
-
Patent number: 8970006Abstract: An embodiment of a die comprising: a semiconductor body including a front side, a back side, and a lateral surface; an electronic device, formed in said semiconductor body and including an active area facing the front side; a vertical conductive connection, extending through the semiconductor body and defining a conductive path between the front side and the back side of the semiconductor body; and a conductive contact, defining a conductive path on the front side of the semiconductor body, between the active area and the vertical conductive connection, wherein the vertical conductive connection is formed on the lateral surface of the die, outside the active area.Type: GrantFiled: June 15, 2011Date of Patent: March 3, 2015Assignee: STMicroelectronics S.R.L.Inventor: Crocifisso Marco Antonio Renna
-
Patent number: 8970007Abstract: A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.Type: GrantFiled: January 8, 2013Date of Patent: March 3, 2015Assignee: Fujitsu Semiconductor LimitedInventor: Hajime Wada
-
Patent number: 8970008Abstract: A wafer has a number of IC areas and a kerf area arranged between the IC areas. The kerf area has a dicing area, a crack stop structure arranged between an IC area and a dicing area, and a trench arranged between the crack stop structure and the dicing area. The crack stop structure includes an extended layer extending beyond the crack stop structure towards the dicing area.Type: GrantFiled: March 14, 2013Date of Patent: March 3, 2015Assignee: Infineon Technologies AGInventors: Achim Gratz, Thimo Schindelar
-
Patent number: 8970009Abstract: To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.Type: GrantFiled: February 7, 2014Date of Patent: March 3, 2015Assignee: Renesas Electronics CorporationInventor: Yasushi Ishii
-
Patent number: 8963291Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: May 20, 2011Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
-
Patent number: 8956955Abstract: A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.Type: GrantFiled: September 12, 2012Date of Patent: February 17, 2015Assignee: Renesas Electronics CorporationInventors: Shoetsu Kogawa, Satoru Nakayama, Seigo Kamata, Shigemitsu Seito
-
Patent number: 8957503Abstract: A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer.Type: GrantFiled: December 9, 2013Date of Patent: February 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ying Yang, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
-
Publication number: 20150040983Abstract: The present invention relates to a method for acidic surface etching of a silicon wafer, such as those used for solar cells, comprising contacting at least one surface of a silicon wafer as cut with an acidic etching agent, provided that the wafer is, prior to the acidic etching, not subjected to an alkaline etching step or process. Further, the present invention is directed to Si wafer, photovoltaic cells, PERC photovoltaic cells and solar modules produced according to the method of the present invention.Type: ApplicationFiled: August 7, 2013Publication date: February 12, 2015Applicant: SolarWorld Industries America, Inc.Inventor: Konstantin Holdermann
-
Patent number: 8952497Abstract: A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips.Type: GrantFiled: September 14, 2012Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: U-Ting Chen, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Jeng-Shyan Lin, Shuang-Ji Tsai
-
Patent number: 8952462Abstract: The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.Type: GrantFiled: February 5, 2010Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Hao Chen, Da-Yuan Lee, Kuang-Yuan Hsu
-
Publication number: 20150035125Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.Type: ApplicationFiled: October 20, 2014Publication date: February 5, 2015Inventors: Kazutaka Yoshizawa, Taiji Ema, Takuya Moriki
-
Patent number: 8946868Abstract: A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die.Type: GrantFiled: September 30, 2009Date of Patent: February 3, 2015Assignee: Silicon Laboratories Inc.Inventors: Ka Y. Leung, Jean-Luc Nauleau