Abstract: A semiconductor element capable of reducing noises of a circuit propagating to another circuit through a seal ring is provided. A semiconductor element includes, on a surface of a semiconductor substrate: a plurality of circuits; a ring-shaped seal ring surrounding the plurality of circuits; and wiring connecting between the seal ring and an external low-impedance node.

Abstract: Various heat-sinked components and methods of making heat-sinked components are disclosed where diamond in thermal contact with one or more heat-generating components are capable of dissipating heat, thereby providing thermally-regulated components. Thermally conductive diamond is provided in patterns capable of providing efficient and maximum heat transfer away from components that may be susceptible to damage by elevated temperatures. The devices and methods are used to cool flexible electronics, integrated circuits and other complex electronics that tend to generate significant heat. Also provided are methods of making printable diamond patterns that can be used in a range of devices and device components.

Abstract: Provided is a highly efficient silicon-based light emitting diode (LED) including a Distributed Bragg Reflector (DBR), an n-type doping layer, and a p-type substrate structure. The silicon-based LED includes: a substrate having a p-type mesa substrate structure; an active layer that is formed on the substrate and has a first surface and a second surface opposite the first surface; a first reflective layer facing the first surface of the active layer; a second reflective layer that is located on either side of the p-type substrate structure and faces the second surface of the active layer; an n-type doping layer sandwiched between the active layer and the first reflective layer; a first electrode electrically connected to the n-type doping layer; and a second electrode electrically connected to the p-type substrate structure.

Abstract: An apparatus including an interface having a number of nanostructures is described. The apparatus comprises heat source, a thermal management device, and an interface disposed between the thermal management device and the heat source. The interface a substrate has a number of nanostructures to facilitate heat transfer and adhesion between the heat source and the thermal management device.

Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

Abstract: A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.

Abstract: A semiconductor device includes a semiconductor structure having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall in openings of a dielectric layer. The first and second charge storage structures are electrically isolated from each other and from the semiconductor structure. A control electrode is formed adjacent to the first sidewall. In another embodiment, third and fourth charge storage structures may be formed adjacent to a second sidewall of the semiconductor structure in openings of a dielectric layer.

Abstract: A radio frequency arrangement is disclosed, having a first semiconductor body with an integrated circuit formed therein and also with first and second terminal locations. A second semiconductor body with a charge store integrated therein and with a first and second contact locations is arranged with its contact locations mutually facing the terminal locations of the first semiconductor body. The first terminal and the first contact location and also the second terminal and the second contact location are coupled to one another in order thus to form an integrated circuit and also a charge store for supplying the integrated circuit. Realizing the integrated circuit and the charge store separately enables a simple and cost-effective manufacturing procedure for the individual components.

Abstract: Embodiments of a composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a matrix comprised of a metal or a metal oxide. The composite carbon nanotube structures may be used as a thermal interface device in a packaged integrated circuit device.

Abstract: The present invention is achieved with the object of providing an illumination system formed of an LED light emitting body and a socket which can appropriately release heat from LED chips. This object is achieved in the following manner. A heat conducting layer 12 made of diamond is provided on a substrate 11, and on top of this, a conductive layer 13 having a predetermined pattern is formed. LED chips 16 are mounted in predetermined positions on the conductive layer 13. Terminals of the conductive layer 13 and electrodes of the LED chips 16 are connected to each other. A connector part 14 for the connection to a socket is provided in an end portion of the substrate 11. The heat conducting layer 12 on the connector part 14 makes thermal contact with the heat conducting layer provided on the inner surface of the opening of the socket. A current is supplied to respective LED chips 16 through the conductive layer 13 from the socket, and respective LED chips 16 emit light.

Abstract: A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.

Abstract: An LED package includes a datum reference feature that is external to the insulating body of the LED package and has a known, fixed relationship to the heat sink. The LED die is mounted to the heat sink such that the LED die has a fixed relationship to the heat sink. Accordingly, the reference datum feature provides a frame of reference to the position of the LED die within the LED package. The reference datum feature may be mounted to the heat sink or integrally formed from the heat sink. A pick-and-place head holds the LED package by engaging the datum reference feature, e.g., with an alignment pin. In addition, the LED package may include a lead that extends laterally into the insulating body, and extends towards the LED die to reduce the vertical distance between the lead and the LED die.

Abstract: A solder is deposited on the backside of a wafer. The wafer can be pre-deposited with a barrier layer such as a titanium base and other materials. Deposition is carried out by electroplating, electroless plating, chemical vapor deposition, and physical vapor deposition. The solder-deposited die is bonded with a heat spreader that did not require a pre-deposited solder.

Abstract: A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gate and a gate dielectric layer disposed between the gate and the substrate. The spacer is disposed on the sidewall of the gate structure. The source/drain region is disposed in the substrate on two sides of the spacer. The barrier layer is disposed around the source/drain region. The source/drain region and the barrier layer are fabricated using an identical material. However, the doping concentration of the source/drain region is larger than the doping concentration of the barrier layer.

Abstract: A modular heat sink decoupling capacitor array includes a plurality of modules, each defining parallel distributed decoupling plates, and each module forming a heat sink fi. Each module includes multiple spaced apart contacts for providing low inductance connections with an associated device. A power distribution interposer module is attached to a heat sink surface of the modular decoupling capacitor. The interposer module is used for implementing power delivery without using valuable ball grid array (BGA) connections and printed circuit board (PCB) layers.

Abstract: There is provided a small-size electronic heat pump device which is low in power consumption and which secures a vacuum gap without use of an additional circuit. The electronic heat pump device includes an emitter 1 and a collector 2. An electrically and thermally insulative spacer section 5 for keeping a space, i.e. vacuum gap G between an emitter electrode 11 and a collector electrode 21 constant is integrally formed in a semiconductor substrate 20 of the collector 2, which makes it possible to maintain the vacuum gap to be a specified space while a back flow of heat is prevented in a simple structure with a reduced number of component parts.

Abstract: A semiconductor package with heat spreader is disclosed. In one embodiment, the semiconductor package comprises a device carrier having a plurality of contact areas and a semiconductor die having a plurality of die pads of an active surface, the semiconductor die being mounted on the device carrier. Connection means to electrically connect the die pads to the contact areas and a heat spreading means mounted on the active surface of the die are provided. The heat spreading means includes an upper plate and a foot ring which protrudes from a bottom surface of the upper plate and which is positioned between the die pads on the active surface such that a cavity is formed between the heat spreading means and the active surface. The cavity is filled with an adhering means interconnecting the heat spreading means and the active surface.

Abstract: A packaged semiconductor chip including the chip, and a package element such as a heat sink is made by connecting flexible leads between contacts on the chip and terminals on a dielectric element such as a sheet or plate and moving the sheet or plate away from the chip, and injecting a liquid material to form a compliant layer filling the space between the package element and the dielectric element, and surrounding the leads. The dielectric element and package element extend outwardly beyond the edges of the chip, and physically protect the chip. The assembly may be handled and mounted by conventional surface mounting techniques. The assembly may include additional circuit elements such as capacitors used in conjunction with the chip.

Abstract: A system of mold locks (28, 30) is formed on a heatsink (2) of a packaged semiconductor to prevent/mitigate delamination. The mold locks (4, 12) anchor a plastic mold compound (34) that forms the protective cover for the packaged semiconductor die. The mold locks (4, 12) are miniaturized to allow the positioning of them within the flag portion of the heatsink (2) and leadframe (24) such that a semiconductor die can be anchored above the mold locks (4, 12) formed within the flag portion of the heatsink/lead frame (2, 24). The miniaturized size of the said moldlocks (4, 12 do not detract from the purpose of the die attach solder (36).

Abstract: In a semiconductor device having semiconductor chips, a lower heat sink which is joined on the principal rear surface side of the semiconductor chips and an upper heat sink which is joined on the principal front surface side of the semiconductor chips, wherein substantially the whole device is encapsulated with a molded resin, the thick-walled portion of a resin lying around a mounted portion is provided with holes which are resin-flow hindering portions for hindering the flow of the resin during the molding thereof, whereby air bubbles are prevented from appearing in the resin within the mounted portion.

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Abstract: A semiconductor device and package has a heat spreader directly disposed on the reverse surface of the semiconductor device. This heat spreader includes a diamond layer or a layer containing diamond and ceramics such as silicon carbide and aluminum nitride. The heat spreader is directly formed on a substrate for the semiconductor device. In particular, the heat spreader is composed of a diamond layer and one or two metal or ceramic members, which are bonded to the diamond layer with one or two polymer adhesive layers. This diamond layer has a fiber structure across the thickness or a microcrystalline structure. Cilia are formed on a surface of the diamond layer facing the one or two metal or ceramic members.

Abstract: A switching chip using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink, an insulating substrate and a conductive plate, with a first conductive layer sandwiched in between. Further, a diode chip having a smaller area than a cathode electrode and using a wide gap semiconductor as the base material is located on the cathode electrode which has a smaller area than an anode electrode, with a second conductive layer sandwiched in between. A closed container encloses every structural component except an exposed portion of a bottom surface in the interior space.

Abstract: A semiconductor device includes a glass substrate, a heat sink formed on the glass substrate and a transistor formed on the heat sink. The transistor includes an active layer formed on the heat sink and having a source region, a channel region and a drain region. A gate electrode is placed on the channel region. In addition, the heat sink may operate as additional gate electrode.

Abstract: Numerous embodiments of a heat spreader, comprised of a plurality of downset legs, which provides a simple and lower cost method of forming a heat spreader as compared to conventional methods are disclosed, as well as novel apparatus and methods for attaching the heat spreader to a substrate and a secondary device to the heat spreader, are disclosed.

Abstract: A thermal interposer is provided for attachment to the back surface of a semiconductor device so as to give a very low thermal resistance. In one preferred embodiment, the thermal interposer has two plates containing wick structures such as grooves. The thermal interposer is integrated with a semiconductor device so as to form a vapor chamber. In particular, the back surface of the semiconductor chip is in direct contact with the interior sealed volume of the vapor chamber, so as to greatly reduce the thermal resistance from the combination of the chip and the vapor chamber. Further, the upper plate is thermally coupled to a heat-sinking fixture such as a heat sink or a cold plate.

Abstract: A semiconductor component contains two semiconductor bodies, which are spatially separated from one another and electrically interconnected. A compensation MOS field effect transistor is provided as the first semiconductor body, and a silicon carbide Schottky diode is provided as the second semiconductor body. Consequently, the semiconductor component can advantageously be produced significantly more compactly and more cost-effectively, since both the compensation MOS field-effect transistor and the silicon carbide Schottky diode contribute to a significant reduction of power loss.

Abstract: An electrically pumped optical device includes a semiconductor active region and a backward diode. Both of these structures are located in the current path of the optical device, which is oriented primarily vertically. The active region has a finite extent along at least one lateral dimension. The overall structure improves the electrical performance of the device.

Abstract: A first conductive type layer having a band gap energy smaller than that of an under growth layer formed on a substrate is formed by selective growth from an opening portion formed in the under growth layer, and an active layer and a second conductive type layer are stacked on the first conductive type layer, to form a stacked structure. When such a stacked structure for forming a semiconductor device is irradiated with laser beams having an energy value between the band gap energies of the under growth layer and the first conductive type layer, abrasion occurs at a first conductive type layer side interface between the under growth layer and the first conductive type layer, so that the stacked structure is peeled from the substrate and the under growth layer and simultaneously isolated from another stacked structure for forming another semiconductor device.

Abstract: An integrated circuit includes an electric resistor trace, a substrate and a thermally conductive structure arranged above or below the electric resistor trace for dissipating heat from the electric resistor trace to the substrate. The present invention is based on the finding that by introducing the additional thermally conductive structure, despite the introduction of this additional thermally conductive structure requiring space at first, due to the significantly increased heat conductivity to the substrate, a smaller overall chip area for implementing integrated resistors can be obtained.

Abstract: A sequential mesa type avalanche photodiode (APD) includes a semiconductor substrate and a sequential mesa portion formed on the substrate. In the sequential mesa portion, a plurality of semiconductor layers, including a light absorbing layer and a multiplying layer, are laminated by epitaxial growth. In the plurality of semiconductor layers, a pair of semiconductor layers forming a pn junction is included. The carrier density of a semiconductor layer which is near to the substrate among the pair of semiconductor layers is larger than the carrier density of a semiconductor layer which is far from the substrate among the pair of semiconductor layers. In the APD, light-receiving current based on movement of electrons and positive holes generated in the sequential mesa portion when light is incident from the substrate toward the light absorbing layer is larger at a central portion than at a peripheral portion of the sequential mesa portion.

Abstract: A semiconductor package with an embedded heat spreader (EHS) is proposed, which can be used for the fabrication of a semiconductor package, such as a FCBGA (Flip-Chip Ball Grid Array) package with a heat spreader, and which is characterized by the provision of a plurality of recessed portions, either in the heat spreader attach area of the substrate, or in the support portion of the heat spreader, or in both, so as to allow the fill-in portions of the adhesive layer that are filled in these recessed portions to form anchor structures to benefit the heat spreader against crosswise shear stress. Moreover, since the provision of these recessed portions allows an increase in the contact area of the adhesive layer with the substrate and the heat spreader, it can help increase the adhesive strength to provide the heat spreader more securely adhered in position on the substrate.

Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.

Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).

Abstract: A switching chip (101) using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink (115), an insulating substrate (114) and a conductive plate (108), with a first conductive layer (109A) sandwiched in between. Further, a diode chip (102) having a smaller area than a cathode electrode (103) and using a wide gap semiconductor as the base material is located on the cathode electrode (103) which has a smaller area than an anode electrode (105), with a second conductive layer (109B) sandwiched in between. A closed container (117) encloses every structural component except an exposed portion of a bottom surface (115BS) in the interior space.

Abstract: A microelectromechanical system (MEMS) based sensor comprises: a substrate defining a plane; a first conductive material layer having a first stress, a first portion of the first conductive material layer being connected to the substrate and extending in a substantially parallel direction to the plane defined by the substrate and a second portion being disconnected from the substrate and extending in a substantially non-parallel direction to the plane defined by the substrate; and a sensor material layer formed over at least the second portion of the first conductive material layer, the sensor material layer having a second stress that is less than the first stress of the first conductive material layer. The stresses form a stress gradient that bends the second portion of the first conductive material layer and the sensor material layer formed over the second portion of the first conductive material layer away from the substrate.

Abstract: A switching chip (101) using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink (115), an insulating substrate (114) and a conductive plate (108), with a first conductive layer (109A) sandwiched in between. Further, a diode chip (102) having a smaller area than a cathode electrode (103) and using a wide gap semiconductor as the base material is located on the cathode electrode (103) which has a smaller area than an anode electrode (105), with a second conductive layer (109B) sandwiched in between. A closed container (117) encloses every structural component except an exposed portion of a bottom surface (115BS) in the interior space.

Abstract: A high-density power module package wherein the circuits and a part of chips of the power module are formed on respective substrates such that the circuit patterns are not influenced by the chips. Accordingly, the density of the circuit can be improved so as to save the required area of substrate and production cost.

Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} surface by an angle in an range of 13° to 90° inclusive.

Abstract: Numerous embodiments of a heat spreader, comprised of a plurality of downset legs, which provides a simple and lower cost method of forming a heat spreader as compared to conventional methods are disclosed, as well as novel apparatus and methods for attaching the heat spreader to a substrate and a secondary device to the heat spreader, are disclosed.

Abstract: A mountable microstructure is provided for mounting with high positional accuracy a compound semiconductor element such as a surface emitting laser element engaged under gravity in concavities on an upper surface of a substrate. A surface emitting laser element 2 is formed on an upper surface of a Si block 1 formed at high accuracy in the same shape as concavities on the upper surface of a substrate by Si anisotropic etching. In the case of a surface emitting laser, since problems such as lattice mismatch occur when an epitaxial layer is grown on the Si substrate, the epitaxial layer 14 is grown on for example a GaAs substrate 11, and this is inverted to bond onto an Si substrate 17. Then after forming the surface emitting laser element 2, the Si block is shaped and divided up by anisotropic etching.

Abstract: A light-emitting diode array comprising a conductive layer formed on a substrate, a plurality of separate light-emitting parts formed on the conductive layer, a first electrode formed on at least part of a top surface of each light-emitting part, and a second electrode formed on the conductive layer near the light-emitting part, the second electrode being a common electrode for operating a plurality of the light-emitting parts, and regions of the conductive layer between the adjacent light-emitting parts being removed.

Abstract: A package for an integrated circuit chip adapted to operate at microwave frequencies. The package includes an electrically conductive lead frame having electrical leads extending outwardly from an inner region. A base section is adhesively affixed to a bottom portion of the lead frame. The base section and a plastic cover are configured to provide a cavity when the cover and the base section are affixed with the integrated circuit chip being disposed with such provided cavity. With another integrated circuit chip package, an electrically conductive lead frame has electrical leads adapted for electrical connection to the integrated circuit chip. The base section includes a conductive member nd a dielectric member. The dielectric member has an aperture disposed in registration with an inner region of the lead frame. The conductive member is electrically to a bottom surface portion of the integrated circuit. The integrated circuit chip being disposed in registration with the aperture.

Abstract: There is disclosed a p-n junction diode structure whose electrical characteristics can be affected by the application of pressure or other mechanical stresses that will control sensitivity. The p-n junction consists of two different semiconductor materials, one being of p-type and the other of n-type, both having predetermined crystallographic axes which are fusion bonded together to form a p-n junction. Because of the ability to control the position of the crystallographic axes with respect to one another, one can affect the electrical characteristics of the p-n junction and thereby produce devices with improved operating capabilities such as Zener diodes, tunnel diodes as well as other diodes.

Abstract: An integrated semiconductor circuit including a substrate and at least one microwave circuit area supported by a substrate is provided, at least one cooling area supported by the substrate being provided for cooling the microwave circuit area, the at least one cooling area having electric contacts and regions having different types of doping so that cooling may be accomplished by the Peltier effect.

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: A plurality of semiconductor chips bent along the outer circumferential surface of a cylindrical substrate are mounted to the outer circumferential surface of the substrate. The bumps of these semiconductor chips are connected to connection pads formed on the outer circumferential surface of the substrate. By diminishing the curvature radius of the bent semiconductor chips, the size of the semiconductor module can be made smaller than the size of the chip.

Abstract: Semiconductor memory devices include memory cell transistors having spaced apart memory cell transistor source and drain regions, and a memory cell transistor insulated gate electrode that includes a memory cell transistor gate dielectric layer. Refresh transistors also are provided that are connected to the memory cell transistor insulated gate electrodes and are configured to selectively apply negative bias to the memory cell transistor insulated gate electrodes in a refresh operation. The refresh transistors include spaced apart refresh transistor source and drain regions, and a refresh transistor insulated gate electrode. The refresh transistor insulated gate electrode includes a refresh transistor gate dielectric layer that is of different thickness that the memory cell transistor gate dielectric layer. The refresh transistor gate dielectric layer may be thinner than the memory cell transistor gate dielectric layer.

Abstract: A semiconductor chip is shown containing an integral heat spreading layer that more effectively transmits heat from the die to ambient as a result of spreading the heat out on the die over a larger cross sectional area. Local hot spots are minimized which allows the semiconductor chip to operate at a higher frequency for a given upper threshold temperature. Also shown is a method of manufacturing such a semiconductor chip, and the associated method of cooling a semiconductor chip.