Abstract: A bonded wafer is produced by directly bonding a silicon wafer for active layer and a silicon wafer for support substrate without an insulating film and thinning the silicon wafer for active layer to a given thickness, in which a silicon wafer cut out from an ingot at a cutting angle of 0-0.1° (compound angle) with respect to a predetermined crystal face is used in each of the silicon wafer for active layer and silicon wafer for support substrate.

Abstract: A GaAs semiconductor substrate includes a main surface (10m) having an inclined angle of 6° to 16° with respect to a (100) plane (10a), and a concentration of chlorine atoms on the main surface (10m) is not more than 1×1013 cm?2. Further, a method of manufacturing a GaAs semiconductor substrate includes a polishing step of polishing a GaAs semiconductor wafer, a first cleaning step of cleaning the polished GaAs semiconductor wafer, an inspection step of inspecting a thickness and a main surface flatness of the GaAs semiconductor wafer subjected to the first cleaning, and a second cleaning step of cleaning the inspected GaAs semiconductor wafer with one of an acid other than hydrochloric acid and an alkali.

Abstract: A nitride semiconductor substrate includes two principal surfaces including an upper surface that is a growth face and a lower surface on its opposite side. An FWHM in a surface layer region at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner region at depths exceeding 5 ?m from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane inclined relative to the upper surface.

Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.

Abstract: An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control film is formed to cover part of the active region where the gate electrode is not formed, the isolation region, the top surface of the gate electrode and sidewalls. A pair of stress control regions are formed to sandwich the gate electrode in the gate width direction of the gate electrode. In the stress control regions, the stress control film is not formed, or alternatively, a stress control film thinner than the stress control film formed on the gate electrode is formed.

Abstract: A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.

Abstract: A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.

Abstract: Group III nitride layers have a wide range of uses in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and recently Si(111). For the purpose inter alia of integration with Si-CMOS electronics, growth on Si(001) is indicated, which is possible only with difficulty because of the different symmetries and is currently limited solely to misoriented Si(001) substrates, which restricts the range of use. In addition, the layer quality is not at present equal to that produced on Si(111) material. Growth on exactly oriented Si(001) and an improvement in material quality can now be simply achieved by a modification of the surface structure possible with a plurality of methods.

Abstract: The present invention is a nitride semiconductor device including an n-type gallium nitride single crystal substrate, an epitaxially grown nitride film on the substrate, and electrodes deposited on a top and a bottom of the substrate. In order to produce the substrate, oxygen is doped into a gallium nitride crystal by preparing a C-plane gallium nitride seed crystal or a three-rotationally symmetric plane foreign material seed crystal, supplying material gases including gallium, nitrogen and oxygen to the C-plane gallium nitride seed crystal or the three-rotationally symmetric foreign seed crystal, growing a faceted C-plane gallium nitride bulk crystal having facets of non-C-planes on the seed crystal, maintaining the facets on the C-plane gallium nitride bulk crystal, and eliminating the seed crystal from the bulk crystal.

Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.

Abstract: A capacitor includes a pair of electrodes and a ferroelectric film sandwiched between the electrodes. The electrodes are provided perpendicular to the direction of the polarization axis of the ferroelectric film.

Abstract: The present invention includes a substrate structural body having a high electrostatic chuck force at a low voltage even when an insulated board is used, and a method for manufacturing the substrate structural body. As the substrate structural body, there is provided a substrate structural body for attaining its fixing by an electrostatic chuck mechanism, comprising at least a first polycrystalline silicon film formed on the back surface of a substrate comprised of an insulating material or its back and side surfaces, wherein a top layer of part of the back surface or the back and side surfaces is of a first silicon insulating film.

Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.

Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate (201). In an illustrative implementation, a laser diode is oriented on a GaN substrate (201) wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <1120> or the <1100> family of directions. For a <1120> off-cut substrate, a laser diode cavity (207) may be oriented along the <1100> direction parallel to lattice surface steps (202) of the substrate (201) in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For <1100> off-cut substrate, the laser diode cavity may be oriented along the <1100> direction orthogonal to lattice surface steps (207) of the substrate (201) in order to provide a cleave laser facet that is aligned with the surface lattice steps.

Abstract: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.

Abstract: A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.

Abstract: The channel of a MOSFET is selectively stressed by selectively stressing the silicide layers on the gate electrode and the source/drain. Stress in the silicide layer is selectively produced by orienting the larger dimensions of the silicide grains in a first direction and the smaller dimensions in a second, perpendicular direction, with one of the directions being parallel to the direction of carrier movement in the channel and the other direction being perpendicular thereto.

Abstract: Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing material that stresses the center semiconductor fin region. The strain inducing material contacts the bulk silicon substrate, wherein the strain inducing material comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane <110> direction of the (011) DSB layer is aligned with an in-plane <110> direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane <100> directions of the (001) base substrate, followed by recrystallization using the base substrate as a template.

Abstract: For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.

Abstract: The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.

Abstract: The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

Abstract: A light control device includes: a single crystal substrate (10); an electro-optic thin film (20) which is provided on the single crystal substrate (10) and has an electro-optic effect; and a plurality of electrodes (30, 40) which are provided along a crystal axis of the electro-optic thin film and apply an electrical field along the crystal axis of the electro-optic thin film (20).

Abstract: In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other.

Abstract: It is an object of the present invention to control the plane orientation of crystal grains obtained by using a laser beam, into a direction that can be substantially regarded as one direction in an irradiation region of the laser beam. After forming a cap film over a semiconductor film, the semiconductor film is crystallized by using a CW laser or a pulse laser having a repetition rate of greater than or equal to 10 MHz. The obtained semiconductor film has a plurality of crystal grains having a width of greater than or equal to 0.01 ?m and a length of greater than or equal to 1 ?m. In a surface of the obtained semiconductor film, a ratio of an orientation {211} is greater than or equal to 0.4 within the range of an angle fluctuation of ±10°.

Abstract: Provided is a sintered silicon wafer, wherein the ratio [I(220)/I(111) . . . (1)] of intensity of a (220) plane and intensity of a (111) plane measured by X-ray diffraction is 0.5 or more and 0.8 or less, and the ratio [I(311)/I(111) . . . (2)] of intensity of a (311) plane and intensity of a (111) plane is 0.3 or more and 0.5 or less. The provided sintered silicon wafer has a smooth surface in which its surface roughness is equivalent to a single crystal silicon.

Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

Abstract: A semiconductor light emitting element includes: an {0001} n-type semiconductor substrate formed of a III-V semiconductor, which is in a range of 0° to 45° in inclination angle into a <1-100> direction, and which is in a range of 0° to 10° in inclination angle into a <11-20> direction; an n-type layer formed of a III-V semiconductor on the n-type semiconductor substrate; an n-type guide layer formed of a III-V semiconductor above the n-type layer; an active layer formed of a III-V semiconductor above the n-type guide layer; a p-type first guide layer formed of a III-V semiconductor above the active layer; a p-type contact layer formed of a III-V semiconductor above the p-type first guide layer; and an concavo-convex layer formed of a III-V semiconductor between the p-type first guide layer and the p-type contact layer.

Abstract: Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the centerline of a wafer. Gates are formed adjacent to the semiconductor fins such that they are approximately perpendicular to the centerline. Then, masked implant sequences are performed, during which halo and/or source/drain dopants are implanted into the sidewalls of the semiconductor fins on one side of the chevron layout and then into the sidewalls of the semiconductor fins on the opposite side of the chevron layout. The implant direction used during these implant sequences is substantially orthogonal to the gates in order to avoid mask shadowing, which can obstruct dopant implantation when separation between the semiconductor fins in the chevron layout is scaled (i.e., when device density is increased).

Abstract: When metallic material is employed for various metallic films, it is possible to improve at least one of the mechanical strength, the durability against abrasion, and the uniformess as a film while keeping unchanged the chemical property and the electric property of the metallic material. Due to the gel three-dimensional mesh structure 406, the dislocations 407 of the tangle in the mesh form are introduced in the crystal of the metal 401 at high density; therefore, when the tensile stress 403 is applied thereto, these dislocations slightly shift. As a result, the metal 401 deforms by uniformly dispersing distortion in the order of crystal grains, and hence there does not occur concentration of stress, which leads to the breakage or the severance at the grain interface 402. Therefore, the metallic material of the present invention improves the mechanical strength and the durability against abrasion.

Abstract: A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.

Abstract: A nitride semiconductor light emitting device includes a nitride semiconductor multilayer film. The nitride semiconductor multilayer film is formed on a substrate and made of nitride semiconductor crystals, and includes a light emitting layer. In the nitride semiconductor multilayer film, facets of a cavity are formed, and a protective film made of aluminum nitride crystals is formed on at least one of the facets. The protective film has a crystal plane whose crystal axes form an angle of 90 degrees with crystal axes of a crystal plane of the nitride semiconductor crystals constituting the facet of the cavity having the protective film formed thereon.

Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.

Abstract: A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <110> crystal orientation, and channels are located at sidewall of the semiconductor layer, a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second <110> crystal orientation perpendicular to the curre

Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface.

Abstract: A method for manufacturing a device includes forming trenches of different morphologies into a substrate. At the upper surfaces, the trenches have different orientations with respect to each other. In an aspect, windows for the trenches are aligned along the <100> and <110> directions of a silicon substrate. The trenches of different morphologies may be formed into capacitors having different capacitance levels. Also included are devices prepared by the method.

Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.

Abstract: A semiconductor device is provided that includes a semiconductor substrate, an n-channel MOSFET formed on the substrate and a p-channel MOSFET formed on the substrate. A first layer is formed to cover the n-channel MOSFET, wherein the first layer has a first flexure-induced stress. A second layer is formed to cover the p-channel MOSFET, wherein the second layer has a second flexure-induced stress.

Abstract: A structural element having a region of porous silicon or porous silicon oxide, which was obtained from a porization, starting from an edge area of the region, in at least largely crystalline silicon. Relative to the edge area, the crystalline silicon has a crystal orientation that has an orientation that differs from a <100> orientation or from an orientation that is equivalent for reasons of symmetry. This structural element is suited for use in a mass-flow sensor, in a component for the thermal decoupling of sensor and/or actuator structures, or a gas sensor. Furthermore, methods for setting the thermal conductivity of a region of porous silicon or porous silicon oxide of a structural element are described.

Abstract: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.

Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

Abstract: To provide a semiconductor device that can effectively suppress the short channel effect without deterioration of carrier migration, an impurity ion is added from a direction of the <110> axis with respect to a silicon substrate on forming a punch through stopper under the gate electrode. In this invention, because the addition of the impurity is conducted by utilizing the principal of channeling, the impurity can be added with a small amount of scattering suppressing damage on the surface of the silicon substrate. A channel forming region having an extremely small impurity concentration and substantially no crystallinity disorder is formed.

Abstract: Disclosed herein is a high-quality group III-nitride semiconductor thin film and group III-nitride semiconductor light emitting device using the same. To obtain the group III-nitride semiconductor thin film, an AlInN buffer layer is formed on a (1-102)-plane (so called r-plane) sapphire substrate by use of a MOCVD apparatus under atmospheric pressure while controlling a temperature of the substrate within a range from 850 to 950 degrees Celsius, and then, GaN-based compound, such as GaN, AlGaN or the like, is epitaxially grown on the buffer layer at a high temperature. The group III-nitride semiconductor light emitting device is fabricated by using the group III-nitride semiconductor thin film as a base layer.

Abstract: A light emitting diode includes a substrate tilted toward first and second directions simultaneously, a first cladding layer formed with a semiconductor material of a first conductive type on the substrate, an active layer formed on the first cladding layer, and a second cladding layer formed with a semiconductor material of a second conductive type on the active layer, wherein concavo-convexes are formed on the interfaces of the first cladding layer, the second cladding layer, and the active layer, and the (100) substrate is a III-V or a IV-IV group semiconductor substrate, and has a crystal orientation such that a (100) plane of the (100) substrate is inclined 2 to 20° toward the [0-1-1] direction and 1 to 8° toward the [0-11] direction.

Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

Abstract: A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction.

Abstract: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.