Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.

Abstract: A three-dimensional memory device includes a first-tier structure containing a first alternating stack of first insulating layers and first electrically conductive layers that has first stepped surfaces, and a first retro-stepped dielectric material portion contacting the first stepped surfaces of the first alternating stack, and a second-tier structure containing a second alternating stack of second insulating layers and second electrically conductive layers that has second stepped surfaces, and a second retro-stepped dielectric material portion contacting the second stepped surfaces of the second alternating stack. The first retro-stepped dielectric material portion has a higher etch rate than the second retro-stepped dielectric material portion. Memory stack structures vertically extend through the first alternating stack and the second alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel.

Abstract: An integrated circuit and method with a delamination free opening formed through multiple levels of polymer dielectric. The opening has a vertical sidewall and no interface between adjacent levels of polymer dielectric is exposed on the vertical sidewall.

Abstract: A package structure is provided, which includes: a first polymer layer with a first surface; a second polymer layer with a second surface on the first polymer layer; a circuit device with opposing third and fourth surfaces, the circuit device disposed on the second polymer layer and with multiple metal pads on the fourth surface; a first high-filler dielectric layer enclosing the circuit device and the second polymer layer and covering the first polymer layer; a first conductive wiring formed on the first high-filler dielectric layer; a first conductive passage formed in the first high-filler dielectric layer and connecting the first conductive wiring to the metal pads; a second high-filler dielectric layer enclosing the first conductive wiring and covering the first high-filler dielectric layer; and a second conductive passage formed in the second high-filler dielectric layer and connecting the first conductive wiring to an external circuit.

Abstract: A method for manufacturing a filling planarization film, the method including: a first coating step of applying a first coating liquid, containing a polyamine and a first solvent, to a region including a recessed part of a member having the recessed part, to fill the first coating liquid into the recessed part; and a second coating step of applying a second coating liquid, containing an organic substance having two or more carboxyl groups and a second solvent having a boiling point of 200° C. or less and an SP value of 30 (MPa)1/2 or less, to the region including the recessed part of the member into which the first coating liquid has been filled.

Abstract: The present invention provides a composition for forming a coating type BPSG film, which comprises: one or more structures comprising a silicic acid represented by the following general formula (1) as a skeletal structure, one or more structures comprising a phosphoric acid represented by the following general formula (2) as a skeletal structure and one or more structures comprising a boric acid represented by the following general formula (3) as a skeletal structure. There can be provided a composition for forming a coating type BPSG film which is excellent in adhesiveness in fine pattern, can be easily wet etched by a peeling solution which does not cause any damage to the semiconductor apparatus substrate, the coating type organic film or the CVD film mainly comprising carbon which are necessary in the patterning process, and can suppress generation of particles by forming it in the coating process.

Abstract: The present invention relates to a process for the production of solar cells comprising a selective emitter using an improved etching-paste composition which has significantly improved selectivity for silicon layers.

Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.

Abstract: A light-emitting device includes a substrate, a plurality of light-emitting elements mounted on one surface of the substrate, a first glass film provided to one surface of the substrate and having a plurality of apertures that form a light-reflecting frame surrounding the perimeter of each the light-emitting elements, and a second glass film provided to the other surface of the substrate. A coefficient of thermal expansion of the second glass film is greater than that of the substrate when a coefficient of thermal expansion of the first glass film is greater than that of the substrate, and a coefficient of thermal expansion of the second glass film is less than that of the substrate when a coefficient of thermal expansion of the first glass film is less than that of the substrate.

Abstract: The present invention discloses a semiconductor device, which comprises: a substrate, and a shallow trench isolation in the substrate, characterized in that, the semiconductor device further comprises a stress release layer between the substrate and the shallow trench isolation. In the semiconductor device and the method for manufacturing the same according to the present invention, the stresses accumulated during the formation of the STI can be released by interposing the stress release layer made of a softer material between the substrate and the STI, thereby reducing the leakage current of the substrate of the device and improving the device reliability.

Abstract: A photosensitive glass paste that can be fired at a low temperature for a short period of time and that can suppress generation of voids and diffusion of Ag in glass layers formed by firing, and a high-performance multilayer wiring chip component manufactured by using the above photosensitive glass paste are provided. As a sintering aid glass which is combined with a ceramic aggregate and a primary glass, a glass having a contact angle to the ceramic aggregate smaller than that of the primary glass to the ceramic aggregate is used, and the content of the sintering aid glass is set to 5 to 10 percent by volume of the inorganic component. As the sintering aid glass, a glass containing SiO2, B2O3, CaO, Li2O, and ZnO at a predetermined ratio is preferably used. As the primary glass, a glass containing 70 to 90 percent by weight of SiO2, 15 to 20 percent by weight of B2O3, and 1 to 5 percent by weight of K2O can be used.

Abstract: A glass to be used in a scattering layer of an organic LED element, and an organic LED element using the scattering layer are provided. The organic LED element of the present invention includes, a transparent substrate, a first electrode provided on the transparent electrode, an organic layer provided on the first electrode, and a second electrode provided on the organic layer, and further includes a scattering layer including, in terms of mol % on the basis of oxides, 15 to 30% of P2O5, 5 to 25% of Bi2O3, 5 to 27% of Nb2O5, and 10 to 35% of ZnO and having a total content of alkali metal oxides including Li2O, Na2O and K2O of 5% by mass or less.

Abstract: A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A first spin-on-dielectric layer is formed over a semiconductor substrate. An abnormal oxidation of the first spin-on-dielectric layer is carried out. A surface of the first spin-on-dielectric layer is removed. A second spin-on-dielectric layer is formed over the first spin-on-dielectric layer. A non-abnormal oxidation of the first and second spin-on-dielectric layers is carried out to modify the second spin-on-dielectric layer without modifying the first spin-on-dielectric layer.

Abstract: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.

Abstract: A ceramic electronic component has a chip element body having a conductor arranged inside, external electrodes, and a discrimination layer. The chip element body has first and second end faces facing each other, first and second side faces being perpendicular to the first and second end faces and facing each other, and third and fourth side faces being perpendicular to the first and second end faces and to the first and second side faces and facing each other. The external electrodes are formed on the first and second end faces, respectively, of the chip element body. The discrimination layer is provided on at least one side face out of the first side face and the second side face in the chip element body. The chip element body is comprised of a first ceramic. The discrimination layer is comprised of a second ceramic different from the first ceramic and has a color different from that of the third and fourth side faces.

Abstract: In order to provide an adhesive composition for electronic components that is excellent in adhesion durability under long-term high temperature conditions, thermal cyclability, and insulation reliability, designed is an adhesive composition for electronic components containing a thermoplastic resin (a), an epoxy resin (b), a hardener (c), and an organopolysiloxane (d), wherein the glass transition temperature (Tg) after curing is ?10° C. to 50° C. and the rate of change of Tg after heat-treating the composition at 175° C. for 1000 hours is 15% or less.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

Abstract: A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) layer on the top wiring patterns to fill a gap between the top wiring patterns, and coating a SOG layer on the substrate on which the primary USG layer has been deposited. Next, the SOG layer on the surface of the substrate may be removed until the primary USG layer is exposed, and a secondary USG layer may be deposited on the substrate on which the primary USG layer has been exposed.

Abstract: The present invention is directed to low-cost, low-processing temperature, and simple reinforcement, repair, and corrosion protection for hermetically sealed modules and hermetic connectors. A thin layer of glass is applied over the module's seal or the connector' glass frit. The layer of glass comprises an alkali silicate glass. The layer of glass is produced from a material which is a low viscosity liquid at room temperature prior to curing and is cured at low temperatures (typically no more than about 160 degrees Celsius). Subsequent to curing, the layer of glass is intimately bonded to the seal, watertight, and is stable from about negative two-hundred forty-three degrees Celsius to at least about seven-hundred twenty-seven degrees Celsius. The glass layer provides corrosion protection, seals any existing leaks, and possesses good flexibility and adhesion. The resulting bond is hermetic with good aqueous durability and strength similar to that of monolithic structures.

Abstract: A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.

Abstract: During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 ? to about 500 ?, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

Abstract: An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

Abstract: An anodic bonding apparatus includes a first electrode and a second electrode. The first electrode has a first surface, and the second electrode has a second surface facing the first surface. The first surface includes a first central area; a first substrate placing area for placing a laminated substrate; and a first peripheral area surrounding the first substrate placing area. The second surface includes a second central area corresponding to the first central area; a second substrate placing area surrounding the second central area; and a second peripheral area corresponding to the first peripheral area and surrounding the second substrate placing area. Further, the second electrode includes a curved portion curved toward the first electrode, so that a distance between the first central area and the second central area becomes smaller than a distance between the first peripheral area and the second peripheral area.

Abstract: A semiconductor device having improved adhesiveness between films composing an interlayer insulating film is presented by providing multilayered films in the interlayer insulating films having film density distribution, in which the film density is gradually changes. A SiOC film is deposited to a thickness of 300 nm via a plasma CVD process, in which a flow rate of trimethylsilane gas is stepwise increased. In this case, the film density of the deposited SiOC film is gradually decreased by stepwise increasing the flow rate of trimethylsilane gas. Since trimethylsilane contains methyl group, trimethylsilane has more bulky molecular structure in comparison with monosilane or the like. Thus, the film density is decreased by increasing the amount of trimethylsilane in the reactant gas.

Abstract: A spin on glass SOG layer 30 is formed, then a PECVD barrier layer 40 over the SOG layer. Holes 50 in the SOG layer for vias are formed with a wine glass profile, so that in a peripheral region around the periphery of the holes, the barrier layer is thinner or absent, and ion implantation is performed substantially perpendicular to the layers, to reach the SOG layer through the barrier layer preferentially in the peripheral region. This enables the implantation to be concentrated on the peripheral region, without the need for implantation at a high angle and wafer rotation. This enables the manufacturing process to be simplified and hence costs reduced. By concentrating the implantation in the peripheral region where it can reduce moisture transfer to material in the holes, there is less risk of deplanarization due to the SOG shrinkage associated with ion implantation.

Abstract: A dielectric composition for forming a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like, the composition including at least two fluoropolymers and two inorganic fillers. A circuitized substrate including at least one such dielectric layer and at least one conductive layer thereon is also provided.

Abstract: A method of simultaneously bonding components, comprising the following steps. At least first, second and third components are provided and comprise: at least one glass component; and at least one conductive or semiconductive material component. The order of stacking of the components is determined to establish interfaces between the adjacent components. A hydrogen-free amorphous film is applied to one of the component surfaces at each interface comprising an adjacent: glass component; and conductive or semiconductive component. A sol gel with or without alkaline ions film is applied to one of the component surfaces at each interface comprising an adjacent: conductive or semiconductive component; and conductive or semiconductive component. The components are simultaneously anodically bonded in the determined order of stacking.

Abstract: A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) layer on the top wiring patterns to fill a gap between the top wiring patterns, and coating a SOG layer on the substrate on which the primary USG layer has been deposited. Next, the SOG layer on the surface of the substrate may be removed until the primary USG layer is exposed, and a secondary USG layer may be deposited on the substrate on which the primary USG layer has been exposed.

Abstract: In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and comprising an upper corner at a periphery of the opening, the upper corner having a corner angle with a first degree of sharpness; b) reducing the sharpness of the corner angle to a second degree; c) after reducing the sharpness, forming a layer of material within the opening and over the etch-stop layer; and d) planarizing the material with a method selective for the material relative to the etch-stop layer to remove the material from over the etch-stop layer while leaving the material within the opening.

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract: There is disclosed a coating material formulation for layering a plurality of electrodes to provide a substrate for the electrochemical synthesis of organic oligomers. Specifically, there is disclosed a coating layer of from about 0.5 to about 100 microns thick and is composed of a mixture of controlled porosity glass (CPG) particles having an average particle size of from about 0.25 to about 25 microns, and a thickening agent.

Abstract: Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.

Abstract: The method for forming a flowable dielectric layer without micro-voids therein in a semiconductor device is employed to utilize a ultra-violet (UV) bake process. The method includes steps of: forming a plurality of patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out a baking process for densifying the flowable dielectric layer from a bottom face thereof; forming a plurality of contact holes by selectively etching the flowable dielectric layer; carrying out a pre-cleaning process in order to remove native oxide and impurity substances on the contact holes; and forming a plurality of contact plugs by filling a conductive material into the contact holes.

Abstract: Environmental sensors and other bodies, together with associated lead wires, are mounted to a oxidizable substrate for high temperature applications by means of a reacted borosilicate mixture (RBM) that secures the body relative to the substrate via of an oxide interface formed between the RBM and substrate during a high temperature reaction process. An oxide interface is also formed with oxidizable bodies to provide further mounting strength. The RBM is a B2O3—SiO2 mixture, with the B2O3 portion a function of the reaction temperature and desired bonding strength and viscosity.

Abstract: A liquid crystal display device comprises a liquid crystal display panel and a semiconductor integrated circuit for driving and controlling the liquid crystal display panel. The number of input/output wires connected to I/O terminals (bonding pads) of the semiconductor integrated circuit is reduced so as to simplify wiring patterns of the I/O wires, whereby degrees of freedom in arranging the I/O wiring patterns are enhanced. The panel has a pair of insulating substrate, and the semiconductor integrated circuit is mounted on one of the paired substrates. The semiconductor integrated circuit has a mode terminal which is fixed to a power supply potential or to a reference potential during operation of the integrated circuit, and power supply dummy terminals connected to the power supply potential or reference potential inside the semiconductor integrated circuit. The wiring patterns formed on the paired insulating substrates connect the mode terminal to the power supply dummy terminals.

Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

Abstract: A fluorine-doped silica glass (FSG) dielectric layer includes a number of sublayers. Each sublayer is doped with fluorine in such a way that the doping concentration of fluorine in the sublayer decreases as one moves from an interior region of the sublayer towards one or both of the interfaces between the sublayer and adjacent sublayers. This structure reduces the generation of HF when the layer is exposed to moisture and thereby improves the stability and adhesion properties of the layer. The principles of this invention can also be applied to dielectric layers doped with such other dopants as boron, phosphorus or carbon.

Abstract: A chip electronic component including a ceramic element and terminal electrodes with metal coating thereon formed on the surface of the ceramic element. A glass layer is formed on a part of the surface of the ceramic element where the terminal electrodes are not formed. A glass material for the glass layer contains at least two species of alkali metal elements selected from Li, Na and K, and the total amount of the alkali metal elements is greater than or equal to 20 atomic percent of the total amount of elements except oxygen contained in the glass material.

Abstract: A thermal activated SACVD method for depositing a phosphorus oxide layer onto a silicon oxide wafer comprising the steps of: loading an SACVD device with a silicon oxide wafer; depositing a phosphorus doped oxide (PSG) layer on the USG layer using pure oxygen and a phosphorus and silicon source; purging the SACVD device; and depositing a boron and phosphorus doped oxide (BPSG) layer on the PSG layer.

Abstract: A method of manufacturing MEMS structures and devices that allows the fabrication of dielectric structures with improved etch selectivity and good electrical leakage characteristics. The dielectric structure includes a composite stack of silicon nitride sub-layers with a silicon-rich nitride sub-layer and a stoichiometric silicon nitride sub-layer at opposite ends of the stack. Alternatively, the dielectric structure includes a single silicon nitride layer providing a graded change in silicon content through the dielectric layer, from silicon-rich nitride to stoichiometric silicon nitride.

Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.

Abstract: The present invention relates to nanoporous dielectric films and to a process for their manufacture. A substrate having a plurality of raised lines on its surface is provided with a relatively high porosity, low dielectric constant, silicon containing polymer composition positioned between the raised lines and a relatively low porosity, high dielectric constant, silicon containing composition positioned on the lines.

Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

Abstract: A photoelectric conversion device is provided, which comprises: a substrate serving as an electrode; numerous crystalline semiconductor particles containing a first conductivity-type impurity deposited on the substrate to join thereto; an insulator provided among the crystalline semiconductor particles; and a semiconductor layer containing an impurity of the opposite conductivity-type to which another electrode is connected, which semiconductor layer being provided over the crystalline semiconductor particles, wherein the crystalline semiconductor particles comprise silicon, and the insulator comprises a glass material which contains at least 1 wt % and at most 20 wt % tin oxide. By this arrangement, it is possible to form a good insulator capable of filling spaces among the crystalline semiconductor particles and preventing defects such as cracking, bubbling and abnormal deposition from occurring, and consequently to provide a photoelectric conversion device with high reliability at low cost.

Abstract: A colloidal suspension of nanoparticles composed of a dense material dispersed in a solvent is used in forming a gap-filling dielectric material with low thermal shrinkage. The dielectric material is particularly useful for pre-metal dielectric and shallow trench isolation applications. According to the methods of forming a dielectric material, the colloidal suspension is deposited on a substrate and dried to form a porous intermediate layer. The intermediate layer is modified by infiltration with a liquid phase matrix material, such as a spin-on polymer, followed by curing, by infiltration with a gas phase matrix material, followed by curing, or by curing alone, to provide a gap-filling, thermally stable, etch resistant dielectric material.

Abstract: A method of forming a film having enhanced reflow characteristics at low thermal budget is disclosed, in which a surface layer of material is formed above a base layer of material, the surface layer having a lower melting point than the base layer. In this way, a composite film having two layers is created. After reflow, the surface layer can be removed using conventional methods.

Abstract: A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.

Abstract: A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate. The introducing of precursors is performed in molar ratios consistent with formation of glass films and may comprise an atomic level chemical vapor deposition of La2O3 and Al2O3 using ratios between 20%-50% La2O3 and 50%-80% Al2O3.

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.