Details Of Insulating Layer Electrical Charge (e.g., Negative Insulator Layer Charge) Patents (Class 257/651)
  • Multilayer metallization for silicon semiconductor devices including a diffusion barrier formed of amorphous tungsten/silicon
    Patent number: 5369300
    Abstract: A semiconductor device aluminum-containing metallization system that is particularly useful for integrated circuits (ICs) having P-type contact regions and also having a likelihood of extended exposure to elevated temperatures. Use of an aluminum/silicon diffusion barrier formed of an amorphous tungsten/silicon on such ICs is made commercially practical. A titanium or transition metal silicide layer is disposed beneath the amorphous tungsten/silicon layer, to consistently provide durable low resistance electrical contacts to P-type regions of the IC.
    Type: Grant
    Filed: June 10, 1993
    Date of Patent: November 29, 1994
    Assignee: Delco Electronics Corporation
    Inventors: Robert J. Heideman, Randy A. Rusch, Michael S. Baird
  • Positive working polyamic acid/imide photoresist compositions and their use as dielectrics
    Patent number: 5336925
    Abstract: Positive working polyamic acid photoresist compositions are disclosed having improved high resolution upon image development and exhibiting stable photosensitivity and superior dielectric performance. The compositions comprise polyamic acid condensation products of an aromatic dianhydride and an aromatic di-primary amine wherein a percentage of the diamine comprises special dissolution inhibiting monomers. The compositions may be further improved by the presence of particular supplemental additives.
    Type: Grant
    Filed: January 29, 1992
    Date of Patent: August 9, 1994
    Assignee: Brewer Science, Inc.
    Inventors: Mary G. Moss, Terry Brewer, Ruth M. Cuzmar, Dan W. Hawley, Tony D. Flaim
  • High frequency JFET
    Patent number: 5321283
    Abstract: The junction field effect transistors (JFETs) of this invention have improved breakdown voltage capability, reduced on-resistance and improved overdrive capability. The JFET on-resistance is decreased by ion-implanting an insulating layer covering a layer that contains the source and gate regions of the unipolar transistor. The charge of the implanted ions is the same as the charge polarity of the gate regions. To improve the overdrive capability of a JFET a region of conductivity opposite to the conductivity of the gate region is formed in the gate region of the transistor. This region of opposite conductivity creates another junction within the gate region i.e., the junction between the region of opposite conductivity and the gate region, and the junction between the gate region and the layer containing the gate region.
    Type: Grant
    Filed: July 30, 1991
    Date of Patent: June 14, 1994
    Assignee: MicroWave Technology, Inc.
    Inventors: Adrian I. Cogan, Neill R. Thornton
  • Oxides and nitrides of metastabale group IV alloys and nitrides of Group IV elements and semiconductor devices formed thereof
    Patent number: 5241214
    Abstract: A process and resultant devices is described for forming MOSFET, CMOS and BICMOS devices of Group IV alloys, in particular Si.sub.x Ge.sub.1-x wherein 0<x<1, using ion beam oxidation (IBO) or ion beam nitridation (IBN) by CIMD to form insulators of the Group IV alloys.
    Type: Grant
    Filed: April 29, 1991
    Date of Patent: August 31, 1993
    Assignee: Massachusetts Institute of Technology
    Inventors: Nicole Herbots, Olof C. Hellman, Olivier P. J. Vancauwenberghe